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Explain different features of Pentium. How is pipelining supported in the floating point unit of Pentium How Pentium services interrupts in real mode? What is the privilege level of an application program, if it is running in real mode? Why? What is ! in Pentium processor? How is it useful? Explain With help of neat diagram, explain how data " operand is stored in register file #$tac%& of floating point unit of the Pentium $tate the super'scalar features of the Pentium (ompare )eal mode and Protected *ode of Pentium What is use of +,+! pin? +s it same as reset pin functionally Explain pin functions +- ii& )./ iii& (P-!/P iv& +0 Which features ma%e Pentium a super scalar processor? 1ive details of every feature. 3ist features of real *ode of Pentium Processor Explain 4unctions of 544 and E6 E7 pins ---000--Explain function of the following pins8 i& 9.$( ii& 9P iii& P :;8<= iv& (P-!/P v& )E> With help of neat diagram, Explain Pentium 9rchitecture How physical address is generated in the Pentium? +s the programmer allowed to use all the instructions and registers, When Pentium operates in the real mode? Ela@orate Explain the following8 +& E6' E7 ii& )./ iii& +E)) $tate and explain pairing rules for instructions in Pentium. Which features of the Pentium can @e called )+$( feature? 1ive .etails. Explaining pipelining in the Pentium processor. How is .ata cache organiBed in the Pentium? With help of neat @loc% diagram, explain the architecture of Pentium Processor Explain 9.$ and ,9 pins of the Pentium Processor What is @ranch prediction in Pentium Processor ---000--What are different memory type addressing modes of the Pentium? Explain, 1ive one example each .ifferentiate @etween pipelined and non pipe lined @us cycles of

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Pentium What are the different steps followed @y Pentium processor in Power up? Explain various addressing modes of Pentium processor, 1ive one example each, What is the significance of ()6 and (); registers in the Pentium? Explain initialiBation process of Pentium. .raw non'pipelined write cycle with one wait state Which are the protected mode )egisters in Pentium? Explain their use. How can you ma%e the Pentium processor enter into s'lf t'st? Explain With help of @loc% diagrams explain how Pentium addresses ;<,?6,2 @it memories .raw non'pipelined read cycle of Pentium Processor ---000--When does the Pentium processor ta%es up uilt in $elf !est? What are the advantages of this test? With the help of a neat diagram, Explain pipelined @us (ycle of the Pentium .raw and explain E4391$ register of the Pentium. ,ame and explain 4 Protected mode instructions of the Pentium Processor With help of neat diagram, explain the non pipelined read @us cycle of the Pentium ,ame protected mode registers of the Pentium What are the !ests performed when +,+! pin is asserted with )E$E! pin? What do you mean @y @us cycle? How are pipelined us'(ycles different than non'pipelined us cycles? Explain Explain different data types supported @y Pentium processor. How are ;< , ?6 ,2 @it memories interfaced to the Pentium Processor ? .raw a neat @loc% diagram? What is DcoldE and DwarmE )eset of the Pentium processor? Explain the operations performed immediately after the )eset $ignal is activated. ---000--.ifferentiate @etween segmentation in Protected mode and $egmentation in )eal *ode What is !3 ? How is it useful in Paging? What are page directories and Page ta@les? What are their siBes? Where are they located"

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What are the selectors in Pentium? Explain their use in $egmentation. $tate privilege level rule for +"5 access, if Pentium is acting in Protected mode -nder what circumstances application program need to change privilege levels? What are different techniFues used for changing Privilege levels? .ifferentiate @etween system descriptors and non'system .escriptors. How does Pentium recogniBe these descriptors? 1ive format of non'system descriptor. 9lso name four system descriptors along with their use. 1ive details of four instructions, which are related to segmentation or Pentium in protected mode. Explain the process of linear to physical address translation for 4 * pages. 9lso name and draw formats of .escriptors and registers used for this translation. How protection is provided at segmentation level in Pentium .ifferentiate @etween +0! +.!. ---000--With the help of descriptor format, explain the different fields used to provide protection to a segment. Explain 3inear to Physical address translation of Pentium What is 3.! descriptor? .escri@e its use in protected mode of Pentium Explain < instructions related to Paging unit of Pentium. What can @e siBes of pages in Pentium? How Pentium protects those pages? Explain the process of translation of logical address to 3inear address, With the help of a neat diagram and related registers and structure. What is !3 ? Where is it situated? How is it organiBed? What is its use? What are the system descriptors in Pentium. ,ame them and descri@e their use in Protected *ode What is (P3, .P3, )P3? What is 1.!8 How is it useful in logical to linear address translation in Pentium. Explain with help o nest diagram '''xxx''' (ompare )eal mode with Protected mode on following features i& Privilege level ii&+nterrupt handling iii&+5P3 iv& +nstructions allowed to @e used ,ame and descri@e descriptors used in multitas%ing ,ame instructions used for performing a tas% switch. Explain the

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significance of +)E! instruction in tas% switching How Pentium enters and leave 0irtual *ode What are error codes? What is their use? Ela@orate What is multitas%ing? How pentium supports this feature? What registers, descriptors are involved? How virtual mode is different from protected mode? What information is pushed on the stac%, When +$) is at different privilege level and reFuires error code What is !as% )egister? Which mode of Pentium ma%es use of this )egister and how? Explain in .etail. What privilege levels are performed when any +"5 access is done @y Pentium Processor in protected *ode? +f this chec% fails , is there any alternative the processor will have to continue +"5 access? 3ist features of virtual mode in Pentium Processor. How pentium enters into 0irtual *ode? '''xxx''' What is !$$ ? Where is it 3ocated? How is it useful in *ultitas%ing What do you mean @y !rap , 4ault, 9@ort? Explain Explain use of 3!) +nstruction. .ifferentiate @etween !$$ .escriptor and !as% 1ate .escriptor. Where are they found? How are they useful to Pentium processor? Explain .ifferentiate @etween )eal *ode and 0irtual *ode. What are different types of exceptions? Explain @y giving one example of each. How are interrupts handled in 0irtual *ode? Explain What is D ac% lin%E? Where is it situated? What is its use? What type of descriptors found in +.!? .ifferentiate @etween them. 9lso give their applications. What is !$$? What it (ontains? How is it useful in multitas%ing in Pentium Processor? Explain. What are sources of interrupts in Pentium Processor ? How interrupts are handled in )eal *ode? Will it @e different if Pentium Processor is in Protected mode? Explain with help of neat diagrams. '''xxx''' ,ame $4) Gs found in 26A? microcontroller Explain the function of the following pins of 26A? u( i& E9 ii&H!93? iii& P$E, iv& !6 +nterface 4I )9* to 26A? microcontroller. ,ame it addressa@le $4)Js in 26A? u( Write an instruction to clear the @it which has address 66?h.

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What is count value to @e loaded in !H? and !3? if delay of ? msec is to @e generated? 9ssume oscillator freFuency of ?< *hB and !+*E) ? in *5.E n?. What is idle mode of 26A? u(? Write a program in 26A? 9ssem@ly 3anguage to H5) two @its. 9ssume those @its are in it addressa@le area. How 26A? u( differentiates external program memory and external data memory read and write operations? Explain different modes of serial part in 26A?? 9lso give details of aud )ate in every mode. Write 26A? instructions to8 i& )ead from external program memory at address 6<66h. ii& Write to external program memory at address 6666h What are the different addressing modes of 26A? u(? 1ive two examples of each. Write 26A? 93P to send one @yte of data serially with @aud rate of ?<66. 5scillator 4reF ?< *hB, 9ssume suita@le mode for serial port. '''xxx''' Explain on'chip features of 26A? u(. Where )$6 and )$? @its are found in 26A?? What is their use? Explain different modes supported @y serial port of 26A?. How do you program aud )ates for programma@le modes of serial P5)!? What is maximum siBe of program memory and data memory can @e connected to 26A? u(? Which pins " $ignals are used for this purpose? What are the different sources of interrupts and vectors allocated in 26A?? 9lso name $4)Js involved in interrupt structure of 26A? ,ame 4 @it addressa@le instructions of 26A? What is use of !6 pin of 26A?? When is it used? Explain What are the different sources of interrupts of 26A?? How are interrupts handled in 26A?? Write 26A? program to generate continuous interrupt every ?66usec? 9ssume cloc% freF ?< *HB. .raw the memory map of 26A? u(. What is it addressa@le area? How many its are addressa@le? What are the uses of $4)Js? +t is said num@er of !imers and (ounters in 26A? is !hree? When this is Possi@le? Explain. What are power saving modes of 26A?? '''xxx''' ,ame and explain the different (P- registers of P+( ?6(6?"7?

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Explain indirect addressing mode of P+( ?6(6?"7? What is ()34 in P+( ?6(6?"7? Explain features of P+( ?6(6?"7? Explain following instructions i& clrf !)+$9 ii&@tfsc $!9!-$ , A ii&movlw 6x<A What is prescaler in P+( ?6(6?"7? Explain features of P+( ?6(6?"7? What is (3)W.!? Explain its significance Explain different addressing modes of P+( ?6(6?"7? With help of neat diagram explain memory organiBation of P+( ?6(6?"7?. 1ive details of Program memory and .ata memory Explain following instructions i& @cf f , @ ii&comf f, 4#W& Explain Watchdog timer found in P+( ?6(6?"7? '''xxx''' .raw and explain memory map of P+( ?6(6?"7? How many +"5 ports are found in P+( ?6(6?" difference @etween P+( ?6(6? and ?6(7?7?? How do you configure them as input or output? What is (3)W.!? 1ive details What is architectural difference @etween P+( ?6(6? and ?6(7? Explain different addressing modes of P+( ?6(6?"7? with one example each. What are the sources of interrupts in P+( ?6(6?"7?? How are they recogniBed? How are they serviced? 1ive details. 1ive details of different (P- registers of ?6(6? P+( Explain the following i&H5) W I ii& incf 4#W& .ifferentiate @etween P+( ?6(6? and P+( 6?42HH u(Js. How many interrupts does P+( 6?(6? and P+( 6?(7? support? With help of neat diagram explain interrupt structure of P+( ?6(6?. How many !imers does P+( 6? ( 6? " 7H contain? Explain !imer6 operation in .etail. Write P+( ?6(6? 93P to configure )96, )9? , )9< as output and )9; as input P5)! lines.

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