FLIP-FLOP

Introduction Gates are decision-making elements. We have seen how various combinational circuits are designed using gates. However, decision-making elements are not enough. We also require memory elements - devices, which can store Bits. Flips- Flops are the basic building blocks of these memory devices. A Flip- Flop is a bi-stable device - it has got two stable states. Consider the circuit in Figure1 in / which two NOT circuits are cross - coupled. The outputs of the two NOTs are labeled Q & Q because they will be complementary as explained below:

Let us assume the input of NOT gate 1 is at logic 0, so its output will be at logic 1. And since Q is at logic1, the input of NOT gate 2 is at logic 1 and so its output Q will be at logic 0. Since Q is the / output of NOT gate 1, our assumption is justified. Therefore, Q = 0 & Q = 1 is one stable state of the system. However, if we change our hypothesis and pre-assume input of NOT gate 1 is at / nd logic 1, then Q will be 0 and Q will be 1. This is the 2 . stable state of the system. It can remain in any of the two stable states indefinitely. The above device however lacks the facility of having any control terminal that can change the outputs from one stable state to the other. The term Flip-Flop really means to switch back and forth. It has got another name: latch, which in Bengali means talla . A talla can be either locked (closed) or unlocked (open). And to facilitate this mechanism we also require a key or a chabbi . A talla is useless unless you have a chabbi.! S- R Flip- Flop Figure 2 shows one way to build up an S-R Flip-Flop using NOR gates. The input or the control / terminals are labeled S & R. The complementary outputs are marked Q & Q as before. The input output relations can now be described with reference to Table-1. Start with second row of Table-1 for which the S input is kept at logic 0 while the R input is kept at logic1. Since R = 1, the NOR gate N2 will be disabled with respect to its other input and the output Q will be always zero whatever be the logic state of its other input. However, as the S input is kept at logic 0, the NOR gate N1 remains enable; so its second input will decide the output state. As the output of gate 2 i.e. Q is the second input of N1, and Q is at logic 0, at present, the output Q/ of N1 will be clearly at logic 1.Thus for

S = 0 & R = 1. Q = 0 & Q/ = 1 This is called RESET state of the Flip-Flop. Table-1

/

Equation1

Comments

* Flip Flop is in its previous state or no change state Vide Table -2

Flip-Flop is in the RESET State

Flip-Flop is in the SET State

**

**

** Illegal State. Race problem arises Vide Table-3

Next consider the third row of Table -1 with input conditions. S = 1 & R = 0. / As S = 1, NOR gate N1 becomes disable and its output Q will be at logic 0, independent of the logic state of its other input. And as R is kept at logic 0, both inputs of N2 are at logic 0; therefore / its output Q will be at logic1. Thus for S = 1 & R = 0. Q = 1 & Q = 0 This is called SET state of the Flip-Flop. The SET and the RESET states of a Flip-Flop are unambiguous in the sense that they do not depend upon the previous history of the Flip-Flop i.e. no matter how or wherefrom such states have been established or arrived at. For S = 0 and R = 1, Q will be always 0 and for S = 1 and R = 0, Q will be always 1. In order to understand what memory means or in what manner the input / output history influences the state of the Flip-Flop, we must now consult first row of Table-1(i.e S = 0 & R= 0)
/

Equation 2

Let us suppose that at any time t1 (Present state) the Flip-Flop is in the Reset state with S = 0 & R / = 1; so that Q = 0 & Q = 1, and then at any later time t2, (Next state) the R input goes to 0. As can be verified from Figure 2, this change in R will not affect the state of the flip-Flop for the change is taking place at the input of the NOR gate N2, which has been already disabled by its / other input Q held at logic 1. Thus, we now find, that with S = 0 & R = 0 the Flip Flop remains in the Reset state and from this fact we can deduce that at a time earlier than t2 the input levels were S = 0 & R = 1. In other words, with S = 0 & R = 0, the state of the Flip-flop depends upon its immediately prior history of the input logic states. [Refer Table 2] / Similarly if initially at time t1, S = 1 & R = 0 so that Q = 1 & Q = 0 and the Flip-Flop was in the set state, and then at any later time t2 even if S becomes 0 (along with R = 0) the Flip Flop will not

change state for the change is taking place at the input of the NOR gate N1, which has been already disabled by its other input Q held at logic 1. Hence with S = 0 & R = 0 this time the FlipFlop will remain in the set state which was its previous state. Table 2

Present state

Next State

Comments

Remembers the previous state 0 1 0 1 0 0 0 1

Finally we will discuss the fourth row of Table 1 i.e. S = 1 and R = 1 / By making S = 1 & R = 1, we are forcing both the NOR gates disabled with Q & Q both 0. In this case the implication in Figure-2 that the outputs are complementary is incorrect. That is why the state of the Flip-Flop is marked illegal in Table-1. But that is not all. The greatest danger of making S = 1 & R = 1 is that, it gives rise to race problem. Refer Table-3 Suppose we want to pass from the illegal state S = 1 & R = 1 to the no change state S = 0 & R =0 via two different intermediate states or paths. Namely From S = 1 & R = 1 we first make S = 0 keeping as yet R = 1, as an intermediate state, and then make R also 0. As we make S = 0 & R = 1 as the intermediate state, the Flip-flop goes to the Reset state (Q = 0 & Q/ = 1) Afterwards when we make R = 0 also, the Flip-Flop passes into the / no change state. So, the final state of the FF is the Reset state (Q = 0 & Q = 1) Table-3

Present state (Illegal)

/

Intermediate state (Set or Reset)

/

Final state

Comments

Race problem arises

Now suppose from S = 1 & R = 1 we first make R = 0, keeping S still at 1, and then make S also 0. In this case the intermediate state becomes Q = 1 & Q = 0 i.e. the Set state. So,

afterwards making S also 0, the Flip Flop simply remembers the previous state. Hence the final state of the FF is the Set state. Conclusion: Whenever the Flip-Flop passes from an initial illegal state to the final no change state via an intermediate Set or Reset state, its output state is determined by the condition which of the two inputs S or R first becomes 0. If it is S, the FF attains the Reset set. If it is R, the FF attains the Set state. This is known as race condition. It is as if the inputs S & R are racing, and the final state of the FF is dictated by whichever S or R becomes the winner of the race. S-R Flip-Flop using NAND Gates S-R Flip-Flop can also be built up using NAND gates as shown in Figure 3. It is to be noted that / / the inputs are labeled by complemented variables S & R rather than S & R.

We can readily verify that the Truth Table for this FF is as shown in Table-4. If we now imagine / / two variables S & R of which S & R are the respective complements and use the information contained in Table-4, we can arrive at a table which is identical with Table-1. Thus whether we employ NAND or NOR gates, Table- 1 becomes a universal table of an S-R Flip-Flop. Table- 4
/ / /

Comments

**

**

**

Illegal Not to be used

RESET State

SET State

* Previous state

Logic symbol of an S-R Flip-Flop is shown in Figure 4.

Debouncer Circuit Whenever a mechanical switch is toggled, the contacts bounce back and forth, and make & break the circuit alternatively a number of times before being finally settled.

Thus although our intention in the circuit of Figure 5 is to raise the voltage at P from 0 Volt (logic 0) to + V volt (logic 1) on a single touch by toggling the SPDT switch, in reality we get oscillations between the two logic states a few times (completely unknown) before being finally settled to logic 1. This is shown in the accompanying diagram. Such a situation often leads to unpredictable results involving memories. One way to eliminate the effects of contact bouncing is to employ an S-R latch in conjunction with a mechanical switch as shown in Figure 6. / / Note that the control terminals of the Flip-Flop S & R are pulled up by the resistors R to the positive supply voltage V (Logic 1) [Comment: For TTL gates the pull up resistors are not necessary since floating TTL inputs always simulate logic 1 state.] / Suppose initially the pole P of the SPDT switch S touches the contact 1, to which the R input is / / joined, and thus returning it to GND (logic 0) Since S is at logic 1 and R is at logic 0, Q is at logic 0 and the FF is in the Reset state. When the switch S is toggled, the pole P leaves the contact1 / and moves towards the other contact 2 (to which S is connected). During the course of the / / journey, both S & R are at logic 1; so the state of the FF does not change. Just at the moment / the pole touches the contact 2 for the first time, S becomes 0 and the FF goes to the Set state / / and Q becomes 1. When the switch bounces back and leave the contact 2, both S & R again assume logic 1state. So the state of the FF does not change i.e. it remains in the Set state with Q / = 1. Once again when the pole touches the contact 2 for the second time, S once again becomes

0. The state of the FF with S = 0 & R = 1 is, as we know, the Set state. But this the state in which the FF already remains. Hence no matter how many times the switch bounces from the contact 2, the logic state of Q does not change it remains at logic1. A similar explanation can be given if the switch is again toggled in the opposite direction.

Problems: Investigate the sequential behavior of the following circuits: Which of them does not suffer from race problem? Why?

Game 1

Test how steady is your hand

A little change in the arrangement of making a Flip-Flop to assume SET & RESET states can result in an interesting game. Here it goes: / / The latch is kept in the remembering state by pulling up the control terminals S and R both high. With the help of an ordinary press-to-on switch S the FF can be RESET, if the switch S is momentarily pressed. In doing so pin 3 of the NAND gate N1 goes high and simultaneously pin 4 of N2 goes low and thus turns off the LED.

In stead of using such a switch to SET the FF, we have made a queer arrangement: From pin 5 of N2, a piece of wire, with insulation removed, and having a few closely spaced conducting loops stem out. Another piece of wire, with insulation only removed at ends, is given the shape of a small circular ring at one end and the other end is connected to the ground. Ask your friend to hold this piece of wire on the insulating part and slip the ring through the messy loop as far as he can, taking care not to touch the loop anywhere. If due to his carelessness or unsteady hand, the ring ever touches any part of the loop, the red LED will turn on. indicating his defeat. Turn off the LED by momentarily pressing S and ask another friend to try. Game 2 WHOS FIRST?

Initial adjustments: When power is first applied any of the two LEDs or both may glow. Press S3 to turn off the Green LED, if it is on. Press S4 to turn off the Red LED if it is on. Two persons are asked to participate in the game. Tell one of them to place his finger on switch S1 and the other on switch S2. They must be told not to press the switches until they are asked to do so. Ready, steady, go!

Who is first? If the Green LED turns on, then switch S1 has been pressed earlier than S2. If Red LED glows, switch S2 has been pressed first. Action of the circuit: There are 3 latches in the circuit namely: Latch 1is formed by 3- input NAND gates N1 & N2. Latch 2 is formed by 2- input NAND gates N3 & N4 & Latch 3 is formed by 2- input NAND gates N4 & N5. Both the triple-input NAND gates N1 & N2 are disabled by pulling down one terminal of each (pin 2 & pin 4 of CD 4023) to ground by 10 k resistors. Hence the latch remains in an illegal state with both outputs (pin 9 & pin 6) high, giving the possibility of race condition. Also pin 3 & pin 8 are high. Further, the two latches built around NAND gate pairs N3, N4 and N5, N6 are kept in the / remembering states with both of their Q outputs low and Q high. That is pin 4 & pin10 are low and pin 3 & pin 11 are high. It is to be noted that the third pin of the two triple input NAND gates / N1 & N2 viz. pin 1 & pin 5 are cross coupled by joining them respectively to Q outputs of the opposite latch 2 & latch 3 respectively. Thus if pin 4 of N3 goes high, pin 3 will go low and this will disable the gate N2. So also, if pin 10 of N5 goes high, pin 11 will go low and this will disable the gate N1. Suppose switch S1 is pressed momentarily just before S2. This makes the following series of actions pin 4 of N2 goes high, so pin 6 goes low. pin 8 of of N5 goes low, so the latch 3 is SET. With its Q output going high, the red LED turns on. Simultaneously, pin 11goes low and disable N1. Hence even if S2 is pressed just after S1, this cannot make pin 9 of N1 low any more. Hence the green LED will not glow. Similar action will take place if S2 is pressed prior to S1. In this case the Green LED will turn on but not the red LED.

Clocked Flip-Flop Necessity of clock

An unclocked Flip-Flop is called latch. Computers use thousands of Flip-Flops. To co-ordinate overall operation, a square wave signal called clock, is applied to each Flip-Flop so that each Flip Flop changes state all at a time. The necessity of using clock is illustrated with the help of a simple circuit shown in Figure 7.The circuit should be thought as a part of a larger digital system and the inputs A & B are coming from various parts of the system. / / Let us assume at the moment of interest A = 1 & B = 0, so S = 1. R is held permanently at logic 1.Therefore, the Flip-Flop is in its previous state. Since Q may be 0 or 1, let us assume that Q = 0 (Reset state).

Now suppose both A & B will undergo change state at the same time, and it is intended that such simultaneous change will not affect the state of the Flop-Flop. That is it will remain in the reset state. Consider, A changes to 0 just only a very small time t before B changes to 1. As it is evident from the timing diagrams in Figure 8a, our intention will be fulfilled i.e. the FF will remain in the Reset state. On the other hand, suppose, A changes to 0 after B changes to 1. It is then clear from Figure 8b / that although S will be in error for a small time t, the Flip-Flop will remain in the wrong state indefinitely. In a digital system, propagation delays through gates and others are unpredictable and the type of the difficulty would have been a common experience. This necessitates the use of a clock so that all Flip-flops change state in synchronization with the clock while the inputs are absolutely stable quite ahead in time.

Demonstration: An experimental arrangement for demonstrating the above theme is shown in Figure 9. The debouncer circuit built around the NAND gates N1 & N2 provides a simple way to change over the

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complementary logic output states A1 & B1. Thus, pressing momentarily the switch S1 will make A1 = 1 & B1 = 0. Pressing momentarily switch S2 will make A1 = 0 & B1 = 1.

It is to be noticed that the outputs A1 & B1 are not directly joined to the inputs A2 & B2 of the NAND gate N5 and that is why the paths a1 b1 & a2 b2 are shown broken. A simple arrangement for delaying the signal is arranged by the NAND gates N6 & N7. The delay circuit has its input marked a and the output marked b. A propagation delay introduced by the two gates (without changing logic states) is sufficient to demonstrate the theme of the experiment. The delay can be introduced either along the path a1 b1 by joining a to a1 & b to b1, or the same amount of delay can be introduced along the path a2 b2 by joining a to a2 & b to b2. / / / An S-R Flip-Flop using NAND gates N3 & N4 has got inputs marked S & R . The S input is joined / to the output of the gate N5, while the R input is pulled up to the logic state1.The Q output of the Flip-Flop drives the LED with suitable current limiting resistor. BY momentarily pressing the switch S3, Q can be made to change from 1 to 0, thus turning the LED off. Procedure: 1. Insert the delay circuit along the broken path a1 to b1. 2. Close the path a2 b2 directly. 3. Press momentarily the switch S1 to make A1 high & B1 low. (Green LED will then be on.) / At this standby stage A2 is also high and B2 is low. So S will be high. Since both states of Q are possible, press S3 to make Q = 0 so as to turn off the LED, if it is on. 4. Now press S2 momentarily. The red LED will immediately turn on indicating Q has become 1. 5. Repeat this experiment this time placing the delay circuit along the broken path a2 to b2 while short circuiting the path a1 b1 6. Repeat step 3 and ensure the red LED is off. 7. Now press S2 momentarily. The red LED will not glow, indicating Q has not changed state. It remains at logic 0. Level clocked Flip-Flop Figure 10 shows a clocked S-R Flip-Flop. A pair of NAND gates N1 & N2 drives a NAND latch built around the NAND gates marked N3 & N4. S & R signals drive the input gates while the output / / control terminals S & R drive the latch.

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 A square wave signal, called clock (CLK) is applied to the system as shown in Figure 10. When CLK is low (0) the input NAND gates N1 & N2 are both disabled and their / / respective outputs S & R are both at logic 1 irrespective of the signal conditions of S & / R. The latch is now in its previous state and the outputs Q & Q simply hold their previous values. When CLK becomes high (1) the input NAND gates are enabled and their outputs will be decided by the signal conditions at the other inputs. So, if S = 0 & R = 1, prior to making / / clock high, then when the clock becomes high, S will remain at logic 1, but R will / become logic 0. So, just after one get delay, Q will be 0 and Q will be 1 [Reset state] Similarly, if S = 1 & R = 0, before the clock becomes high, then after it, the FF will attain the Set state. If S & R are both 1, and CLK = 1, the FF will be in the in the illegal state as previously discussed. We therefore find that the Flip-Flop responds only when and as long as clock remains high. This short of Flip-flop is, therefore, called Level clocked Flip-Flop. [In a digital system using clocked Flip-flops, as in Figure-10 each clock pulse advances the digital processing by one step. The rate at which the processing proceeds is then determined by frequency of these clock pulses. In many systems, the pulses occur at a regular rate, reminiscent of the ticking of a clock; hence the name is quite appropriate.] The Truth Table of the level clocked S-R Flip-Flop is shown in Table-5. In the Truth table Q (t) represents the output state of the Flip-Flop at any given time t (i.e. the Present State) and Q (t+1) represents the output state after the clock transition denoted by time (t + 1) (i.e. Next State)

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Table-5

Present state

Next state

Q (t)

Q (t+1)

Not allowed

Not allowed

More over only Q output has been shown; because the other output is just its complementary and is, indeed, superfluous. Figure 11 shows the logic symbol of a positive level clocked S-R FlipFlop. Negative level clocking is similar. Visualize an inverter between the clock and the input gates in Figure -10. In this case the latch must wait until the clock goes low before the output can change. Figure -12 shows the logic symbol of a negative level clocked S-R Flip-Flop. Edge Triggered Flip-Flop

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Necessity of edge triggering

In a level-clocked Flip-Flop, the output can change state during an entire half cycle when the clock is high (1). This creates certain problems especially when feedback is employed from the output of a Flip-Flop to the input of the same Flip-Flop. This will be discussed in J-K Flip-Flops. In an edge-triggered Flip-Flop, output can change state only at a particular instant either when the clock transits from low (0) to high (1) or from high (1) to low (0). The former is known as positive edge-triggering and the latter negative-edge triggering. Edge triggering is also called dynamic triggering.

Figure-13 shows one way to build up a positive edge-triggered S-R Flip-Flop. The RC network acts as a passive differentiator circuit by keeping the time constant (RC) much lower than the clock pulse width. So when clock goes from low to high, the exponential charging produces a narrow positive voltage spike across the resistor as shown in the diagram. Later, on the trailing edge of the clock pulse a narrow negative voltage spike is also produced but the diode allows only the positive spike to pass through and enables the input steering gates N1 & N2 to sample S,R data only for a small interval of time. Thus the Flip-Flop responds only at the instant of triggering - the rest of the time it remains inactive.

Edge Detector: A narrow positive spike can also be generated at the rising edge of the clock using an inverter.

an AND gate as shown in Figure 14. The inverter produces a delay of a few nanoseconds. The

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AND gate produces an output spike that is High only for a few nanoseconds, when CLK & CLK/ are both high. (Note that no such spike will be generated at the negative going transition of the CLK.).

Note that the triangle in Figure 15 is the distinctive symbol of an edge triggered Flip-Flop. FlipFlops may be designed to respond at the trailing of the clock pulses. Figure16 shows the logic symbol of a negative-edge triggered S-R Flip-Flop .Note that the bubble is a reminder that the Flip-Flop is a negatively- edge triggered. Truth table of the edge triggered (positive or negative) S-R Flip-Flop is exactly the same as the level clocked Flip-flop as shown previously. The only difference is that the Flip-Flop responds only at the edge of the clock

PRESET & CLEAR When the power is first applied, the outputs of the Flip-Flops are quite random. To initiate the Flip-Flops in the desired state PRESET (synonymous with SET) and / or CLEAR (synonymous with RESET) facilities are usually provided. They may be active high or active low but the point is that only of them must be activated at a time and not both.

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Figure 17 shows a positive- edge triggered S-R Flip-Flop with both PRESET & CLEAR facilities. Thus on pressing momentarily the PRESET switch, the Flip-Flop will go to the SET state, while pressing the CLEAR switch; it will go to the RESET state. PRESET & CLEAR are called direct inputs. That means they are independent of clocking and can over ride any other inputs. Figure 18 gives the schematic symbol of such a Flip-Flop. .Note that the bubbles indicate they are active low.

Flip-Flop Operating Characteristics: Manufacturers of IC specify several important characteristics and timing properties that must be considered before a Flip-Flop is used in any circuit application. Most notable features are:

Propagation delay time tp Propagation delay time tp of a Flip-Flop is the minimum time required for the output to change stat, after the inputs have been sampled by the active clock edge. Set up time ts Set up time ts of a Flip-Flop is the minimum time required for fixing the data absolutely constant before the active clock edge has struck the Flip-Flop. Hold time th Hold time th of a Flip-Flop is the minimum time required to hold the data at the inputs of the FlipFlop after the active clock edge hits the Flip-Flop.

D Flip-Flop The S-R Flip Flop is susceptible to race condition. We can modify the design to eliminate the race problem. The result is a new kind of Flip-Flop known as D-Flip-Flop. D-Flip-Flop has a single input called Data (D) which is routed to S input directly and its / complement (D ) to R input of an S-R Flip-Flop. D Flip-Flop may be level clocked (Figure 19) or edge triggered (Figure 20). Whatever be it, the Flip-Flop responds only when clock is active. If D = 0, we get Q = 0 and if D = 1, we get Q = 1. It is for this reason a D-flip-Flop is called a transparent latch. Logic symbol of a positive edge-triggered D Flip is shown in Figure 21 while its Truth Table is provided in Table 6.

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Table 6

Q (t)

Q (t+1)

It is interesting to note that no input condition exists that will leave the state of the D-flip-flop unchanged. Table-6 reveals that neither for D = 0 nor for D = 1 we can get Q (t+1) = Q (t). In fact the only relation that we can build up to satisfy Table-6 is Q (t+1) = D. So, how can a D-Flip-Flop at all be called a memory element? After all Flip-Flops are just 1- bit memory cell. The answer is that no change condition can of course be realized in a D-Flip-Flop by employing feedback and a Multiplexer as shown in Figure 22. When the Select pin of the MUX, labeled LOAD, is 1, input I1 is selected and data (d) appears at the MUX output i.e. at the D-input of the Flip-Flop. On the next clock transition, it is loaded. If now LOAD is made 0, I0 will be selected and the MUX output will be simply Q (t) i.e. d. So even if data changes at the input I1, with every clock transition the previous data will be reloaded again and again. This is how the no change condition is accomplished in a D-Flip-Flop.

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Mathematically, since MUX Out put = D-input of the FF, hence at time t, D (t) = LOAD .I0(t)+ LOAD.I1(t) = LOAD/.Q(t)+ LOAD. d(t) Also Q(t + 1) = D(t) / Therefore, Q (t+1) = LOAD .Q (t) + LOAD. d (t) Thus for LOAD = 0, Q (t+1) = Q (t) [No change state] & for LOAD = 1, Q (t+1) = d (t)

J-K Flip-Flop J-K Flip-Flop is the most versatile Flip-Flop in the whole family. It overcomes the race problem and is considered to be an ideal memory element. Figure 23 shows the basic structure of a J-K Flip-Flop in which we find feedback is given from the output of the Flip-Flop to the input of the same Flip-Flop. We will first investigate the difficulty if we employ level clocking in such a configuration. The inputs of the Flip Flop are labeled J & K. Suppose that both J & K are held at logic 1 and the clock is at present low (0). Then the Flip-Flop exists in its previous state which we assume, without any loss of generality, is the RESET state (Q = 0 & Q/ = 1). / When clock goes from low to high, we must have, after one propagation delay, Q = 1 & Q = 0. / / Now since Q = 1 & Q = 0, and the clock is high the output will toggle i.e. Q will be 0 & Q = 1 again after another propagation delay. And once again when new outputs return to the input gates, we get another toggle. So, the output will toggle repeatedly as long as the clock remains high. In other words output oscillates during positive half cycle and the state of the Flip-Flop when clock goes low, is completely unpredictable.

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We therefore conclude, J-K Flip Flop is not possible to design with level clocking. Either it must be edge-triggered or Master- Slave.

Edge Triggered J-K Flip-Flop Figure 24 shows a positive edge-triggered J K Flip-Flop. The most striking feature of edge / / triggered Flip-Flop is that S & R can change state, according to input gate conditions, only during a narrow span of time when the positive edge of the clock hits the steering gates 1 A & 1 B but / / thereafter the steering gates become disable and S & R both remain at logic 1 & the outputs remain in their previous states. For this reason the problem of repeated toggling of output as encountered in level clocked J-K Flip for J = 1 & K = 1does not arise here. This is illustrated below: If we assume that the total propagation delay from input to output is top, then the output can change state only after a time tp, the rising edge of the clock has struck the steering gates. If the spike is sufficiently narrower than top, then the new values of Q & Q/ signals will return to the input only too late to cause false toggling because the spike has then already decayed to zero and the input gates have become disable by that time. This is however a restrictive requirement, since the operation of the circuit depends on the width of the pulses.

Master Slave J-K Flip-Flop The Master-Slave Flip Flop is really a combination of two similar Flip -Flops. The first one is called Master and the second one is called the Slave. The output of the Slave Flip-Flop is considered to be the output of the MS J K Flip-Flop. Both the Flip-Flops are level clocked, and the only difference between them is that the Master FF responds only when the clock is high but the Slave FF responds only when clock is low because / it is excited by the complement of CLK signal i.e. CLK . This means that while CLK is high (1), the Master is active but the Slave is inactive and while CLK is low, the Master is inactive but the Slave is active. The circuit diagram of a Master-slave J K Flip-flop is shown in Figure 25. / First of all we can show that such a FF cannot have any illegal state i.e. both QS & Q S cannot be simultaneously 1. The reason is: / / / If possible, let us assume QS = Q S = 1. This would then imply S S = 0 and R S = 0. In its turn this / / / would then imply QM = Q M = 1 and CLK = 1 or CLK = 0. This would then imply both S M = 0 and / R M = 0; so CLK must be 1. This is then a contradiction for CLK cannot be simultaneously low / and high. Hence QS & Q S must be complementary. Action of the circuit:

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Let J = 0 & K = 0

This means the Master FF will remain inactive even when the CLK is high (1) because with J = 0 / / / & K = 0, both the steering gates are disable and S M & R M are both high (1); so QM and Q M remain in their previous states. Later on when CLK becomes low (0) and the Slave becomes active; it will / not be able to change state because its inputs QM & Q M have not changed state. Thus the FF / remains in its previous state QS & Q S.

Let J = 0, & K = 1
/ /

Assume CLK = 1 so that the Master FF is active but the slave is inactive. With CLK = 0, both S S / and R S are 1. So the Slave FF remains in its previous state. However, QS may be 0 or 1. / Let us assume QS = 1 (Q S = 0) / As the Master FF is now active, then since J = 0, S M must be 1 but with K = 1, QS = 1 & CLK = 1, / / R M = 0; hence QM = 0 Q M = 1. This is the job Master has performed it has gone to the RESET state. / / If now CLK becomes 0, or CLK = 1, the Slave FF becomes active. Therefore, with QM = 0, Q M = / / / 1, S S = 1 & R S = 0; hence QS becomes 0 & Q S becomes 1. So, the Slave also goes to RESET state. / Note, therefore, there are two distinct states in establishing the final out states Q (= QS) & Q (= / Q S) .of the FF: First the Master is reset, while CLK is high. Second the Slave is reset when CLK is low. This action is some times called cocking & triggering. You cock the master during positive half cycle of the clock, and you trigger the Slave during negative half cycle. It is then clear that even if CLK becomes high once again , there will be no change of state of master outputs because both the steering gates 1A and 1 B have become disable (Former by J = / / Conclusion: For J = 0 & K = 1, Q = Qs = 0 & Q = Q S = 1. That is MS FF remains in the RESET state. Let J = 1 & K = 0 Assume, as before. CLK = 1 so that the Master 0 & the later by QS = 0)FF is active but the Slave is inactive. Since both states of Qs are possible, assume Qs = 1. As the Master FF is now active, / / / / then since K = 0, R M must be 1 but with J = 1, Q S = 1 & CLK = 1, S M = 0; hence QM = 1 & Q M =

20

0. Thus the Master has gone to the SET state. When CLK becomes 0, or CLK = 1, the Slave FF becomes active. Therefore, with QM = 1, Q/M =0, S/S = 0 & R/S = 1; hence QS becomes 1 & Q/S becomes 0. So, the Slave also goes to SET state. This is the Master Slave relationship. Every action of the Master during clock is high is exactly copied by the Slave during clock is low . Let J = 1 & K = 1 Assume, as before. CLK = 1 so that the Master FF is active but the slave is inactive. Since both states of Qs are possible, again assume Qs = 1. As the Master FF is now active, then since both J & K are at logic 1, the steering gates are / / Enable. Therefore, with J = 1, Q S = 0 and CLK = 1, S M = 1and with K = 1, QS =1 and CLK = 1, / / R M = 0. Hence QM = 0 & Q M = 1. That is the Master is in the reset state. / When CLK becomes 0, or CLK = 1, the Master becomes inactive and the Slave FF becomes / / / active. As S M & R M are both 1, QM remains at 0 & Q M at 1. Since the Slave is active, therefore, / / / / with QM = 0, & Q M = 1, S S = 1 & R S = 0; hence QS becomes 0 & Q S becomes 1. So, the Slave toggles i.e. it goes to reset state. Once again when CLK becomes 1, and steering gates are enable, then with new input data viz. J / / / = 1, Q S = 1 and CLK = 1, S M = 0 and with K = 1, QS = 0 and CLK = 1, R M = 1. Hence QM / becomes 1 and Q M becomes 0. Hence the master has toggled to the set state. Once again when CLK goes to 0, the Master becomes inactive and the Slave becomes active, / Hence there will be no change of QM & Q M (they remain at 1 and 0 respectively) & with QM = 1, & / / / / Q M = 0, S S = 0 & R S = 1; hence QS becomes 1 & Q S becomes 0. So, the Slave also toggles to / the set state with QS = 1 & Q S =0. / / / / If CLK becomes again 1, we return to our starting point i.e. S M = 1, R M = 0, QM = 0, Q M = 1, S S = / / 1, R S = 0 and QS = 0 & Q S = 1.The timing diagram as shown in Figure26 gives a visual indication

21

The timing diagram as shown in Figure26 gives a visual indication of the various logic states attained by the Master and the Slave in different clock cycles. / A Master-Slave J-K Flip-Flop is recognized by the postponed output symbol I at its Q and Q terminals as shown in Figure 27. Also no dynamic indicator symbol is provided at its clock terminal. An experimental arrangement for the study of Master-Slave J K Flip-Flop is shown in Figure E1.

Gates 1 A, 1 B, 3 A & 3 B: CD 4011[Quad 2-input NAND gates] Gates 2 A & 2 B: CD 4023 [Triple 3-input NAND gates]

T- Flip-Flop A T-Flip-Flop, called Toggle Flip-Flop has single input labeled T. When T = 1, the Flip-flop toggles on every clock trigger. When T = 0, the Flip-Flop remains in its previous state. Figure 28 shows the way T Flip-Flop can be designed using a J-K-Flip-Flop. The J & K inputs are tied together and provide the single input denoted by T.

Figure 29 shows the schematic symbol of the T-Flip-Flop & Table -7 shows its Truth-Table.

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Table-7

T 0 0 1 1

Q (t) 0 1 0 1

Q(t+ 1) 0 1 1 0

Characteristics Tables & Characteristics Equations of Flip-Flops

Characteristics Table of a Flip-Flop is a list of all possible combinations of inputs, the present state, and the corresponding next state of the Flip-Flop. That is if you know the inputs and the present of the FF, you can find out from the Table what will be its next state. The Characteristics Equation of a Flip-Flop expresses the next state of the FF as a function of the inputs and the present state of the Flip-flop. Characteristics Table & Characteristics Equation of an S-R flip-Flop Illustration: (i) (ii) (iii) (iv) (v) (vi) (vii) For S = 0, R = 0 & Q (t) = 0, we have Q (t+1) = 0 For S = 0, R = 0 & Q (t) = 1, we have Q (t+1) = 1 For S = 0, R = 1 & Q (t) = 0, we have Q (t+1) = 0 For S = 0, R = 1 & Q (t) = 1, we have Q (t+1) = 0 For S = 1, R = 0 & Q (t) = 0, we have Q (t+1) = 1 For S = 1, R = 0 & Q (t) = 1, we have Q (t+1) = 1 S = 1, R = 1 Not Allowed

23

From K-map we get Characteristics Equation: Q (t+1) = S + R . Q (t) Characteristics Table & Characteristics Equation of a J-K flip-Flop Illustration: (i) (ii) (iii) (iv) (v) (vi) (vii) (viii) For J = 0, K = 0 & Q (t) = 0, we have Q (t+1) = 0 For J = 0, K = 0 & Q (t) = 1, we have Q (t+1) = 1 For J = 0, K = 1 & Q (t) = 0, we have Q (t+1) = 0 For J = 0, K = 1 & Q (t) = 1, we have Q (t+1) = 0 For J = 1, K = 0 & Q (t) = 0, we have Q (t+1) = 1 For J = 1, K = 0 & Q (t) = 1, we have Q (t+1) = 1 For J = 1, K = 1 & Q (t) = 0, we have Q (t+1) = 1 For J = 1, K = 1 & Q (t) = 1, we have Q (t+1) = 0
/

Equation 3

From K-map we get Characteristics Equation: / / Q (t+1) = J. Q (t) + K .Q (t)

Equation 4

Characteristics Table & Characteristics Equation of D Flip-Flop Illustration: (i) (ii) (iii) (iv) For D = 0 & Q (t) = 0, we have Q (t+1) = 0 For D = 0 & Q (t) = 1, we have Q (t+1) = 0 For D = 1 & Q (t) = 0, we have Q (t+1) = 1 For D = 1 & Q (t) = 1, we have Q (t+1) = 1

24

Characteristics Equation is: Q (t+1) = D Characteristics Table & Characteristics Equation of T- Flip-Flop Illustration: (i) For T = 0 & Q (t) = 0, we have Q (t+1) = 0 (ii) For T = 0 & Q (t) = 1, we have Q (t+1) = 1 (iii) For T = 1 & Q (t) = 0, we have Q (t+1) = 1 (iv) For T = 1 & Q (t) = 1, we have Q (t+1) = 0 Characteristics Equation is: Q (t+1) = T /. Q (t) + T. Q/ (t) = T Q (t)

Equation 5

Equation 6

Excitation Tables of Flip-Flops

During the design of sequential circuits, we usually know the required transition from the present state to the next state and wish to find out the Flip-Flop input conditions that will cause (excite) the required transition. The Excitation Table lists the required input combinations for a given change of state. It is to be noted that the Characteristics Table of a Flip-Flop of course contains all the necessary information that are required to build up the Excitation Table. It is just looking at the behavior of the FF from a different angle. Excitation Table of an S-R flip-Flop: Illustration:

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If we look at the Characteristics Table [Table 6] of the S-R Flip-Flop, we notice: For the transition Q (t) = 0 to Q (t+1) = 0 [Refer Row 1 & Row 3] there are two possibilities viz. S = 0, R = 0 & S = 0, R = 1 Or, in short: S = 0, R = X [X denotes the dont care condition i.e. R can be both 0 and 1]

Again for the transition Q (t) = 0 to Q (t+1) = 1, there is just one possible pair viz. S = 1, R = 0 For the transition Q (t) = 1 to Q (t+1) = 0, there is just one possible pair viz. S = 0, R = 1 & For the Q (t) = 1 to Q (t+1) = 1, there are two possibilities viz. S = 0, R = 0 & S = 1, R = 0 which can be abbreviated as S = X, R = 0 This gives us the Excitation Table of the S-R Flip-Flop as shown in Table- 14 Excitation Table of a J-K Flip-Flop: From the Characteristics Table [Table 10] of the J-K Flip-Flop, we notice: For the transition Q (t) = 0 to Q (t+1) = 0, there are two possibilities viz. J = 0, K = 0 & J = 0, K = 1 Or, in short: J = 0, K = X Again for the transition Q (t) = 0 to Q (t+1) = 1, there can be two possible pairs, namely: J = 1, K = 0 as well as J = 1 & K = 1. That is J = 1, K = X For the transition Q (t) = 1 to Q (t+1) = 0, there is again two possible pairs viz. J = 0, K = 1 & J = 1, K = 1 i.e. J = X, K = 1 Finally for the Q (t) = 1 to Q (t+1) = 1, there are two possibilities viz. J = 0, K = 0 & J = 1, K = 0 i.e. J = X, K = 0 This gives us the Excitation Table of the J-K Flip-Flop as shown in Table- 15

26

Excitation Table of a D Flip-Flop: From the Characteristics Table [Table 12] of the D Flip-Flop, we notice: For the transition Q (t) = 0 to Q (t+1) = 0, D = 0 Again for the transition Q (t) = 0 to Q (t+1) = 1, D = 1

For the transition Q (t) = 1 to Q (t+1) = 0, D = 0 Finally for the Q (t) = 1 to Q (t+1) = 1, D = 1 This gives us the Excitation Table of the D Flip-Flop as shown in Table- 16 Excitation Table of a T Flip-Flop: From the Characteristics Table [Table 13] of the T Flip-Flop, we notice: For the transition Q (t) = 0 to Q (t+1) = 0, T = 0 Again for the transition Q (t) = 0 to Q (t+1) = 1, T = 1

For the transition Q (t) = 1 to Q (t+1) = 0, T = 1 Finally for the Q (t) = 1 to Q (t+1) = 1, T = 0 With the Excitation Table of the T Flip-Flop shown in Table- 17, our discussion ends.

27

Conversion of Flip-Flops

To convert one type of Flip-Flop into another, we have to design a combinational circuit such that The outputs of the combinational circuit are the inputs of the given Flip-Flop. The inputs of the required Flip-Flop are the inputs of the combinational circuit. The output of the given Flip-Flop also becomes the output of the required FlipFlop

The scheme is represented in Figure -30 and the procedure for conversion is illustrated below.

Step 1: Draw the Characteristic Table of the required Flip-Flop. Step 2: Next draw the Excitation table of the given Flip-Flop [It may be helpful if you overlap the two Tables] Step 3: Express each input of the given Flip-Flop as a function of the inputs of the required FlipFlop and the present state after drawing the respective K-Maps. Examples: 1. To convert an S- R Flip-Flop into a J-K Flip-Flop By Step 1, Step 2 as mentioned above, we get the conversion Table as shown in Figure 31. By step 3, we get from the K-Map of S [Figure 32] S = J .Q/ (t) Equation 7 And from the K-Map of R [Figure 33] R = K. Q (t) Equation 8 The relevant circuit is shown in Figure 34

28

29

2.

To convert an S- R Flip-Flop into a D Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 35. By step 3, we get from the K-Map of S [Figure 36] S=D Equation 9 And from the K-Map of R [Figure 37] / R=D Equation 10 The relevant circuit is shown in Figure 38.

3.

To convert an S- R Flip-Flop into a T Flip-Flop

30

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 39 By step 3, we get from the K-Map of S [Figure 40] / S = T. Q (t) Equation 11 And from the K-Map of R [Figure 41] R = T. Q (t) Equation 12 The relevant circuit is shown in Figure 42

4.

To convert a J - K Flip-Flop into an S-R Flip-Flop

31

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 43 By step 3, we get from the K-Map of J [Figure- 44] J=S Equation 13 And from the K-Map of K [Figure-45] K=R Equation 14 The relevant circuit is shown in Figure- 46

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5.

To convert a J - K Flip-Flop into a D Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure -47 By step 3, we get from the K-Map of J [Figure -48] J=D Equation 15 And from the K-Map of K [Figure- 49] / K=D Equation 16 The relevant circuit is shown in Figure- 50

33

6.

To convert a J - K Flip-Flop into a T Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure- 51 By step 3, we get from the K-Map of J [Figure-52] J=T Equation 17 And from the K-Map of K [Figure-53] K=T Equation 18 The relevant circuit is shown in Figure- 54

34

7.

To convert a D- Flip-Flop into an S-R Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 55 By step 3, we get from the K-Map of D [Figure 56] / Equation 19 D = S + R .Q (t) The relevant circuit is shown in Figure 57

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8.

To convert a D- Flip-Flop into a J-K Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 58 By step 3, we get from the K-Map of D [Figure 59] / / D = J Q (t) + K Q (t) Equation 20 Relevant circuit is shown in Figure 60.

9.

To convert a D- Flip-Flop into a T Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 61 By step 3, we get from the K-Map of D [Figure 62] / / D = T .Q (t) + T Q (t) = T Q (t) Equation 21 Relevant circuit is shown in Figure 63

36

10.

To convert a T- Flip-Flop into an S -R Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 64 By step 3, we get from the K-Map of T [Figure 65] / T = S. Q (t) + R. Q (t) Equation 22 Relevant circuit is shown in Figure 66

37

11.

To convert a T- Flip-Flop into a J-K Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 67 By step 3, we get from the K-Map of T [Figure 68] / T = J. Q (t) + K Q (t) Equation 23 Relevant circuit is shown in Figure 69.

38

12.

To convert a T- Flip-Flop into a D Flip-Flop

By Step 1& Step 2 as mentioned above, we get the conversion Table as shown in Figure 70 By step 3, we get from the K-Map of T [Figure 71] / / T = D. Q (t) + D . Q (t) = D Q (t) Equation 24 Relevant circuit is shown in Figure 72.

39