Xilinx ISE8.

1 and Spartan-3 Tutorial EE3810

Simple 3-to-8 Decoder

Part1) Starting a new project

Start the Xilinx ISE 8.1i Project Navigator:

Select File > New Project in the opened window

Simple 3-to-8 Decoder

Select a project location and name. For this tutorial we will name the project decoder.

Click Next.

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Select the device family, device, package, and speed grade, as shown here: Click Next.
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Click New Source.

Select VHDL Module and enter decoder as the file name: Click Next.
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Specify the inputs and outputs for the decoder. We have one 3-bit input (sel) and one 8-bit output (y) Click Next.
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In the summary window click Finish.

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Click Next.

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Click Next, because we do not want to add any other source.

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In this summary window click Finish.

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On the Project Navigator window, Click on the decoder.vhd tab below the summary window, or double-click on decoder behavioral in the top left Sources pane. 11

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Using VHDL, describe the behavior for a 3-to-8 decoder. Dont worry about the code yet, you will learn its details soon

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Before we can synthesize this design we need to specify what pins on the FPGA the inputs and outputs are connected to. Double-Click on Assign Package Pins under User Constraints in the Processes pane in the left of the Project Navigator window shown in slide 11. Note: You may be asked to save the VHDL file, and your design will be checked for syntax errors (these will need to be fixed before you can proceed).

We want to create a UCF file, so click Yes.

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The PACE editor will load as seen above Select Package View at the bottom of the right pane (this simply gives a better view of the physical FPGA package)

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Enter the pin names for each signal in the Design Object List at the left as shown here: Click File > Save followed by File > Exit.

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Note: This dialog may appear when saving the file:

Note: You may notice that the items listed in the Processes pane have changed. The Processes pane shows the actions that can be run on the file that is currently selected in the Sources pane. Select the decoder-behavioral source to get the same actions that were previously shown.
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You can then view the UCF file by double-clicking Edit Constraints (Text) in the Project Navigator:
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Part2) Generating a PROM file
How to generate a PROM file that can be written to the Platform Flash on the Spartan-3 board, so that your FPGAs configuration is saved even when the board is powered down.

Double-click on Generate PROM, ACE, or JTAG File under Generate Programming File in the Processes pane of Xilinx -ISE window. You will notice that Project Navigator will execute the steps listed above Generate Programming File (Synthesis and Implement Design) and mark them with a green checkmark as they complete.

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Enter the PROM File Name (for example, decoder_prom) and click Next

Select Prepare a PROM File and click Next

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Click Finish.

Select the appropriate PROM (which is xcf / xcf02s for this board) from the dropdown menus and click Add and click Next.

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Select the decoder.bit file and click Open.

Click OK.

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Click No.

Click OK.

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Double-click on Generate File under the iMPACT Processes pane.

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You should then see iMPACT report successful file generation:

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Before you close iMPACT, select File Save Project As

Save the configuration under a filename such as decoder_prom.ipf, but do not use the default filename of decoder.ipf (remember this filename). You can now close iMPACT.

Click YES.
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Simple 3-to-8 Decoder

In the Project Navigator, right-click on Generate PROM, ACE, or JTAG File in the Processes pane and select Properties. In the Process Properties window that opens, set the iMPACT Project File to the decoder_prom.ipf file that you saved at the end of Part 2. This will cause iMPACT to always load this configuration. To enable automatic file generation (iMPACT will not open, but the PROM file simply created in batch mode), turn on Automatically Generate File.

Click Ok to apply these settings. Now, anytime you double-click Generate PROM, ACE or JTAG File, the PROM file will be automatically created.
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Part3) Programming the board

Make sure that your JTAG cable is plugged into your PC and the board, and that the board is powered up.

Right-click on Generate Programming File in the Processes pane and select Properties.

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In the Process Properties window that opens, select the Startup Options tab. Change the CCLK to JTAG Clock in the FPGA Start-Up clock property. Make sure the other options look like shown here Click Ok.
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Double-click on Configure Device (iMPACT). The iMPACT tool will open and a wizard to create a new configuration will open.

Click OK if you get this warning.

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In the iMPCAT window; double click on the Boundary Scan under the Flows pane.

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In this window, right click and say Initialize chain

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First, the FPGA will be highlighted in the main window (xc3s200). You should select the decoder.bit file:

Click Open.
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Now the PROM should now be highlighted in the main window (xcf02s).

Select the decoder_prom.mcs file that you generated and click Open.

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You will now be at the main iMPACT window:

Right-click on the FPGA (xc3s200) and select Program. The following dialog will appear:

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Make sure that Verify is not checked and click Ok.

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The FPGA will now be programmed:

And you get this message:

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Right-click on the PROM and select Program. The following dialog will appear:

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Make sure that Erase Before Programming and Verify are both checked. Then click Ok.

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The device will now be programmed:

And you get this message:

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You can now close the iMPACT. If you get this message, select Yes here,

If somehow you get the following problem: Problem: Whenever you double-click Generate PROM, ACE, or JTAG File, iMPACT will not show you the dialogs to create the PROM file as shown in Part 2. Solutions: There are two workarounds to this problem: (1) delete any *.ipf files in the projects directory before you try to generate a PROM file, or (2) when iMPACT opens, select File New and select Prepare Configuration Files, then follow the steps as described in Part 2.
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References
Spartan 3 Information (including User Manual): http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3_fpgas/index.htm

ISE Webpack 8.1 (click download free and register): http://www.xilinx.com/ise/logic_design_prod/webpack.htm

Special thanks to James Duckworth and Hauke Daempfling for the tutorial. For more information: http://ece.wpi.edu/~rjduck/ece574.htm

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