Proceedings of MTECS-2008, AMU Aligarh

Comparison of Hybrid-CMOS Adders with static CMOS Adder in deep submicron Technology
Naushad Alam and Mohd. Hasan Department of Electronics Engineering Aligarh Muslim University itsnaushad@rediffmail.com m_hasan786@rediffmail.com
in low-power VLSI design [2], [3]. In this work, Minimum Leakage Vector (MLV) [4], [5] for all the full adder cells is also determined and the leakage power corresponding to MLV is compared. This paper investigates the full adder cells using HSPICE in 65nm technology with level 54 Berkeley Predictive Technology Model (BPTM) [6]. The rest of the paper is organized as follows. In section 2, modules of full adder cells are described and analysed. Twenty full adder cells obtained from combining these modules are simulated and their characteristics are compared in section 3. Summary and conclusion are given in section 4. II. MODULES OF FULL ADDER CELLS

Abstract--This paper presents an analysis and evaluation of Hybrid-CMOS full adder cells in 65nm technology. The cells are characterized with respect to active power, delay, Power-DelayProduct (PDP), and leakage power. The traditional CMOS cell characteristics are used as reference for comparison. It was observed from the analysis that many of the hybrid full adder cells out perform traditional CMOS structure. Moreover, minimum leakage vector (MLV), determined for all the cells, reveals that leakage power minimization by Input Vector Control (IVC) is more yielding for hybrid CMOS full adder cells.

I. INTRODUCTION Miniaturization has led to the popularity of portable systems. Power being the essential concern for such systems it is imperative to design systems that are power efficient. One direct way to reduce the dynamic power dissipation, which has been the major source of power dissipation, is supply voltage scaling which subsequently needs down scaling of the threshold voltage, channel length and gate oxide thickness of transistors to meet the performance requirement of the system. However, in deep submicron technologies, the exponential increase of sub-threshold leakage current pose serious design challenges. Further, as the technology scales, the gate oxide thickness needs to be scaled as well in order to keep the driving capacity of the gate on a considerable level. Consequently, not only sub-threshold leakage current, but gate leakage becomes more important as the gate direct tunneling current occurs in both ON and OFF transistors. In this paper twenty hybrid full adder cells, realized using smaller modules, are studied and compared with respect to active power, delay, PDP and static leakage power. These full adder cells have been analysed earlier in 0.35 CMOS technology and simulated with level 13 BSIM transistor models [1]. However, leakage power characteristic has not been addressed earlier. With shrinking feature size leakage power has become significant and can no longer be ignored

The relations between the inputs and the outputs of a full adder cell are expressed as Sum = A B Cin Cout = A.B + Cin.(A B) The above Boolean expression may be rearranged as H=AB Sum = H Cin = H .Cin + H .Cin Cout = A.H + Cin . H (1) (2) (3) (4) (5)

From the above expressions it is clear that H and its complement (H) are primary variables for both Sum and Cout. Module-1 is used to generate these two signals. Module-2 and Module-3 are used to generate Sum and Cout respectively. Dividing the full adder in this way enables the analysis, testing and optimization of each module separately [7]. Circuits of the three modules of full adder cell collected from [1] are shown in Fig. 1, Fig. 2, and Fig. 3. Circuits of first module are simulated with input test pattern suggested in [8] and are shown in Fig. 4. Simulation results of the circuits of each module are reported in Table-1, Table-2 and Table-3. Considering first module, circuit shown in Fig-1(d) consumes least power because it has no direct path between

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Proceedings of MTECS-2008, AMU Aligarh the power supply and the ground rails, eliminating direct short circuit current. Consequently, the leakage power of this circuit is minimum. Incomplete voltage swing at internal node of circuit in Fig. 1(c) leads to a constant current drain and hence consumes maximum power. For the second module, circuit in Fig-2 (b) has the lowest active power and leakage power as it has no ground or power supply rails and hence no short circuit current. Circuit in Fig. 3 (a) consumes very small power because of its powerless and groundless structure. Table-2 Simulation results for four different circuits of the Module-2 Leakage Module- Active Delay PDP Power 2 Power ( # Tr.) (pS) (nW) (uW) (x10-18 J) A B C D (6) (4) (6) (5) 1.4199 0.2271 0.6963 0.2935 52.866 27.429 49.218 23.722 75.064 6.226 34.256 6.962 82.14 64.74 91.83 78.34

Fig. 2. Circuits for Module-2

Fig. 1. Circuits for Module-1 Table-1 Simulation results for five different circuits of the Module-1 Module1 ( # Tr.) A B C D E (10) (8) (6) (8) (10) Active Power (uW) 1.723 1.159 2.038 0.525 1.151 Delay (pS) 56.664 45.303 42.890 35.266 48.345 PDP
(x10-18 J)

Leakage Power (nW) 174.97 160.33 101.29 85.79 186.88

Fig. 3. Circuit for Module-3 Table-3 Simulation results for the circuits of the Module-3 Leakage Module-3 Active Delay PDP ( # Tr.) Power Power (pS) (x10-18 J) (nW) (uW) A (4) 0.0579 6.58 0.381 2.46

97.632 52.506 87.409 18.515 55.645

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Proceedings of MTECS-2008, AMU Aligarh using these cells for low leakage applications where leakage power can be minimized using Input Vector Control method.

IV.

SUMMARY AND CONCLUSION

Fig. 4. Input test pattern for Module-1 III.

HYBRID CMOS FULL ADDERS

Combining different structures of Module-1 and Module-2 twenty full adder cells were realized. Each full adder cell is named with two letters corresponding to the circuits used for the first and second modules of the cell. The first letter refers to the circuit shown in Fig. 1 and second letter refers to the circuit shown in Fig. 2. All the above full adder cells and conventional CMOS full adder with 28 transistors are simulated with Vdd=1V at 800 C. Active power is measured with input test pattern suggested in [9] and shown in Fig. 5. Delay of all the transitions in Sum and Cout is measured and worst delay is reported as the cell delay. Leakage power of a cell is determined by taking average of static power for all the eight input combinations. Minimum Leakage Vector (MLV) for all the cells is determined and can be used for static power reduction by Input Vector Control method. The simulation results for the 21 full adder cells are reported in Table-4 and Table-5. Results in Table-4 show that cell DD and DB outperform all other cells from power dissipation point of view. This is well anticipated from the analysis results of individual modules in section-2 where circuit of Fig. 1(d) of Module-1 and Fig. 2(b), Fig. 2(d) of Module-2 consumes much smaller power compared to other circuits of that module. Cell CB uses minimum number of transistors and low power circuit for module-2 but consumes considerable power attributed to the highest power consuming circuit for the first module. Cell DB has smallest delay and is closely followed by cell DD as it uses fastest circuits for first and second modules. Thus, it is clear that generating intermediate signals H and H simultaneously in the first module gives better performance results. Table-5 lists full adder cells in the increasing order of average leakage power. It also shows the minimum leakage power corresponding to MLV for each cell. Though cells DD DB and CD use low leakage modules, however, interconnection of these modules to design full adder cells result in some very high leakage path for certain input vectors (001 for DD, 001 and 110 for DB, and 001 and 110 for CD). Consequently, the average leakage power for these cells is much higher than expected. On the other hand these adder cells have very small leakage power for their MLV (000 for DD, 111 for DB and 000 for CD). Hence there is scope for

Twenty Hybrid-CMOS full adder cells designed from smaller modules and a standard CMOS full adder cell are investigated in the deep submicron technology. This paper shows that Hybrid-CMOS structures exploit the benefits of different logic styles and many of these structures outperform the standard CMOS structure in all the aspects studied. Comparing the results of this paper with the previous analysis, it is concluded that characteristics of circuits in deep submicron technology is more involved and different. Short channel effects come into picture and ranking of full adder cells in this paper is slightly different from the earlier one. This work goes one step beyond the earlier analysis that it compares the full adder cells from leakage power perspective and determines best low leakage full adder and evaluates MLV for all the cells. Table-4 Simulation results for the full adder cells sorted by low power consumption. # Tr. Full Active Delay PDP Adder Power (pS) (x 10-18 J) Cell (uW) DD DB BD BB ED EB BA BC AB AD EA EC AC AA CB CD DC DA CMOS CC CA 17 16 17 16 19 18 18 18 18 19 20 20 20 20 14 15 18 18 28 16 16 0.979 1.027 1.641 1.689 1.812 1.894 2.271 2.360 2.386 2.388 2.532 2.607 3.043 3.139 3.177 3.189 3.840 4.479 4.528 6.961 7.737 52.2 51.2 70.1 70.6 63.1 70.7 80.1 103.2 93.4 95.3 70.3 108.2 90.2 83.1 60.5 61.3 143.2 196.3 111.4 152.2 153.1 51.125 52.582 115.006 119.215 114.331 133.920 181.931 243.111 222.824 227.576 177.247 281.588 274.488 260.554 192.209 194.523 549.134 877.884 502.586 1058.118 1183.776

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Proceedings of MTECS-2008, AMU Aligarh REFERENCES [1] Ahmed M. Shams, Tarek K. Darwish, and Magdy A. Bayoumi, Performance Analysis of Low-Power 1-Bit CMOS Full Adder Cells, in IEEE Transactions on VeryLarge Scale Integration (VLSI) systems, vol. 10, no.1, February 2002. [2] K. Roy, S. Mukhopadhyay, and H. MahmoodiMeimand, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits, in the Proceedings of the IEEE, vol. 91, no.2, Feb. 2003. [3] G. Merrett and Bashir M. Al-Hashimi, Leakage Power Analysis and Comparison of Deep Submicron Logic Gates, in IEEE 14th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2004), Santorini, Greece, September 2004. [4] Farzan Fallah and Massoud Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, in IEICE TRANS. ELECTRON., VOL.E88C, NO.4 APRIL 2005. [5] A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K.Roy, and Chris H. Kim, Leakage Power Analysis and Reduction for Nanoscale Circuits, Published by the IEEE Computer Siciety , April 2006. [6] Berkeley Predictive Technology Model: Device Group, University of California at Berkeley [online] Available: http://www-device.eecs.berkeley.edu/~ptm [7] A. Shams and M. Bayoumi, A Structured Approach for Designing Low Power Adders, in the thirty-first ASILOMAR Conference on Signals, Systems, & Computers, Pacific Grove, CA, June 1997. [8] S. Goel, A. Kumar, and Magdy M. Bayoumi, Design of
Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style, in IEEE Transactions on VLSI Systems, vol. 14, no. 12, December 2006. [9] J. C. Park and V. J. Mooney III, Sleepy Stack Leakage Reduction, in IEEE Transactions on VLSI Systems, vol. 14, no. 11, November 2006.

Fig. 5. Input test pattern for Full Adder Cells Table-5 Simulation results for the full adder cells sorted by leakage power consumption. Full Adder Cell BD BB AD ED AB BA EB BC CMOS AA AC EA EC CB DD DB CD DA CA CC DC # Tr. 17 16 19 19 18 18 18 18 28 20 20 20 20 14 17 16 15 18 16 16 18 Average Leakage (nW) 236.659 250.126 251.284 263.241 264.742 267.757 276.506 277.391 281.449 282.412 291.991 294.357 303.887 373.084 406.437 444.490 582.737 623.386 698.384 699.076 1080.099 Min. Leakage (nW) 194.339 165.852 202.278 180.144 188.773 143.156 151.609 165.914 232.560 204.371 227.130 183.631 206.375 106.059 76.477 67.982 38.370 154.613 153.981 176.737 169.671 MLV

110 111 000 110 111 101 111 101 111 101 101 101 101 000 000 111 000 111 101 101 101

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