Proceedings of MTECS-2008, AMU Aligarh

SUBTHRESHOLD OPERATION OF FIELD PROGRAMMABLE GATE ARRAY

A.K. Kureshi1, Naushad Alam2, and Mohd. Hasan3

Department of Electronics Engineering, AMU, Aligarh, akkureshi@rediffmail.com1 , m_hasan786@rediffmail.com2,itsnaushad@rediffmail.com3

Abstract FPGA architectures are well suited for wireless
applications since they provide high performance computation together with the capability to adapt to changing communication protocols, but as the process technology approaches sub-100nm, the leakage current poses serious design challenges in FPGA. Furthermore, the fraction of total delay due to routing is increasing with each process generation; hence these two parameters become a big obstacle in the use of FPGA in wireless low power portable application. This paper analyses the operation of FPGA basic Building Blocks in subthreshold region. HSPICE simulation based on BPTM (Berkeley Predictive Technology Model) at 30C for 32nm channel length device shows that with proper sizing of (W/L) ratio for the routing switches and LUT the FPGA work satisfactorily at a supply voltage of 0.3V with a marginal improvement in power delay products (PDP), as compared to conventional FPGA. Index terms-- Ultra-low Power, Subthreshold, FPGA, Switches, LUT, SRAM.

approach for achieving ultra-low power consumption of FPGA is to operate all the MOS transistors in sub- threshold region [5], where supply voltage (Vdd) is less than transistors threshold voltage (Vth) [6]. This paper simulates several FPGA routing switches and LUT (look-up table) at operating frequency of 2.5 MHz with supply voltages of 0.9V(>Vth) and 0.3V(<Vth). The paper is organized as follows: Section II enumerates some of the specific application areas where subthreshold FPGA are suitable. Section III deals with the basic architecture of FPGA, the power consumption and delay of all the Switches and LUT are evaluated in Section IV, Section V analyses SRAM cell and Section VI concludes this paper. II. APPLICATION AREAS

I.

INTRODUCTION

Subthreshold logic has emerged as a technology that can deliver theoretical minimum energy per computation which is very low as compare to (conventional) super-threshold CMOS. Subthreshold circuit operates with a supply voltage less than the threshold voltage of the MOS transistor [1], where the transistor essentially operates on leakage current. Conventional digital circuit either work in saturation or cut-off but subthreshold circuit operates either in an off state or an almost in on state which is the weak inversion region [2]. As power is related quadratically on the supply voltage, reducing the voltage to ultralow level results in a dramatic reduction in both power and energy consumption [3]. Minimizing the power consumption of FPGA is a vital design objective for portable devices such as mobile communication and bio-medical appliances where the power lowering is as important as the performance [4]. One

Subthreshold FPGA will be suitable for specific applications, which do not need very high performance but requires extremely low power consumption. This type of application includes medical equipments such as hearing aids, pacemakers, emerging wearable wrist watch computers and self power devices [6]. A subthreshold FPGA is also suitable for bursty-mode applications, which remains idle for a long period of time. III. ISLAND STYLE FPGA ROUTING ARCHITECTURRE

Figure 1(a) shows an island style FPGA routing architecture comprising of logic blocks and routing switches. The logic block has a basic logic element (BLE). The BLE consists of one Kinput lookup table (K-LUT) and one flip-flop shown in Figure 1(b). A 4-Input look-up table consists of 16:1 multiplexer with 16 SRAM for storing the configuration bits as shown in Figure 1(c). The data stored in the SRAM cell is transferred to the output by enabling selection lines from I0 to I3. A group of BLE forms a cluster, which is called Configurable Logic Block (CLB). The connection between the logic blocks is made by using one wire

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Proceedings of MTECS-2008, AMU Aligarh or two wires programmable switches [7]. The routing switches are in the form of pass transistors (NMOS) and tri-state buffers. Figure 2 shows the connection between the CLBs through C Box and S Box. The C Box is having buffer-multiplexer and multiplexer buffer structure whereas the S Box consists of pass transistors.

Figure 2. Typical Interconnect Structure Figure 1(a): sland style FPGA routing architecture

IV. Different Routing Switches

(a) Pass Switch

Figure 1(b): Island style FPGA routing architecture

Figure 3. Types of routing switches

Figure 3 shows the two routing switches namely pass transistor and tri-state buffer. Small transistor limits the current while large transistor increases the capacitance and has area penalty, when long connections are required pass transistors are unsuitable due to quadratic delay increase, whereas buffers are slower for short connection and require more area than the pass switch, therefore pass switch and tri-state buffer switch is used for short and long connections respectively. Table-1 lists the power consumption and delay of above switches.
(b) Multiplexer-tri-state buffer

Figure 4. Multiplexer-tri-state buffer

Figure 1(c): Transistor level view of 4-input LUT

Figure 4 shows the circuit of multiplexer-tri-state buffer, it is used as an inter-connect between CLBs. As the pass switch causes a drop of threshold voltage (Vth) in the output therefore a level restoring buffer is used at the output stage to compensate the Vth drop. Figure 5 shows the multiplexer-tri-state buffer switch box, which can be used to route four wires. Table I lists the power and delay of above switch.

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Figure 5. Multiplexer-tri-state buffer switch box

(c) Buffer- Multiplexer Switch

Proceedings of MTECS-2008, AMU Aligarh The subthreshold operation of FPGA can be easily implemented and derived from the traditional existing FPGA by lowering the supply voltage below the threshold voltage (Vth) of MOS transistor. Results show that subthreshold FPGA is more energy efficient (an average improvement of 25% in the Power Delay Product) than the standard CMOS FPGA with compromised frequency of operation. However, due to its low performance subthreshold FPGA is limited to only certain applications where ultra-low power is the primary requirement and performance is the secondary.

Table- 1 Summary of Power and Delay of all routing Switches and LUTs FPGA Building Blocks 4 Input LUT Vdd (Volts) Power (x10-10 W) Delay (x10-9 s) PDP (x10-19 J)

Figure 6. Buffer multiplexer switch

Figure 6 shows the circuit of Buffermultiplexer switch, as the buffers are having higher driving capability hence for longer connection the buffer multiplexer type switch is used which causes little delay in signal propagation. Table-1 lists the power and delay of above switch operating in superthreshold (Vdd = 0.9V) and subthreshold region (Vdd = 0.3V). V. SRAM CELL

0.9 0.3

318.3 29.40 408.1 5.310 3.481 0.054 210.5 3.310 210.6 5.310 3902 493.6

4.48 28.57 0.207 14.63 0.541 3.59 0.312 12.51 0.315 10.35 2.60 14.58

1425.98 839.95 84.47 77.68 1.88 0.193 65.67 41.40 66.33 54.95 10145.2 7196.7

D FlipFlop

0.9 0.3

Pass Switch

0.9 0.3

Tri-State Buffer Switch BufferMultiplexer Switch. MUX -TriState Buffer Switch Switch Box.

0.9 0.3 0.9 0.3 0.9 0.3

Figure 7. Basic SRAM Cell Architecture

The data for all the routing switches and LUTs are stored in the configurable SRAM cells. Figure 7 shows the transistor level circuit of SRAM cell. The cell is used to store a bit of information such as logic 0 (low) or logic 1 (high), the data can be read or written into the cell by asserting the word-line (WL) high [8] [9]. The (W/L) ratio of access transistors and pull-down transistors decide the delay in the read and write cycles. The simulation result at Vdd =0.3V and Vdd =0.9V supply voltage of SRAM cell are listed in Table-2, it shows that there is 4X reduction into the static noise margin and static power dissipation when the SRAM cell is operated in subthreshold region.

0.9 0.3

2007.8 281.7

1.81 7.027

3634.1 1979.5

Table- 2 Simulation Results for SRAM Cell Vdd (Volts) 0.9 0.3 SNM Active power Static power (nw) 15.21nW 3.75nW

VI. CONCLUSION This paper presents various routing switches and LUT working in the subthreshold region as a mean to achieve ultra-low power. 246

364mV 96mV

22.23 uW 49.36 nW

Proceedings of MTECS-2008, AMU Aligarh REFRENCES

[1] A. Wang, A. P. Chandrakasan, and S. V. Optimal supply and threshold scaling for subthreshold CMOS Proc. IEEE Annu. Symp. VLSI, 2002, pp. 59. Kosonocky, circuits, in

[2] J. Kao, M. Miyazaki, and A. Chandrakasan, A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture, IEEE J. SolidState Circuits, vol. 37, no. 11, pp. 15451554, Nov. 2002. [3] H. Kim and K. Roy, Ultra-low power DLMS adaptive filter for hearing aid applications, in Proc. Int. Symp. Low Power Electronics and Design, 2001, pp. 352357. [4] G. Schrom and S. Selberherr, Ultra-low-power CMOS technologies, in Proc. Int. Semiconductor Conf., 1996, pp. 237246. [5] B. H. Calhoun, A.Wang, and A. Chandrakasan, Device sizing for minimum energy operation in subthreshold circuits, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2004, pp. 9598. [6] Hendrawan Soleleman and Kaushik Roy, Robust subthreshold logic for ultra-low power operation, IEEE J. VLSI, vol. 9, no. 1, pp.90-98. [7] Betz, V., Rose, J. Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size in Proceedings of the IEEE 1997 Custom Integrated Cir-cuits Conference, May 1997, pp.551-554. [8] Faith Hamzaoglu, Mircea R.Stan, Circuit level techniques to control gate leakage for sub-100nm CMOS, ISLPED 2002, pp.61-63 [9] Ankur Goal, Bakuer Mazhari, Gate leakage and its reduction in deep submicron SRAM, IEEE International Conference on VLSI Design 2005

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