F.

Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block

Design of CMOS Analog
Integrated Circuits
Franco Maloberti
Basic Building Block
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
2 3/
INVERTER WITH ACTIVE LOAD
The simplest form of gain stage, the DC gain is given by the slope of the curve
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
3 3/
Small signal analysis:
C
1
= C
gs1
+ C
gs1,ov
C
2
= C
gd1
+ C
gd1,ov
C
3
= C
db1
+ C
db2
+ C
gd2
+ C
gd2,ov
+ C
L
At low frequency:
Since:
2 ds 1 ds
1 m
in
out
v
g g
g
V
V
A
+

D ds D ox m
I g I
L
W
C 2 g
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
4 3/
It results:
The DC gain increases as the square root of the bias current is decreased. This holds
until the devices enter the subthreshold region.
( )
p n D
1
ox 1
v
I
L
W
C 2
A
+

,
_

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
5 3/
At high frequency:
Millers theorem is applied to C
2
The output total capacitance is C
2
+ C
3
The output resistance is 1/(g
ds1
+ g
ds2
)
The transfer function has one pole
The unity gain frequency is:
It increases as the square root of the bias current increases
Due to Millers theorem the input capacitance becomes: C
in
= C
1
+ C
2
(1 - A
v
)
if |A
v
| >> 1 it can become significant to the stage driving it.
( )
3 2
D p n
3 2
2 ds 1 ds
p
C C
I
C C
g g
+
+

+
+

( )
D
3 2
ox 1
3 2
1 m
v p T
I
C C
L
W
C 2
2
1
C C
g
2
1
0 A
2
1
f
+

,
_

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block

6 3/
Example
Simulate an inverter with active load (V
DD
= 5 V) as the following figure with BSIM
3
V
2
Models. Find the DC gain and unity gain frequency.
Observe that the achieved gain is about 47 dB; the unity gain frequency is fairly good, being
around 500 MHz and the phase margin is about 87 degrees.
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
7 3/
CASCODE
The cascode gain stage is used to attenuate the Miller effect on node 1.
Bias voltage such to keep M
1
in the
saturation region
2
ox n
1
1
ox n
1
n , Th
L
W
C 2
I
L
W
C 2
I
V " "

,
_

,
_

+
+ + + >
2 , sat n , Th 1 , sat 2 GS 1 , sat B
V V V V V V
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
8 3/
Small signal analysis:
C
1
= C
gs1
+ C
gs1,ov
C
2
= C
gd1
+ C
gd1,ov
C
4
= C
gs2
+ C
gs2,ov
+ C
db1
+ C
sb2
C
3
= C
gd2
+ C
gd2,ov
+ C
gd3
+ C
gd3,ov
+ C
db2
+ C
db3
+ C
L
For low frequency, neglecting g
ds1
and g
ds2
:
g
m1
v
in
= -g
m2
v
1
= -g
ds3
v
0
Hence:
The Miller effect is significantly reduced if g
m1
g
m2
2 m
1 m
in
1
1
3 ds
1 m
in
0
v
g
g
v
v
A
g
g
v
v
A
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
9 3/
At high frequency:
The circuit has two nodes: the output and node 1.
The capacitance at the output is C
3
The output impedance is 1/g
ds3
(neglecting the impedance at the drain of M
2
)
The capacitance at the node 1 is (C
2
+ C
4
)
The impedance at the node 1 is 1/g
m2
The pole associated to the output node is:
The pole associated to the node 1 is:
Where = (1 + r
ds3
/r
ds2
)
3
3 ds
out
out , p
C
g
2
1 1
2
1
f

( )
2 1 m 4 2 2 m
2
2 m
1
1 , p
C g C C g
/ g
2
1 1
2
1
f
+ +

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block

10 3/
Since g
m
>> g
ds
, f
p,out
is dominant.
The gain-bandwidth product is:
If a good phase margin is needed, it must be:
This conditiin can be fulfilled
by increasing C
L
.
3
1 m
v dom , p T
C
g
2
1
A f f

( )
2 1 m 4 2
2 m
3
1 m
C g C C
/ g
C
g
+ +

<
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
11 3/
Impedance at the drain of M2:
1 ds
x
2 s
2 ds
2 s 2 m x
1 ds
x
x
g
i
v
g
v g i
g
i
v
+
+
2 ds 2 m 1 ds
1 ds
2 m
2 ds 1 ds
x
x
2 D
r g r
g
g
1 r r
i
v
r

,
_

+ +
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
12 3/
Impedance at the node 1,r
1
:
( )
x m x 2 ds x 1 a x
v g i r i R v +
2 m 2 ds
3 ds
2 m
2 s
g r
r
1
g
1
r

,
_

+
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
13 3/
CASCODE WITH CASCODE LOAD
Transconductance gain stage
The gain is increased by increasing g
m
or r
out
.
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
14 3/
In the improved version the transconductance of M
1
is increased by the factor
V
B1
and V
B2
must keep M
1
and M
4
out the triode region
V
B1
> V
sat,1
+ V
GS2
V
B2
< V
DD
- V
sat,4
- V
GS3
The figure plots the folded
structure useful if we need to
raise the voltage source of M
1
( )
4
5 4
M
M M
I
I I +
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
15 3/
Small signal analysis:
The output impedance is (conventional version):
[for the improved and folded version r
ds1
must be replaced with (r
ds1
//r
ds5
)]
The DC gain is:
The circuit has three nodes:
The output node
The source of M
2
The source of M
3
( )( )
3 ds 3 m 4 ds 2 ds 2 m 1 ds
3 ds 3 m 4 ds 2 ds 2 m 1 ds
out
r g r r g r
r g r r g r
r
+

( )( )
( )
2
ds m
3 ds 3 m 4 ds 2 ds 2 m 1 ds
3 ds 3 m 4 ds 2 ds 2 m 1 ds
1 m v
r g
2
1
r g r r g r
r g r r g r
g A
+

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
16 3/
The transfer function will have three poles. The dominant one is the output pole
C
out
, C
2
, C
3
capacitances incident on nodes 1, 2, 3.
At low frequency:
3 3
3
2 2
2
out out
out , p
C r
1
2
1
f
C r
1
2
1
f
C r
1
2
1
f

( )( )
3 ds 3 m 4 ds 2 ds 2 m 1 ds
3 ds 3 m 4 ds 2 ds 2 m 1 ds
out
r g r r g r
r g r r g r
r
+

1 ds
2 ds
4 ds 3 ds 3 m
2 m
2
r
r
r r g
1
g
1
r

,
_

+
4 ds
3 ds
2 ds 1 ds 2 m
3 m
3
r
r
r r g
1
g
1
r

,
_

+
3 2 out
r , r r >>
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
17 3/
At high frequency:
Output swing:
The output swing is limited by the conditions for which one of the transistors of the stage is
brought out of saturation
VB1 and VB2 must keep M1, M4, and M5 out of the triode region.
3 m
3
2 m
2
g
1
r
g
1
r
3 sat 3 GS 2 B max out
V V V V +

2 sat 2 GS 1 B min out

V V V V +

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block

18 3/
Example
Simulate the folded cascode amplifier, shown in the following figure, with V
DD
= 3.5V. Use
the models BSIM
3
V
2
to find the gain and the phase from input to output and from input to
node 2.
We observe that the gain and the phase plots of the output show a 20 dB roll-off with a good
phase margin (60 degrees). The low frequency gain is 77 dB and the unity gain frequency
is around 80 MHz. The behavior of the gain from the input to node 2 is interesting: above
the dominant pole, it holds 14 dB, just 2 dB more than the expected value g
m1
/g
m2
. At low
frequency climbs to 34 dB.
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
19 3/
DIFFERENTIAL STAGE
M
1
, M
2
in saturation with (W/L)
1
= (W/L)
2
assume:
( )
2
Th 1 GS
1
ox
1
V V
L
W
2
C
I

,
_

( )
2
Th 2 GS
2
ox
2
V V
L
W
2
C
I

,
_

2
v
V V ;
2
v
V V
in
0 GS 2 GS
in
0 GS 1 GS
+
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
20 3/
The output variable is the differential current:
since the bias current can be expressed as:
it results: at small signal:
with a common mode signal:
( )
Th 0 GS in
1
ox 2 1
V V v
L
W
C I I I

,
_

( )
2
Th 0 GS
1
ox 2 1 SS
V V
L
W
C I I I

,
_

+
SS
1
ox in
I
L
W
C v I

,
_

m in
g v i
i
in
i m
CM m
CM
r 2
v
r g 2 1
v g
i
+

i m
CM
d
r g 2
i
i
CMMR
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
21 3/
Example
Verify equation Consider an n-channel differential pair using
(W/L) = 100 m and Iss = 100 A.
The transconductance transfer function is fairly linear over a wide range of input signal. It
starts to saturate only when the input signal approaches the overdrive voltage of the
differential pair (75 mV).
. I
L
W
C v I
SS
1
ox in

,
_

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
22 3/
SOURCE FOLLOWER
Used as buffer or as DC-level shifter
at low frequency:
hence:
( ) 0 v g v g v g g
1 gs 1 m out 1 ds out 2 ds 1 ds
+ +
1 mb 2 ds 1 ds 1 m
1 m
in
out
v
g g g g
g
v
v
A
+ + +

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
23 3/
If
at high frequency:
where:
The output impedance is obtained by applying a test source V
x
at the output node.
Hence:
The output is not symmetrical. For n-channel input device
( )
out 1
1
v
C C
C
S A
+

ov 1 gs 1 gs 1 1 sb 2 db ov 2 gd 2 gd L
C C C C C C C C C + + + + +
1 A then g g g g
v 1 mb 2 ds 1 ds 1 m
+ + >>
( )
x 1 m 1 mb 2 ds 1 ds x
v g g g g i + + +
1 m 1 m mb 2 ds 1 ds
out
g
1
g g g g
1
R
+ + +

2 sat min out 1 GS DD max out

V V V V V

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
24 3/
Example
Simulate the large signal behavior and derive the dc small signal voltage gain. I
B
= 0.1 mA
and V
DD
= 3.3 V.
The output voltage, practically, follows the input shifted by V
GS
. However, due to the body
effect, the value of V
GS
is not constant; it rises from 713 mV to 1.13 V. Therefore, the input-
output characteristic is not 1 but 0.81. The figure shows also the dc gain: its value ranges
from 0.74 to 0.86 quite well match as theoretical results.
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
25 3/
IMPROVED OUTPUT STAGES
Performances improved by the use of negative feedback.
( )
x 3 ds 1 m 2 2 4 m x 2 ds 1 m x
v r g v v g v g g i + +
( )
2 ds 3 ds 4 m 1 m
out
g r g 1 g
1
R
+ +

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block

26 3/
Class AB push-pull:
let:
With R
out
= 0:
The output conductance is:
With resistive load, the drop voltage across the output resistance determines (going out
current):

,
_

+ + +
ox 4 p
4
ox 3 n
3
5 p , Th n , Th 4 GS 3 GS 12
C W
L 2
C W
L 2
I V V V V V
4 2 3 1
L
W
k
L
W
L
W
k
L
W

,
_

,
_

,
_

,
_

; kI I I ; V V ; V V
5 2 1 4 GS 2 GS 3 GS 1 GS

2 m 1 m out
g g g +
out 1 2 4 GS 2 GS 3 GS 1 GS
I I I ; V V ; V V < >
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
27 3/
For a given load I
2
--> 0; the output conductance becomes g
out
= g
m1
In general an output stage has the following equivalent circuit:
It determines harmonic distortion
( ) ... I I 1 R R
2
out 2 out 1 0 out out
+ + +
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
28 3/
Class AB push-pull with gain stage
if it is verified the condition:
2 g 1 g
V V
6 ds
5 m 4 m
r
g
1
g
1
<< +
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
29 3/
Voltage divider
Analog circuits normally have only two dc voltage supplies
In order to obtain dc bias voltages, voltage dividers can be used
Resistive or capacitive dividers can be used, however they are
complex or silicon area consuming
MOS in the diode configuration can be used
The transistors are in saturation
( ) ( )
2
2 Th 2 DS
2
2
1 Th 1 DS
1
V V
L
W
2
k
V V
L
W
2
k

,
_

,
_

DD 2 DS 1 DS
V V V +
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
30 3/
It results a voltage division of V
DD
plus
an offset.
If a signal (usually undesired) is
superposed to V
DD
, the small signal
equivalent circuit must be considered.
At low frequency (assuming g
m2
>>g
ds2
and g
m1
>>g
ds1
)
2 gs 2 2 sb 1 db 1 gs 1
C C ; C C C C + +
2 1
2 Th 2 1 DS 1
DD
2 1
2
1 DS 1
V V
V V V
+

+
+

2
2
1
1
L
W
;
L
W

,
_

,
_

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
31 3/
At high frequency
It results an injectin of the noise from the power supply (V
DD
)
2 m 1 m
mb
2 m 1 m
2 m 1 m
mb
1 m
dd 1
g g
g
g
1
g
1
g g
g
g
1
V V
+ +
+

2 1
2
DD 1
C C
C
V V
+

F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
32 3/
Level Shifter
Essential for NMOS circuits, useful for CMOS circuits
High-impedance level shift
Low-impedance, or battery, level shift
High Input Impedances:
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
33 3/
Body effect neglected
Threshold voltage variation effect (V
Th
+150 mV)
Input and output swing limitation
Level shift threshold-independent:
(assuming M
1
in saturation and neglecting )
usually V < V
Th
Th ov Th GS
V V V I
kW
L 2
V V + +
( )
1
1
]
1

,
_

,
_

2
2
2 1
1
I
W
L
I I
W
L
k
2
V
F. Maloberti : Design of CMOS Analog Integrated Circuits - Basic Building Block
34 3/
Low Impedances:
It behaves like a voltage source
a)
b)
a) Simple level shifter b) Shunt feedback level shifter
a) r
out
= 1/g
m
b) affected by twice voltage
threshold variation
Th DS
V I
kW
L 2
V V +
2
2
1
1
2 Th 1 Th 2 GS 1 GS
I
kW
L 2
I
kW
L 2
V V V V V

,
_

,
_

+ + +