Chapter 8.

Working with FSMs

In chapter 7, we looked at a general procedure for implementing finite state machines (FSMs) and illustrated the FSM designs with three models (Moore, Mealy, synchronous Mealy). Now we are going to discuss how to optimize or minimize the design in this chapter.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz

Finite state machine optimization

State minimization
fewer states require fewer state bits fewer bits require fewer logic equations

Encodings: state, inputs, outputs

state encoding with fewer bits has fewer equations to implement
however, each may be more complex

state encoding with more bits (e.g., one-hot) may have simpler equations
complexity directly related to complexity of state diagram

input/output encoding may or may not be under designer control How can we minimize or optimize the FSM? Again, there are three categories of variables: state, inputs and outputs. The first thing to think about is states. In general, minimizing the number of states leads to a simple design. How about encoding for state? Even with the same number of states, encoding can be different. At first sight, the minimum # of bits to represent states seems to be best. But we have to think over other options. Inputs and outputs may not be controlled, depending or situations.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 2

Algorithmic approach to state minimization

Goal identify and combine states that have equivalent behavior Equivalent states:
same output for all input combinations, states transition to same or equivalent states

Algorithm sketch
1. place all states in one set 2. initially partition set based on output behavior 3. successively partition resulting subsets based on next state transitions 4. repeat (3) until no further partitioning is required
states left in the same set are equivalent

polynomial time procedure

The first goal is to find out some redundant or duplicate states in the first naive design. That is, we need to find out equivalent states. The sketchy algorithm is described here. The first criterion for grouping states is output. The rationale behind this partitioning is that, if the outputs of states are same, there is a possibility that we may be able to combine those states into a single state. Then the next trick is to check whether some states have the same next state. VIII - Working with Sequential
Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 3

State minimization example

Sequence detector for 010 or 110
Input Sequence Reset 0 1 00 01 10 11 1/0 S6 0/1 1/0 Next State Present State X=0 X=1 S0 S1 S2 S3 S4 S5 S6 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 Output X=0 X=1 0 0 0 0 1 0 1 0 0 0 0 0 0 0

0/0 0/0 S3 0/0 S1

S0

1/0 0/0 S5 0/0 S2

1/0 S4 0/1 1/0

1/0

1/0

X: the current input

Suppose there is a binary input string; one bit is coming into the system at each clock tick. What this system should do is to make output asserted when the current three bits are either 010 or 110. The state diagram with a Mealy model is on the left; this is an initial nave and ad hoc design of states. Each of the three bits will have two choices, which yields 8 cases or scenarios. That state diagram consists of 7 states and is converted to a stateVIII transition table in a little bit different form. Note that this system reads the input in - Working with Sequential Logic of 3bits. No overlapping 4 Copyright 2004, Gaetano 11010 Borriello and Randy H. Katz generate 00100 the unit is allowed. input will

Method of successive partitions

Input Sequence Reset 0 1 00 01 10 11 Next State Present State X=0 X=1 S0 S1 S2 S3 S4 S5 S6 S1 S3 S5 S0 S0 S0 S0 S2 S4 S6 S0 S0 S0 S0 Output X=0 X=1 0 0 0 0 1 0 1 0 0 0 0 0 0 0

( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 )

S4 is equivalent to S6 S1 is equivalent to S2 S3 is equivalent to S5

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 ) ( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )

Now lets try partitioning. First, lets see the output. S4 and S6 have the same output for both values of X. and the other states will make the same outputs. Then what states lead to S4 and S6? The right previous states of S4 and S6 are S1 and S2. So they are grouped next. Then S3 and S5 will move to S0. So S3 and S5 are grouped last. Typically, the states in the same level of the state diagram may be merged.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 5

Minimized FSM
State minimized sequence detector for 010 or 110
Input Sequence S0 X/0 S1 0/0 S3 X/0 0/1 1/0 S4 1/0 Reset 0+1 X0 X1 Next State Present State X=0 X=1 S0 S1' S3' S4' S1' S3' S0 S0 S1' S4' S0 S0 Output X=0 X=1 0 0 0 1 0 0 0 0

Now we have a minimized FSM (Mealy model). Actually, it utilizes the common part of the inputs to be detected. As the first bit can be any value, the system needs to detect X10.

VIII - Working with Sequential Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

More complex state minimization

Multiple input example
00 S0 [1] 10 11 00 S2 [1] 10 10 00 S4 [1] 11 01 11 01 10 01 10 S5 [0] 11 00 00 01 S1 [0] 11 00 01 01 S3 [0] 11 10

inputs here

present state S0 S1 S2 S3 S4 S5

00 S0 S0 S1 S1 S0 S1

next state 01 10 11 S1 S2 S3 S3 S1 S4 S3 S2 S4 S0 S4 S5 S1 S2 S5 S4 S0 S5

output 1 0 1 0 1 0

symbolic state transition table

Lets look at a more complicated case. Now there are two input bits incoming simultaneously. Even though there are less states in the initial design, the state transition appears to be very complicated. Output-based nave checking in the previous example may not be effective due to complex transitions. That means we need a systematic way.
VIII - Working with Sequential Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Minimized FSM
Implication chart method
cross out incompatible states based on outputs then cross out more cells if indexed chart entries are already crossed out
S1 S0-S1 S1-S3 S2-S2 S3-S4 S0-S1 S3-S0 S1-S4 S4-S5

[S0,S2,S4] !== [S1,S3,S5]

present state S0' S1 S2 S3'
S1-S0 S3-S1 S2-S2 S4-S5 S1-S1 S0-S4 S4-S0 S5-S5 S3

S2

S3 S0-S0 S1-S1 S2-S2 S3-S5

next state 00 01 10 11 S0' S1 S2 S3' S0' S3' S1 S3' S1 S3' S2 S0' S1 S0' S0' S3' minimized state table (S0==S4) (S3==S5)

output 1 0 1 0

S4

S5 S0

S0-S1 S3-S4 S1-S0 S4-S5 S1

S0
S4

S3

S2

The implication chart method checks the equivalence of two states systematically. Black X marks indicates two states (row and column of a cell) are not compatible. Each cell lists VIII the- next for all input values (row cell first). If any pair is not compatible, that Workingstates with Sequential Logic 8 S3. Copyright 2004, Gaetano Borriello and Randy Katz cell should be crossed out (red X). Finally S4 and S0 are H. equivalent and so are S5 and

Minimizing incompletely specified FSMs

Equivalence of states is transitive when machine is fully specified But its not transitive when don't cares are present
e.g., state S0 S1 S2 output 0 1 1

S1 is compatible with both S0 and S2 but S0 and S2 are incompatible

No polynomial time algorithm exists for determining best grouping of states into equivalent sets that will yield the smallest number of final states If states A and B are equivalent and so are B and C, normally A and C are also equivalent. However, with dont care terms, that transitivity may not hold true.

VIII - Working with Sequential Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

Minimizing states may not yield best circuit

Example: rising edge detector - outputs 1 when last two input changes from 0 to 1 X Q Q Q+ Q+
0 00 [0] 0 10 [0] 1 1 1 0 01 [1]
1 0 1 0

0 0 0 1 1 1

0 0 1 0 0 1 1

0 1 0 0 1 0 1

0 0 0 0 1 1

0 0 0 1 0 0

Q1+ = X (Q1 xor Q0) Q0+ = X Q1 Q0 Out = Q1 Q0

Minimizing the number of states may not achieve the simplest design due to complex logic equations. In this above state diagram, we use only 3 states. However, the combinational logic may not be so simple. In this example, we assume that input X starts with 0.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 10

Another implementation of edge detector

"Ad hoc" solution - not minimal but cheap and fast
0 00 [0] 1 10 [0] 0 0 11 [0] 1 1 01 [1]

This looks a more nave state diagram at first glance. However, after constructing the state transition table, we can derive much simpler logic. Q1+ = Q0, Q0+ = X, Out = Q1Q0. This example is not a general case. In most cases, the minimum number of states is favored in sequential logic system design.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 11

State assignment
Choose bit vectors to assign to each symbolic state
with n state bits for m states there are 2n! / (2n m)! [m <= 2n] 2n codes possible for 1st state, 2n1 for 2nd, 2n2 for 3rd, huge number even for small values of n and m
intractable for state machines of any size heuristics are necessary for practical solutions

optimize some metric for the combinational logic

size (amount of logic and number of FFs) speed (depth of logic and fanout) dependencies (decomposition)

Now we finish how to decide the number of states. From now on, we will talk about what binary values will be assigned to individual states. Suppose we have m states and use n bits to represent all the states. Then the number of total possible assignments is 2nPm. There are many many ways to assign the bit vectors to states. Depending on the state assignment, the complexity of combination logic can be different. Again there can be a variety of criteria to evaluate the combinational logic.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 12

State assignment strategies

Possible strategies
sequential just number states as they appear in the state table random pick random codes one-hot use as many state bits as there are states (bit=1 > state) output use outputs to help encode states heuristic rules of thumb that seem to work in most cases

No guarantee of optimality another intractable problem Some of the popular strategies of state assignment are listed. We already talked about one-hot encoding in the last chapter. A rule of thumb is a principle with broad application that is not intended to be strictly accurate or reliable for every situation. We can easily learn or come up with a heuristic algorithm. In any case, the optimal assignment is an NP-hard problem.

VIII - Working with Sequential Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

13

One-hot state assignment

Simple
easy to encode easy to debug

Small logic functions

each state function requires only predecessor state bits as input

Good for programmable devices

lots of flip-flops readily available simple functions with small support (signals its dependent upon)

Impractical for large machines

too many states require too many flip-flops decompose FSMs into smaller pieces that can be one-hot encoded

Many slight variations to one-hot

one-hot + all-0

One hot encoding is popular since it is likely to have a simple structure of combinational logic. Also, the number of terms per next state literal is the number of incident arcs, which fits into a PAL
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 14

Heuristics (adjacency in K-map, Gray coding)

Adjacent codes to states that share a common next state
group 1's in next state map (e.g. uniting theorem)
I i i Q a b Q+ c c O j k c=i*a + i*b a i/j c b i/k

Adjacent codes to states that share a common ancestor state

group 1's in next state map
I i k Q a a Q+ b c O j l b=i *a c=k*a i/j b a k/l c

Adjacent codes to states that have a common output behavior

group 1's in output map
I i i Q a c Q+ b d O j j j=i *a+ i *c b=i*a d=i*c a i/j b c i/j d

Now we will explain some heuristic algorithms for state assignment. A heuristic is a technique designed to solve a problem that ignores whether the solution can be proven to be optimal or best, but which usually produces a good solution. In general, we want to VIII - Working with Sequential haveLogic on-set elements adjacent to one another. 15 Copyright 2004, Gaetano Borriello and Randy H. Katz

General approach to heuristic state assignment

All current methods are variants of this
1) determine which states attract each other (weighted pairs) 2) generate constraints on codes (which should be in same cube) 3) place codes on Boolean cube so as to maximize constraints satisfied (weighted sum)

Can't consider all possible embeddings of state clusters in Boolean cube

heuristics for ordering embedding to prune search for best embedding expand cube (more state bits) to satisfy more constraints Fig 8.6, 8.32, 8.33

Typically, the reset state is assigned state 0. Overall, we want to cluster 1s in the vicinity for potential application of the uniting theorem in K-maps. The three guidelines in the previous slide have the same purpose. Somehow we have to order the grouping rules. E.g., in the previous slide, the top rule has the highest priority and the bottom one has the lowest priority.
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 16

Output-based encoding
Reuse outputs as state bits - use outputs to help distinguish states
why create new functions for state bits when output can serve as well fits in nicely with synchronous Mealy implementations H1H0
Inputs C TL 0 0 1 1 1 0 0 1 Present State TS 0 1 0 1 HG HG HG HY HY FG FG FG FY FY Next State HG HG HY HY FG FG FY FY FY HG Outputs ST H 0 00 0 00 1 00 0 01 1 01 0 10 1 10 1 10 0 10 1 10 F 10 10 10 10 10 00 00 00 01 01 F1F0

HG = ST H1 H0 F1 F0 + ST H1 H0 F1 F0 HY = ST H1 H0 F1 F0 + ST H1 H0 F1 F0 FG = ST H1 H0 F1 F0 + ST H1 H0 F1 F0 HY = ST H1 H0 F1 F0 + ST H1 H0 F1 F0

Output patterns are unique to states, we do not need ANY state bits implement 5 functions (one for each output) instead of 7 (outputs plus 2 state bits)

If there are many output patterns, maybe we can substitute outputs for states. Each state is replaced by each unique output or its combination. That is, the next state is absorbed VIII - Working with Sequential by the current outputs Logic 17 Copyright 2004, Gaetano Borriello and Randy H. Katz

Output-based encoding
Present state is now represented by present outputs
No one state-bit is assigned to a state (ex) HY = 00010 + 11001 (STH1H0F1F0 + STH1H0F1F0)
C TL TS
ST = CTLHG + TSHY+ CFG + TLFG + TSFY

HG HY FG HY

H1 = FG + FY H0 = HY F1 = HG + HY F0 = FY

After identifying the states by outputs, the current state will be replaced by the outputs. Then the outputs are again encoded by the inputs and the new current states
VIII - Working with Sequential Logic Copyright 2004, Gaetano Borriello and Randy H. Katz 18

Current state assignment approaches

For tight encodings using close to the minimum number of state bits
best of 10 random seems to be adequate (averages as well as heuristics) heuristic approaches are not even close to optimality used in custom chip design

One-hot encoding
easy for small state machines generates small equations with easy to estimate complexity common in FPGAs and other programmable logic

Output-based encoding
ad hoc - no tools most common approach taken by human designers yields very small circuits for most FSMs

In general, the minimum number of states is preferred. For the encoding for each state, there can be various strategies. Each has its pros and cons.

VIII - Working with Sequential Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

19

Sequential logic optimization summary

State minimization
straightforward in fully-specified machines computationally intractable, in general (with dont cares)

State assignment
many heuristics best-of-10-random just as good or better for most machines output encoding can be attractive (especially for PAL implementations)

VIII - Working with Sequential Logic

Copyright 2004, Gaetano Borriello and Randy H. Katz

20