Digital Design Flow Eda Tool

Code ET4351
Digital Design Flow

Tutorial for EDA Tools:
Synopsys Design Compiler Mentor Modelsim Cadence SOC Encounter V12.1
Delft University of Technology
Ir. A.C. de Graaf Dr. ir. T.G.R. van Leuken
Preface
This document describes the top-down design ow of the implementation a SoC design. Starting from an example HDL description the designer is guided through all the design steps to tapeout GDS2 layout description. This tutorial is derived from "Top-Down digital design ow" version 3.1 (November 2006) by Alain Vachoux, Microelectronic Systems Lab EPFL, Lausanne, Switzerland.
Contents
1 Introduction 1.1 Top-down design ow . . . . . . . . . 1.2 Design project organisation . . . . . . 1.3 EDA tools and design kit conguration 1.4 VHDL example: FIR-Filter . . . . . . 1.5 Design ow steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3 5 5 8 10 10 11 13 14 16 16 17 17 18 19 21 22 27 28 28 29 30 30 32 32 34 35 36 38 39 41 42 44
VHDL and Verilog simulation 2.1 Starting the Modelsim graphical environment . . . . . . . . . . 2.2 Simulation of (pre-synthesis) RTL VHDL models . . . . . . . . 2.3 Simulation of the post-synthesis Verilog model with timing data 2.4 Simulation of the post-route Verilog model with timing data . .
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Logic synthesis 3.1 Starting the Design Vision graphical environment . . . . . . . . . . . . . . . . . . . . . . 3.2 RTL VHDL model analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Design elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Design environment denition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Design constraint denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Design mapping and optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Report generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 VHDL/Verilog gate-level netlist generation and post-synthesis timing data (SDF) extraction 3.9 Design constraints generation for placement and routing . . . . . . . . . . . . . . . . . . 3.10 Design optimization with tighter constraints . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard cell placement and routing 4.1 Starting the Encounter graphical environment 4.2 Generate uniquied netlist . . . . . . . . . . 4.3 Design import . . . . . . . . . . . . . . . . . 4.4 Floorplan Specication . . . . . . . . . . . . 4.5 Global net connections . . . . . . . . . . . . 4.6 Power ring/stripe creation and routing . . . . 4.7 Operating conditions denition . . . . . . . 4.8 Core cell placement . . . . . . . . . . . . . 4.9 Post-placement timing analysis . . . . . . . 4.10 Clock tree synthesis (optional) . . . . . . . . 4.11 Filler cell placement . . . . . . . . . . . . . ii
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CONTENTS 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 Design routing . . . . . . . . . . . . . . . . Post-routing timing optimization and analysis Design checks . . . . . . . . . . . . . . . . Report generation . . . . . . . . . . . . . . . Post-route timing data extraction . . . . . . . Post-route netlist generation . . . . . . . . . GDS2 le generation . . . . . . . . . . . . . Using scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii 45 46 46 50 53 54 54 55 56 56 60 63 66 70 70 70 75 75 80 81 83 84 85 86 86 89
A Appendix A: VHDL Netlists A.1 File: lter.vhd . . . . . . A.2 File: lter_top.vhd . . . A.3 File: lter_soc.vhd . . . A.4 File: lter_soc_tb.vhd . .
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B Appendix B: Tool Scripts B.1 Synopsys: Design Compiler B.1.1 lter_soc_syn.tcl . . B.2 Cadence: SOC Encounter . . B.2.1 start.tcl . . . . . . . B.2.2 fplan.tcl . . . . . . . B.2.3 pplan.tcl . . . . . . . B.2.4 place.tcl . . . . . . . B.2.5 cts.tcl . . . . . . . . B.2.6 route.tcl . . . . . . . B.2.7 pplan.tcl . . . . . . . B.2.8 verify.tcl . . . . . . C Appendix C: Design Metrics
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Chapter 1
Introduction
This document details the typical steps of a top-down digital VHDL/Verilog design ow with the help of one simple design example. The following tools are considered in this document: Modelsim v6.5e or higher, from Mentor Graphics. Design Compiler and Design Vision D-2010.03 or higher from Synopsys. Encounter 9.12 or higher from Cadence Design Systems. The design kit used is from Faraday. The process is L90_SP, a 90 nm 9-metal CMOS process. Each of the next chapters in this document is addressing a specic set of tasks. Chapter 2 is about VHDL and Verilog simulation, chapter 3 is about logic synthesis and chapter 4 is about place and route. Steps in these chapters are not necessarily to be done in the given sequence. Go to 1.5 Design ow steps to get a typical sequence of steps supporting a top-down approach.
1.1
Top-down design ow
Figure 1.1: Top-down design ow
CHAPTER 1. INTRODUCTION Figure 1.1 illustrates the top-down ow that includes the following steps:
VHDL RTL model creation The goal here is to develop synthesizable VHDL models at the RTL level (RTL means RegisterTransfer Level). Such models usually dene a clear separation between control parts (e.g. nite state machines-FSM) and operative parts (e.g. arithmetic and logic units). Registers are used to store small size data between clock cycles. RAM/ROM memories are used to store large amounts of data or program code. Blocks such as FSMs, ALUs, registers are usually described as behavioral models that do not imply any particular gate-level implementation. Tools used at this step can range from simple text editors to dedicated graphical environments that generate VHDL code automatically. RTL simulation The VHDL RTL models are validated through simulation by means of a number of testbenches also written in VHDL. RTL synthesis The synthesis process infers a possible gate-level realization of the input RTL description that meets user-dened constraints such as area, timings or power consumption. The design constraints are dened outside the VHDL models by means of tool-specic commands. The targeted logic gates belong to a library that is provided by a foundry or an IP company as part of a so-called design kit. Typical gate libraries include a few hundreds of combinational and sequential logic gates. Each logic function is implemented in several gates to accommodate several fan-out capabilities or drive strengths. The gate library is described in a tool-specic format that denes, for each gate, its function, its area, its timing and power characteristics and its environmental constraints. The synthesis step generates several outputs: a gate-level VHDL netlist, a Verilog gate-level netlist, and a SDF description. The rst netlist is typically used for post-synthesis simulation, while the second netlist is better suited as input to the place&route step. The SDF description includes delay information for simulation. Note that considered delays are at this step correct for the gates but only estimated for the interconnections. Post-synthesis gate-level simulation The testbenches used for RTL model validation can be reused (with possibly some modications to use the VHL gate-level netlists). The gate-level simulation makes use of VHDL models for the logic gates that are provided in the design kit. These VHDL models follow the VITAL modeling standard to ensure proper back-annotation of delays through the SDF les generated by the synthesis or the place&route step. Standard cell place and route The place&route (P&R) step infers a geometric realization of the gate-level netlist so-called a layout. The standard cell design style puts logic cells in rows of equal heights. As a consequence, all logic gates in the library have the same height, but may have different widths. Each cell has a power rail at its top and a ground rail at its bottom. The interconnections between gates are today usually done over the cells since current processes allow several metal layers (i.e. 9 metal layers for the Faraday L90_SP process). As a consequence, the rows may be abutted and ipped so power and ground rails are shared between successive rows. The P&R step generates several outputs: a geometric description (layout) in GDS2 format, a SDF description and a Verilog gate-level netlist. The SDF description now includes interconnect delay. The Verilog netlist may be different from the one read as input as the P&R step may make further timing optimizations during placement, clock tree generation and routing (e.g. buffer insertion). Post-layout gate-level simulation
CHAPTER 1. INTRODUCTION
The Verilog gate-level netlist can be simulated by using the existing VHDL testbenches and the more accurate SDF data extracted from the layout. System-level integration The layout description is then integrated as a block in the designed system. This step is not covered in this document.
1.2
Design project organisation
First we have to setup a proper work environment. The toolscripts need the CSH shell as command shell while the standard shell after login is the Bash shell. So rst we take care that the CSH shell is our default command shell by:
cp /opt/eds/DesignLab/bin/dot.bashrc ~/.bashrc
Now close the current terminal window and start a new terminal. Then add the DesignLab script directory to our PATH by:
source /opt/eds/DesignLab/bin/dlab.csh
Given the number of EDA tools and les used in the ow, it is strongly recommended to organize the working environment in a proper way. To that end, the create_eda_project script can be used to create a directory structure in which design les will be stored. The use of the script is as follows:
create_eda_project <project-name>
where <project-name> is the name of the top-level directory that will host all design les for the projects. For example, to create the project directory called FILTER that will be used to do the tasks presented in the rest of this document, execute the following command:
student@tango> create_eda_project FILTER student@tango> cd FILTER
The FILTER top-level directory hosts the conguration les for logic simulation (Modelsim), logic synthesis (Synopsys DC) and standard cell place and route (Cadence SoC Encounter). As a consequence, it is required that the tools are always started from that point. One exception is full-custom layout tools (Cadence IC) that must be started from the subdirectory LAY, which hosts different conguration les. Figure 1.2 gives the proposed directory structure and the role of each subdirectory. The actual use of the subdirectories and les will be explained while going throughout the tutorial in this document.
<project-name> |-- .synopsys_dc.setup |-- modelsim.ini |-- DOC |-- HDL | |-- GATE | |-- RTL | -- TBENCH |-- IP |-- LAY |-- LIB | |-- MSIM | -- SNPS |-- PAR | |-- BIN | |-- CONF | |-- CTS | |-- DB | |-- DEX | |-- LOG | |-- RPT | |-- SDC | |-- TEC | -- TIM |-- SIM | |-- BIN | -- OUT -- SYN |-- BIN |-- DB |-- LOG |-- RPT |-- SDC -- TIM # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # project directory home setup file for Synopsys tools setup file for Modelsim tool documentation (pdf, text, etc.) VHDL/Verilog source files gate-level netlists RTL descriptions testbenches external blocks (e.g., memories) full-custom layout files design libraries Modelsim library (VHDL, Verilog) Synopsys library (VHDL, Verilog) place & route files commands, scripts configuration files clock tree synthesis files database files design exchange files log files report files system design constraint files technology files timing files simulation files commands, scripts output files (e.g., waveforms) synthesis files commands, scripts database files log files report files system design constraint files timing files
Figure 1.2: Design project structure.
1.3
EDA tools and design kit conguration
The text le edadk.conf lists both tools and designkit to use. The tech_setup command reads this le and setup your technology environment. In order to use the EDA tools and Faraday design kit, a script le called edadk.csh with the necessary PATHs to the tools exists in the directory from which the tools are launched (the top-level project directory). Add these PATHs to your current environment by executing:
student@tango-FILTER> tech_setup student@tango-FILTER> source edadk.csh
For information on the FARADAY design kits, nd the FARADAY documentation in /opt/eds/DesignLab/tech/Faraday/L90_SP/Docs.
1.4
VHDL example: FIR-Filter
The FIR-Filter example will be used as the reference design throughout the topdown ow. Microelectronic chips require specialized circuitry for electrostatic discharge (ESD) protection and to be able to drive large off-chip loads. These input/output (I/O) drivers also include bonding pads that enable physical connection between the microchip and the package. I/O drivers are basically specialized buffers, much larger than regular standard cells, and are designed to be placed around the core. While physical design is not our job at the moment, the nished top-level design needs to include these I/O drivers. The most convenient way to include the I/O drivers is to add a new hierarchy level. In our example the top level design is called lter_top and can be found under HDL/RTL/lter_top.vhd (See App. A.2. The hierarchy level that instantiates lter_top and the I/O drivers will be called SOC and is found in HDL/RTL/lter_soc.vhd (See App. A.3). Figure 1.3 shows the levels of hierarchy. The coefcient LUT will be implemented as a ROM. Listing ?? gives the declaration of the SOC level VHDL model of FIR-Filter.
Figure 1.3: VHDL design hierarchy
Listing 1.1: Declaration of the synthesisable FIR-Filter.
library ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; 3 u s e i e e e . n u m e r i c _ s t d . a l l ; l i b r a r y techmap ; u s e t e c h m a p . gencomp . a l l ; 8 entity filter_soc is generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 1 6 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ); end f i l t e r _ s o c ; architecture r t l of f i l t e r _ s o c i s c o m p o n e n t d e c l a r a t i o n s component f i l t e r _ t o p i s generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 1 6 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ); end component ;
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s i g n a l d e c l a r a t i o n s s i g n a l ClkxCI_s : s t d _ l o g i c ; s i g n a l ResetxRBI_s : s t d _ l o g i c ; s i g n a l D a t a I n x D I _ s : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; s i g n a l DataInReqxSI_s : s t d _ l o g i c ; s i g n a l DataInAckxSO_s : s t d _ l o g i c ; s i g n a l DataOutxDO_s : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; s i g n a l DataOutReqxSO_s : s t d _ l o g i c ; s i g n a l DataOutAckxSI_s : s t d _ l o g i c ; s i g n a l VCCIO : s t d _ u l o g i c _ v e c t o r ( 7 downto 0 ) ; s i g n a l GNDIO : s t d _ u l o g i c _ v e c t o r ( 7 downto 0 ) ; s i g n a l VCCCO : s t d _ u l o g i c ; s i g n a l GNDCO : s t d _ u l o g i c ; constant padtech : i n t e g e r := faraday ; constant p a d l e v e l : i n t e g e r := 0; begin Pad I n s t a n t i a t i o n s Power Pads io_VCCIO : v c c i o p a d v g e n e r i c map ( w i d t h => 8 , t e c h => p a d t e c h , l i m i t => c o r e _ l i m i t e d ) p o r t map ( VCCIO ) ; io_GNDIO : g n d i o p a d v g e n e r i c map ( w i d t h => 8 , t e c h => p a d t e c h , l i m i t => c o r e _ l i m i t e d ) p o r t map (GNDIO) ; io_VCCCO : v c c c o p a d g e n e r i c map ( t e c h => p a d t e c h , l i m i t => core_limited ) p o r t map (VCCCO) ; io_GNDCO : g n d c o p a d g e n e r i c map ( t e c h => p a d t e c h , l i m i t => core_limited ) p o r t map (GNDCO) ; S i g n a l Pads i o _ C l k x C I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( ClkxCI , C l k x C I _ s ) ; i o _ R e s e t x R B I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( ResetxRBI , R e s e t x R B I _ s ) ; i o _ D a t a I n x D I : i n p a d v g e n e r i c map ( w i d t h => DWIDTH, t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( D a t a I n x D I , D a t a I n x D I _ s ) ; i o _ D a t a I n R e q x S I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( D a t a I n R e q x S I , D a t a I n R e q x S I _ s ) ; io_DataInAckxSO : o u t p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l =>
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p a d l e v e l , s l e w => f a s t , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataInAckxSO , DataInAckxSO_s ) ; io_DataOutxDO : o u t p a d v g e n e r i c map ( w i d t h => DWIDTH, t e c h => p a d t e c h , l e v e l => p a d l e v e l , s l e w => f a s t , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataOutxDO , DataOutxDO_s ) ; io_DataOutReqxSO : o u t p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , s l e w => f a s t , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataOutReqxSO , DataOutReqxSO_s ) ; i o _ D a t a O u t A c k x S I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataOutAckxSI , D a t a O u t A c k x S I _ s ) ; Component I n s t a n t i a t i o n s i_filter_top : filter_top g e n e r i c map ( CWIDTH => CWIDTH, CAW => CAW, DWIDTH => DWIDTH, DAW => DAW) p o r t map ( ClkxCI => ClkxCI_s , R e s e t x R B I => R e s e t x R B I _ s , D a t a I n x D I => D a t a I n x D I _ s , D a t a I n R e q x S I => D a t a I n R e q x S I _ s , DataInAckxSO => DataInAckxSO_s , DataOutxDO => DataOutxDO_s , DataOutReqxSO => DataOutReqxSO_s , DataOutAckxSI => D a t a O u t A c k x S I _ s ); end r t l ; Lines 73 to 98 instantiate generic components for IO cells dened in the technology independent library techmap. To install the VHDL model and its associated testbenches in the project directory, enter the following command in the top-level project directory FILTER:
student@tango-FILTER> install_design filter
Appendix A.4 gives the testbench for the RTL model (le lter_soc_tb.vhd). The testbench for the mapped netlist (le lter_soc_mapped_tb.vhd) can also be used for the simulation of the placed and routed Verilog netlist. The le lter_soc.io denes the positions of the IO pins for place and route. The le lter_soc_syn.tcl in directory SYN/BIN is a Tcl script that performs synthesis of the VHDL model in batch mode. The le top_level.tcl in directory PAR/BIN is a Tcl script that performs the placement and routing of the synthesized Verilog netlist in batch mode.
1.5
Design ow steps
Here are the main steps of the top-down design ow with references to the sections in the document that give more details.
CHAPTER 1. INTRODUCTION Step 1) Pre-synthesis VHDL simulation (tool: Modelsim) 2.1 Compilation of the RTL VHDL model and related testbench [2.2] 2.2 Simulation of the RTL VHDL model Step 2) Logic synthesis (tool: Synopsys Design Compiler) 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 RTL VHDL model analysis [3.2] Design elaboration (generic synthesis) [3.3] Design environment denition (operating conditions, wire load model) [3.4] Design constraint denitions (area, clock, timings) [3.5] Design mapping and optimization (mapping to gates) [3.6] Report generation [3.7] VHDL gate-level netlist generation [3.8] Post-synthesis timing data (SDF) generation for the VHDL netlist [3.8] Verilog gate-level netlist generation [3.8] Design constraints generation for placement and routing [3.9]
Step 3) Post-synthesis VHDL simulation (tool: Modelsim) [2.3] 4.1 Compilation of the VHDL/Verilog netlist and related testbench 4.2 Simulation of the post-synthesis gate-level netlist with timing data Step 4) Placement and routing (tool: Cadence Encounter) 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 Generate a uniquied netlist (Convert Verilog mapped netlist) [??] Design import (technological data + Verilog netlist) [4.3] Floorplan specication [4.4] Power ring/stripe creation and routing [4.6] Global net connections denition [4.5] Operating conditions denition [4.7] Core cell placement [4.8] Post-placement timing analysis [4.9] Clock tree synthesis (optional) [4.10] Design routing [4.12] Post-route timing optimization and analysis [4.13] Filler cell placement [4.11] Design checks [4.14] Report generation [4.15] Post-route timing data extraction [4.16] Post-route netlist generation [4.17] GDS2 le generation [4.18]
Step 5) Post-layout VHDL/Verilog simulation (tool: Modelsim) [2.4] 6.1 Compilation of the Verilog netlist and related testbench 6.2 Simulation of the post-synthesis or post-P&R gate-level netlist with PaR timing data
Chapter 2
VHDL and Verilog simulation

This chapter presents the main steps to perform the logic simulation of VHDL and Verilog models with the Modelsim tool.
2.1
Starting the Modelsim graphical environment

student@tango-FILTER> vsim &
To start the Modelsim environment, enter in the vsim command in the Unix shell:
Figure 2.1: Modelsim console window
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CHAPTER 2. VHDL AND VERILOG SIMULATION
11
The modelsim.ini le actually denes the mapping between logical design libraries and their physical locations. Note that the Help menu on the top right allows one to access the complete documentation of the tool. After having started the vsim GUI you have two options to simulate your model, either interactively or by executing the following convenience scripts (see directory SIM/BIN) on the VSIM command line: wave.do To start a wave window with the ports of the top level module. start_far_[mapped | routed ].do To start up the simulation of the particular module. run_far_[mapped | routed ].do To load the lter coefcients into the coefcient ROM and runs the simulation for 300 us.
2.2
Simulation of (pre-synthesis) RTL VHDL models
The task here is to validate the functionality of the VHDL model that will be synthesized. The rst step is to compile the VHDL model and its associated testbench. There are two ways to compile VHDL models. One way is to execute the vcom command from the command line of the Modelsim window:
ModelSim> ModelSim> ModelSim> ModelSim> ModelSim> ModelSim> ModelSim> ModelSim> vcom vcom vcom vcom vcom vcom vcom vcom HDL/RTL/SYAA90_128X16X1CM2.vhd HDL/RTL/SPAA90_512X16BM1A.vhd HDL/RTL/coeffFAR.vhd HDL/RTL/dataRamFAR.vhd HDL/RTL/filter.vhd HDL/RTL/filter_top.vhd HDL/RTL/filter_soc.vhd HDL/TBENCH/filter_soc_tb.vhd
or execute the shell script compile_msim_far.sh from the CSH command line:
student@tango-FILTER> sh compile_msim_far.sh
The other way is to left-click on the Compile icon and HDL/TBENCH directories, click on Compile and nally close the window (click Done). The compiled modules are stored in the logical library WORK which is mapped to the physical location LIB/MSIM. Once VHDL (or Verilog) models have been successfully compiled in the design library, it is possible to create a make le that can be used to recompile only the required les. The vmake command can only be run from a Unix shell and creates the make le:
student@tango-FILTER> vmake > Makefile
, to select the les to compile in the HDL/RTL
The created le Makele now denes the design unit dependencies and the compilation commands to recompile only those source les that have been modied or that depend on modied les. To rebuild the library, run the make command in the Unix shell To simulate the RTL model, select the main menu item Simulate Start simulation... to get the simulation dialog window. Select in the Design Tab from library work the architecture of the testbench and a resolution of ns. Then click OK.
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The main window now changes a bit to show the simulation hierarchy, the list of signals in the testbench and the simulation console (with now the VSIM number> prompt). Left clicking twice on an instance in the simulation hierarchy pane displays the corresponding VHDL source in the right pane.
The next step is to select the signals to display in simulation. Right click in the Objects (top center) pane, then select Add to Wave Signals in Region. Note that the appropriate hierarchy level is selected in the simulation hierarchy window. Selecting another level, e.g. dut, will display all the signals visible in this scope. You may want to add selected signals from inner levels (local signals). The selected signals are displayed in a new window called wave. The wave pane is by default located on the top right (as a new tab on the source windows). You can click on the Undock icon to make the wave pane separate. Now rst load the content coefcient le into the coefcient memory:
VSIM 7> run 35 ns VSIM 7> do SIM/BIN/load.do
Then to start the simulation, it is either possible to enter run commands in the simulation console such as:
VSIM 7> run 300 us
or to click on the Run icon in the main window or in the wave window. The signal waveforms are then visible in the wave window. To change the radix of the displayed signals, select the signals (press shift left-click for multiple selection), then select the wave menu item Format Radix Unsigned.
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Note that the command run -all runs the simulation until there is no more pending event in the simulation queue. This could lead to never ending simulation when the model, like the testbench loaded here, has a continuously switching signal such as the clock signal clk. It is however possible to stop the current simulation by clicking the Break icon in the main window or in the wave window.
Run the simulation interactively as described in the previous section or run the following scripts (See SIM/BIN) from the VSIM command line.
VSIM 7> do SIM/BIN/start_far.do VSIM 8> do SIM/BIN/wave.do VSIM 9> do SIM/BIN/run_far.do
If you make any modication to the VHDL source, you need to recompile the sources (manually or using the vmake command described earlier in this section), and then restart the simulation in the same environment (e.g., the same displayed waveforms or the same simulation breakpoints) with the restart -f command.
2.3
Simulation of the post-synthesis Verilog model with timing data
This step occurs after the RTL model has been synthesized into a gate-level netlist. The timing information about the design which includes the delay of the library cells only is stored in a SDF le. (See -3.8 VHDL/Verilog gate-level netlist generation and post-synthesis timing data (SDF) extraction.) Compile the Verilog gate-level netlist generated by the logic synthesis and its testbench in a new library called mapped:
vlib LIB/MSIM/mapped ModelSim> vcom -work ModelSim> vcom -work ModelSim> vlog -work ModelSim> vcom -work LIB/MSIM/mapped LIB/MSIM/mapped LIB/MSIM/mapped LIB/MSIM/mapped HDL/RTL/SYAA90_128X16X1CM2.vhd HDL/RTL/SPAA90_512X16BM1A.vhd HDL/GATE/filter_soc_mapped.v HDL/TBENCH/filter_soc_tb_mapped.vhd
or execute the shell script compile_msim_far_mapped.sh. To simulate the RTL model, 1. Select the main menu item Simulate Start simulation... to get the simulation dialog window. 2. Select from library mapped the architecture of the testbench and a resolution of 100ps. 3. Click the Libraries tab to add the gate libraries fsd0a_a_generic_core and fod0a_b25_t25_generic_io,
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4. Then click the SDF tab. In the SDF dialog window, add the le SYN/TIM/lter_soc_mapped.sdf and specify the region dut, which is the label of the instance in the testbench that will be annotated with timing data. Note that the Reduce SDF errors to warnings box must be checked. This is required to avoid the simulation to stop prematurely due to errors such as "Failed to nd port a(7)". These are not really errors here as they are related to interconnect delay data in the SDF le that are not used in the simulation (they are actually all set to zero).
Then click OK in the remaining Start Simulation dialog box to load the mapped netlist. Clock to output delays of the order of 100ps to 1ns should be visible in the wave window. Run the simulation interactively as described in the previous section or run the following scripts (See SIM/BIN) from the VSIM command line.
VSIM 7> do SIM/BIN/start_far_mapped.do VSIM 8> do SIM/BIN/wave.do VSIM 9> do SIM/BIN/run_far_mapped.do
2.4
Simulation of the post-route Verilog model with timing data
This step occurs after the design has been placed and routed. The Post-route SDF-le contains cell delay and wire delays of the circuit. See "4.16 Post-route timing data extraction" and "4.17 Post-route netlist generation". This step involves the simulation of a Verilog gate-level netlist with a VHDL testbench. Com-
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pile the Verilog gate-level netlist generated by the logic synthesis and its testbench in a new library called routed:
vlib LIB/MSIM/routed ModelSim> vcom -work ModelSim> vcom -work ModelSim> vlog -work ModelSim> vlog -work ModelSim> vcom -work LIB/MSIM/routed LIB/MSIM/routed LIB/MSIM/routed LIB/MSIM/routed LIB/MSIM/routed HDL/RTL/SYAA90_128X16X1CM2.vhd HDL/RTL/SPAA90_512X16BM1A.vhd HDL/GATE/faraday-io.v HDL/GATE/filter_soc-routed.v HDL/TBENCH/filter_soc_tb_mapped.vhd
or execute the shell script compile_msim_far_routed.sh.
To simulate the placed and routed netlist with timing data: 1. Select the item Simulate Start simulation... in the main menu to get the simulation dialog window. 2. Select from library routed the architecture of the testbench and a resolution of 100ps. 3. Then click the Libraries tab to add the gate libraries fsd0a_a_generic_core and fod0a_b25_t25_generic_io 4. Load the SDF timing le PAR/TIM/lter_soc-routed.sdf. Note that the Reduce SDF errors to warnings box must be checked. This is required to avoid the simulation to stop prematurely due to errors such as Failed to nd matching specify timing constraint. These are not really errors here as they are related to removal (asynchronous) timing constraints generated by Encounter that are not supported in the Verilog models of the gates. Run the simulation interactively or run the following scripts (See SIM/BIN) from the VSIM command line.
VSIM 7> do SIM/BIN/start_far_routed.do VSIM 8> do SIM/BIN/wave.do VSIM 9> do SIM/BIN/run_far_routed.do
Chapter 3
Logic synthesis
This chapter presents the main steps to perform the logic synthesis of the VHDL RTL model with the Synopsys Design Vision and Design Compiler tools. The sold alias displays the complete Synopsys documentation set. Manual pages are available by executing the command snps man command (e.g., snps man design_vision).
3.1
Starting the Design Vision graphical environment

student@tango-FILTER> design_vision
To start the Synopsys Design Vision environment, enter the design_vision command in a new shell:
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CHAPTER 3. LOGIC SYNTHESIS
17
The command line is also echoed in the terminal shell from which the tool has been started, so it is possible to enter DC commands from there as well (the shell has the design_vision> prompt). It is still possible to execute some Unix commands from here.
3.2
RTL VHDL model analysis
The analysis phase compiles the VHDL model and checks that the VHDL code is synthesizable. Select File Analyze... in the main menu. Use the Add... button to add all the VHDL sources you need to analyze. In the case you have more than one VHDL le to analyze, be careful to list the les in the correct analysis order. Click OK.
3.3
Design elaboration
The elaboration phase performs a generic presynthesis of the analyzed model. It essentially identies the registers that will be inferred. Select File Elaborate... in the main menu. The DEFAULT library is identical to the WORK library. Specify the value for the CWIDTH, DWIDTH generic parameters to 16 and for the CAW, DAW parameters 7. Click OK. The console now displays the inferred registers and the kind of reset (here asynchronous reset AR: Y).
design_vision> elaborate FILTER_SOC -architecture RTL -library WORK -parameters "CWIDTH = 16, CAW = 7, DWIDTH = 16, DAW = 7, CWIDTH = 16" ... Inferred memory devices in process in routine filter_DWIDTH16_DAW7 line 158 in file /mnt/tango/md2/users/sander/ET4351/asic/designs/filter1/HDL/ RTL/filter.vhd. =============================================================================== | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =============================================================================== | OutRegxDP_reg | Flip-flop | 16 | Y | N | Y | N | N | N | N | =============================================================================== ... design_vision> Current design is filter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7.
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Note the name lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 given to the elaborated entity. It is possible to display the elaborated schematic by selecting the entity i_lter_top in the hierarchy window and then clicking the Create Design Schematic icon components that do not yet represent any real logic gate. . Note that the symbols merely indicate generic
3.4
Design environment denition
Before a design can be optimized, you must dene the environment in which the design is expected to operate. You dene the environment by specifying operating conditions, wire load models, and system interface characteristics. Operating conditions include temperature, voltage, and process variations. Wire load models estimate the effect of wire length on design performance. System interface characteristics include input drives, input and output loads, and fanout loads. The environment model directly affects design synthesis results. Here we will only deal with operating conditions and wire load models. To dene the operating conditions, select the main menu item Select the WCCOM condition, which denes a temperature of 125C, a voltage of 0.9V (the L90_SP process is a 1V process), and a slow process. Each cell library denes its own set of operating conditions and may use different names for each set. Click OK. Wire load models allow the tool to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. The FARADAY design kit denes a number of wire load models. It also denes an
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automatic selection of the wire load model to use according to the design area, which is actually considered here. To get the denitions of the available operating conditions (and on the cell library), execute the report_lib command in the tool command line: report_lib fsd0a_a_generic_core_ss0p9v125c The report_design command summarizes the denitions of the design environment.
3.5
Design constraint denitions
Many kinds of constraints may be dened on the design. Here only constraints on the area and the clock will be dened. To dene the clock attributes, i.e. its period and duty cycle, select the entity lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 in the hierarchy window and then click the Create Symbol View icon. In the symbol view, select the clk pin and then select the main menu item Attributes Specify Clock.... Dene a clock period of 10 ns with 50% duty cycle. Time unit is not specied here. It is dened in the cell library and is usually ns. Click OK. The console now includes the command line equivalent of the clock denition:
create_clock -name "clk" -period 10 -waveform { 0 5 } { clk }
To dene an area constraint, select in the main menu the item Attributes Optimization Constraints Design Constraints.... A max area constraint set to zero is not realistic but it will force the synthesizer to target a minimum area. Click OK. The console now includes the command line equivalent of the constraint denition: set_max_area 0
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It is a now good idea to save the elaborated design so it will be possible to run several optimization steps from that point. Select the entity lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 in the hierarchy window and then the main menu item File Save As.... Save the elaborated design under the name lter_soc_elab.ddc in the SYN/DB directory. The selection of the option Save all design in hierarchy is relevant for hierarchical designs. The console includes the equivalent command line: write -hierarchy -format ddc -output .../FILTER/SYN/DB/lter_soc_elab.ddc To read back an elaborated design, select the main menu item File Read... and then select the le to read.
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3.6
Design mapping and optimization
The optimization phase, also called here compilation phase, is technology dependent. It performs the assignment of logic gates from the standard cell library to the elaborated design in such a way the dened constraints are met. Select the main menu item Design Compile Ultra.... For a rst run there is no need to change the default settings. Click OK. The console and the Unix shell now include the progress of the work. The equivalent command line is: compile_ultra -map_effort medium -area_effort medium
The mapped design schematic is now hierarchical as it includes instances of the coefcient rom, data ram and the lter circuit. Also, the cells are now real gates from the cell library. Note that the default resource allocation and implementation for operative parts is based on timing constraints. This means that resource sharing is used so that timing constraints are met or not worsened. In our case, a
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single adder has been inferred for both adder and subtractor operations. The mapped design can now be saved. Select the entity lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 in the hierarchy window and then the main menu item File Save As.... Save the mapped design under the name lter_soc_mapped.ddc in the directory SYN/DB.
3.7
Report generation
It is possible to get many reports on various synthesis results. Here only reports on the area used, critical path timing and the resources used will be generated. To get a report of the area used by the mapped design, select the main menu item Design > Report Area.... Save the report in the le SYN/RPT/lter_soc_mapped_area.rpt as well as in the report viewer. Click OK. A new window and the console now display the report:
I n f o r m a t i o n : U p d a t i n g g r a p h . . . ( UID 83) Report : area Design : f i l t e r _ s o c V e r s i o n : D 2010.03 SP5 1 Date : Wed May 30 1 3 : 5 2 : 1 0 2012 I n f o r m a t i o n : U p d a t i n g d e s i g n i n f o r m a t i o n . . . ( UID 85) L i b r a r y ( s ) Used : f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Core / f s d 0 a _ a / 2 0 1 0 Q4v2 . 1 / GENERIC_CORE / F r o n t E n d / s y n o p s y s / s y n t h e s i s / f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c . db ) f o d 0 a _ b 2 5 _ t 2 5 _ g e n e r i c _ i o _ s s 0 p 9 v 1 2 5 c ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / IO / f o d 0 a _ b 2 5 / 2 0 0 9 Q2v3 . 0 / T25_GENERIC_IO / F r o n t E n d / s y n o p s y s / f o d 0 a _ b 2 5 _ t 2 5 _ g e n e r i c _ i o _ s s 0 p 9 v 1 2 5 c . db )

SYAA90_128X16X1CM2_BC ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Memory / SYAA90_128X16X1CM2_BC . db ) SPAA90_512X16BM1A_BC ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Memory / SPAA90_512X16BM1A_BC . db ) Number Number Number Number of of of of ports : nets : cells : references : 38 78 97 24 176044.062891 190436.095396 u n d e f i n e d ( Wire l o a d h a s z e r o n e t a r e a ) 366480.158287 undefined
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Combinational area : Noncombinational area : Net I n t e r c o n n e c t a r e a : Total cel l area : Total area : 1
The area unit depends on the standard cell library. Here all area gures are in square microns. The net interconnect area is estimated with the use of a wire load model that has been automatically selected from the design area. To get a report on the most critical timing path in the mapped design, select the main menu item Timing Report Timing Path Save the report in the le SYN/RPT/lter_soc_mapped_timing.rpt as well as in the report viewer. Click OK. A new window and the console now display the report:
Report : timing p a t h f u l l d e l a y max m a x _ p a t h s 1 s o r t _ b y group

Design : f i l t e r _ s o c V e r s i o n : D 2010.03 SP5 1 Date : Wed May 30 1 3 : 5 2 : 1 3 2012 O p e r a t i n g C o n d i t i o n s : WCCOM Library : fsd0a_a_generic_core_ss0p9v125c Wire Load Model Mode : e n c l o s e d S t a r t p o i n t : i _ f i l t e r _ t o p / i _ f i l t e r / StatexDP_reg [0] ( r i s i n g edge t r i g g e r e d f l i p f l o p c l o c k e d by ClkxCI ) E n d p o i n t : DataInAckxSO ( o u t p u t p o r t c l o c k e d by ClkxCI ) P a t h Group : ClkxCI P a t h Type : max Des / C l u s t / P o r t Wire Load Model Library filter_soc G5K fsd0a_a_generic_core_ss0p9v125c filter_DWIDTH16_DAW7 enG5K fsd0a_a_generic_core_ss0p9v125c Point Incr Path c l o c k ClkxCI ( r i s e e d g e ) 0.00 0.00 clock network delay ( i d e a l ) 0.00 0.00 i _ f i l t e r _ t o p / i _ f i l t e r / S t a t e x D P _ r e g [ 0 ] / CK ( DFFRBX1 ) 0.00 0.00 r i _ f i l t e r _ t o p / i _ f i l t e r / S t a t e x D P _ r e g [ 0 ] / QB ( DFFRBX1 ) 0.35 0.35 f i _ f i l t e r _ t o p / i _ f i l t e r / U178 / O ( NR2X1 ) 0.69 1.03 r i _ f i l t e r _ t o p / i _ f i l t e r / DataInAckxSO ( filter_DWIDTH16_DAW7 ) 0.00 1.03 r i _ f i l t e r _ t o p / DataInAckxSO ( filter_top_CWIDTH16_CAW7_DWIDTH16_DAW7 ) 0.00 io_DataInAckxSO / x0 / op / O (VYA4GSGB) 3.03 4.06 r DataInAckxSO ( o u t ) 0.00 4.06 r data a r r i v a l time 4.06 c l o c k ClkxCI ( r i s e e d g e ) 8.00 8.00 clock network delay ( i d e a l ) 0.00 8.00 output external delay 0.80 7.20 data r e q u i r e d time 7.20 data r e q u i r e d time 7.20 data a r r i v a l time 4.06 s l a c k (MET) 3.14
24
1.03 r
All times are expressed in ns (the time unit is dened in the cell library). The slack denes the time margin from the clock period. A positive slack means that the latest arriving signal in the path still arrives before the end of the clock period. A negative slack means that the timing constraint imposed by the clock is violated. The timing delays that are accounted for are the internal gate delays (from the cell library) and the estimated interconnect delays (from the cell library and the wire load model in use). To highlight the critical path on the schematic, select the lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 entity in the hierarchy window and then the Select menu item Schematic New Path Schematic View Of Paths From/Through/To... . You can see that the critical path goes from pin DO(1) of instance .../i_lter_top/i_coeff/a9d16 to pin D of instance .../i_lter/OutRegxDP_reg[15]. Another useful report is the list of resources used. A resource is an arithmetic or comparison operator read in as part of an HDL design. Resources can be shared during execution of the compile command.
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To get a report on the resources used, select the main menu item Design Report Design Resources.... Save the report in the le SYN/RPT/lter_soc_mapped_resources.rpt as well as in the report viewer. Click OK. As the report stated no special operator were found in our lter_soc design. The last useful report is the one on power used. Here a estimate on power consumption is given based on switch activity and the library models used in the circuit. To get a report on the power used, select the main menu item Design Report Power.... Save the report in the le SYN/RPT/lter_soc_mapped_power.rpt as well as in the report viewer. Click OK.
A new window and the console now display the report:
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L o a d i n g db f i l e / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / IO / f o d 0 a _ b 2 5 / 2 0 0 9 Q2v3 . 0 / T25_GENERIC_IO / F r o n t E n d / s y n o p s y s / f o d 0 a _ b 2 5 _ t 2 5 _ g e n e r i c _ i o _ s s 0 p 9 v 1 2 5 c . db L o a d i n g db f i l e / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Core / f s d 0 a _ a / 2 0 1 0 Q4v2 . 1 / GENERIC_CORE / F r o n t E n d / s y n o p s y s / s y n t h e s i s / f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c . db L o a d i n g db f i l e / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Memory / SPAA90_512X16BM1A_BC . db L o a d i n g db f i l e / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Memory / SYAA90_128X16X1CM2_BC . db I n f o r m a t i o n : P r o p a g a t i n g s w i t c h i n g a c t i v i t y ( low e f f o r t z e r o d e l a y s i m u l a t i o n ) . (PWR 6) Warning : D e s i g n h a s u n a n n o t a t e d p r i m a r y i n p u t s . (PWR 414) Warning : D e s i g n h a s u n a n n o t a t e d s e q u e n t i a l c e l l o u t p u t s . (PWR 415) Warning : D e s i g n h a s u n a n n o t a t e d b l a c k box o u t p u t s . (PWR 428) R e p o r t : power a n a l y s i s _ e f f o r t low Design : f i l t e r _ s o c V e r s i o n : D 2010.03 SP5 1 Date : Wed May 30 1 3 : 5 2 : 1 3 2012
L i b r a r y ( s ) Used : f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Core / f s d 0 a _ a / 2 0 1 0 Q4v2 . 1 / GENERIC_CORE / F r o n t E n d / s y n o p s y s / s y n t h e s i s / f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c . db ) f o d 0 a _ b 2 5 _ t 2 5 _ g e n e r i c _ i o _ s s 0 p 9 v 1 2 5 c ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / IO / f o d 0 a _ b 2 5 / 2 0 0 9 Q2v3 . 0 / T25_GENERIC_IO / F r o n t E n d / s y n o p s y s / f o d 0 a _ b 2 5 _ t 2 5 _ g e n e r i c _ i o _ s s 0 p 9 v 1 2 5 c . db ) SYAA90_128X16X1CM2_BC ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Memory / SYAA90_128X16X1CM2_BC . db ) SPAA90_512X16BM1A_BC ( F i l e : / o p t / e d s / D e s i g n L a b / t e c h / F a r a d a y / L90_SP / Memory / SPAA90_512X16BM1A_BC . db )
O p e r a t i n g C o n d i t i o n s : WCCOM Library : fsd0a_a_generic_core_ss0p9v125c Wire Load Model Mode : e n c l o s e d Design Wire Load Model Library filter_soc G5K fsd0a_a_generic_core_ss0p9v125c filter_top_CWIDTH16_CAW7_DWIDTH16_DAW7 enG30K f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c f a r a d a y _ v c c c o p a d _ l i m i t 1 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d c o p a d _ l i m i t 1 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 7 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 7 enG5K fsd0a_a_generic_core_ss0p9v125c filter_DWIDTH16_DAW7 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 6 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 5 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 4 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 3 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 2 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 1 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ g n d i o p a d _ l i m i t 1 _ 0 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 6 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 5 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 4 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 3 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 2 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 1 enG5K fsd0a_a_generic_core_ss0p9v125c f a r a d a y _ v c c i o p a d _ l i m i t 1 _ 0 enG5K fsd0a_a_generic_core_ss0p9v125c
Global Operating Voltage = 0.9 Power s p e c i f i c u n i t i n f o r m a t i o n : V o l t a g e U n i t s = 1V Capacitance Units = 1.000000 pf Time U n i t s = 1 n s Dynamic Power U n i t s = 1mW ( d e r i v e d from V, C , T u n i t s ) L e a k a g e Power U n i t s = 1pW
C e l l I n t e r n a l Power Net S w i t c h i n g Power T o t a l Dynamic Power
= =
1 . 4 1 0 8 mW 7 9 . 1 4 8 7 uW = 1 . 4 8 9 9 mW
(95%) (5%) (100%)
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3.8
VHDL/Verilog gate-level netlist generation and post-synthesis timing data (SDF) extraction
This step generates a VHDL model of the mapped design for simulation and a Verilog model of the same design to be used as input to the placement and routing tool. It also generates a SDF (Standard Delay Format) le that includes the gate delays. Care should be taken to use the right naming scheme when generating the SDF le, otherwise the back-annotation of the delays onto the VHDL or Verilog netlists for simulation will fail. Here we only consider the back-annotation of VHDL netlists. Before generating the VHDL netlist, it is required to apply some VHDL naming rules to the design. This is done by entering the following command in the console (be sure that the entity lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 is selected in the hierarchy window): change_names -hierarchy -rules vhdl -verbose
Save the mapped design in the le lter_soc_mapped.vhd in the directory HDL/GATE. Note: the dialog window creates HDL les with the .vhdl extension rather than .vhd as used so far. Click Save. The console now echoes the equivalent command line:
write -hierarchy -format vhdl -output .../FILTER/HDL/GATE/filter\_mapped.vhd
To generate the SDF le, enter the following command in the console write_sdf -version 2.1 SYN/TIM/lter_soc_mapped.sdf Information: Annotated cell delays are assumed to include load delay. The informational message says that the estimated interconnect delays are actually included in the SDF le as part of the cell delays. The generated SDF le actually includes a list of interconnect delays of zero values. Before generating the Verilog netlist, it is better to reload the database and apply specic Verilog naming rules to the design. This is done by selecting File Remove All Designs from the main menu, then reading the database le ./SYN/DB/lter_soc_mapped.ddc, and entering the following command in the console (be sure that the entity lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7 is selected in the hierarchy window): change_names -hierarchy -rules verilog -verbose Save the mapped design in the le lter_soc_mapped.v in the directory HDL/GATE. Click Save. The console now echoes the equivalent command line: write -hierarchy -format verilog -output .../FILTER/HDL/GATE/lter_soc_mapped.v
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3.9
Design constraints generation for placement and routing
Both design environment and design constraint denitions may be stored in a format that can be read by other Synopsys tools such as PrimeTime or other EDA tool such as Cadence Soc Encounter. The following command creates a new le that includes the design constraints that have been dened for synthesis in Tcl format: write_sdc -nosplit SYN/SDC/lter_soc_mapped.sdc It is important to do that step after the Verilog naming rules have been applied to the mapped design (see 3.8), otherwise there could be discrepencies on port/signal names between the netlist and the constraint le.
3.10
Design optimization with tighter constraints
It is possible to let the synthesizer infer another faster adder architecture, e.g., a carry look-ahead architecture, by shortening the clock period. The goal here is to redo some steps in this chapter and to compare the low results with the ones obtained with the initially s clock. 1. Read the elaborated design. It is not necessary to re-analyze the VHDL sources. 2. Speciy the clock with a 1 ns period. 3. Save the new elaborated entity in the le SYN/DB/lter_soc_CWIDTH16_CAW7_DWIDTH16_DAW7_1ns_elab.db. 4. Map and optimize the design. 5. Save the mapped design in the le SYN/DB/lter_soc_1ns_mapped.db. 6. Get the new area, timing and resources reports. Compare with the reports you got for the 10 ns clock period. 7. Generate the VHDL gate-level netlist in HDL/GATE/lter_soc_1ns_mapped.vhdl and the associated SDF timing data le in SYN/TIM/lter_soc_1ns_mapped.sdf. 8. Do a post-synthesis simulation. 9. Generate the Verilog gate-level netlist in HDL/GATE/lter_soc_1ns_mapped.v. 10. Save the design constraints for placement and routing in the le SYN/SDC/lter_soc_1ns_mapped.sdc
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3.11
Using scripts
It is much more convenient to use scripts and to run the synthesis tool in batch mode when the design complexity increases. Scripts also conveniently capture the synthesis ow and make it reusable. Synopsys Design Compiler supports the Tcl language for building scripts. An example of such a script for the synthesis of the lter_soc design has been installed in the SYN/BIN directory (see ?? VHDL example: FIR-Filter). The script must be run from the project top directory and it assumed a directory organization as described in 1.2 Design project organisation. To run the Tcl script, execute the following command in a Unix shell:
student@tango-FILTER> dc_shell -f SYN/BIN/filter_soc_syn.tcl
When the script nishes executing, the dc_shell environment is still active so you can enter other dc_shell commands. Enter quit or exit to return to the Unix shell. The script is given below. It may be modied to dene design information and constraints and to control the ow to some extent.
Chapter 4
Standard cell placement and routing

This chapter presents the main steps to perform the placement and the routing of the synthesized gatelevel netlist using standard cells from the FARADAY design kit. The tool used here is Cadence Encounter (Velocity).
4.1
Starting the Encounter graphical environment

student@tango-FILTER> velocity -log PAR/LOG/encounter -overwrite
To start the Encounter environment, enter the velocity command in a new Unix shell:
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CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING
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that includes all commands entered in the session. If the -overwrite switch is not used, both log and command les are incremented at each new session. The Unix shell from which the tool is started is called the Encounter console. The console displays the velocity> prompt. This is where you can enter all Encounter text commands and where the tool displays messages. If you use the console for other actions, e.g., Unix commands, the Encounter session suspends until you nish the action. The main window includes three different design views that you can toggle during a session: the Floorplan view, the Amoeba view, and the Physical view. The Floorplan view displays the hierarchical module and block guides, connection ight lines, and oorplan objects, including block placement, and power/ground nets. The Amoeba view displays the outline of the modules and submodules after placement, showing physical locality of the module. The Physical view displays the detailed placements of the modules blocks, standard cells, nets, and interconnects. The main window includes a satellite window, which identies the location of the current view in the design display area, relative to the entire design. The chip area is identied by a yellow box, the satellite view is identied by the pink crossbox. When you display an entire chip in the design display area, the satellite crossbox encompasses the chip area yellow box. When you zoom and pan through the chip in the design display area, the satellite crossbox identies where you are relative to the entire chip. To move to an area in the design display area, click and drag on the satellite crossbox. To select a new area in the design display area, click and drag on the satellite crossbox. To resize an area in the satellite window, click with the Shift key and drag a corner of the crossbox. To dene a chip area in the satellite window, right-click and drag on an area. There are a number of binding keys available (hit the key when the Encounter GUI is active): b display the list of binding keys d (de)select or delete objects f zoom the display to t the core area k create a ruler K remove last ruler displayed q display the object attribute editor form for the selected object; click the left-button mouse to select an object, Shift-click to select or deselect an object u undo last command U redo last command z zoom-in 2x Z zoom-out 2x Arrows pan the display. Hit CTRL-R to refresh the display.
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4.2
Generate uniquied netlist
Within your synthesized netlist, there are several adder modules. You might realize that these modules should have unique names and currently they do not (i.e., as is, the multiple instances of the adder module are all called the same name, meaning that the current netlist is wrong). You will x this using an Encounter Stop command to make the instances unique: uniquifyNetlist A accu accu.vh netlist This command takes the netlist called AIJnetlistAI, where the accu module is the top module, and makes a unique netlist saved to the le accu.vh. You should view the accu.vh le to verify that the adder modules are now instantiated with unique names.
4.3
Design import
Importing the design into Encounter involves specifying the following setup information: Design libraries and les. This includes information on the technological process and the cell library in the LEF (Layout Exchange Format) format. LEF les provides information such as metal and via layers and via generate rules which is used for routing tasks. They also provide the minimum information on cell layouts for placement and routing. Gate-level netlist. This relates to the (Verilog) netlist to be placed and routed. Timing libraries. This includes information on the cell timings (delays, setup/hold times, etc.). To start the design import, select File Import Design... in the main menu. Then, click on the Load... button and load the le PAR/CONF/L90_SP_std.conf This le denes a basic import conguration. There is a number of additions and changes to bring to the initial conguration. The new conguration will then be saved for future uses. The rst information to add is the netlist. Click on the ... button on the right of the Verilog Files eld. You get a new dialog window with only one pane. Click on the top-right icon to get the full window. Remove the VERILOG/none line in the left pane. Select the Verilog netlist le HDL/GATE/lter_soc_unique.v (or the Verilog netlist you want to place and route), add it to the left pane and close the window. It is assumed here that the imported netlist is the one generated for the 8 ns clock period. In the Design Import window, select the Auto Assign box to let the tool extract the top cell name from the le. If the Verilog le includes more than one design (more than one top module name), you need to give the name of the top module to use explicitly. In the Timing Constraint File Field: Select the le that has been generated during logic synthesis (3.6 Design mapping and optimization): SYN/SDC/lter_soc_mapped.sdc Only timing information in the constraint le is actually used by Encounter. In the IO Assignment File Field: Select the PAR/CONF/lter_soc.io le In the Advanced tab select in the left pane the Power tag, you can keep only the VCC and GND power nets. The names of power and ground nets must be the same as the ones used in the LEF le that describes
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the standard cells. You can now save the updated conguration in the le PAR/CONF/lter_soc.conf by clicking on the Save... button. Finally, click on OK. The conguration is then read in. To reload a conguration, select File Import Design... in the main menu. Then, click on the Load... button and load the conguration le from the PAR/CONF directory.
4.4
Floorplan Specication
The oorplan denes the actual form, or aspect ratio, the layout will take, the global and detailed routing grids, the rows to host the core cells and the I/O pad cells (if required), and the location of the corner cells (if required).
Select Floorplan Specify Floorplan... in the main menu. In order to be able to add PAD cells and IO cells we need to specify Die Size and the Core to IO Boundary parameters. Click the button at Die Size by: and ll in 1872.02 m for both Width and Height. At "Core Margins by:" click the button Core to IO Boundary and ll in the distance between the I/O boundary and the core, here 560im at Core to Left, Top, Right, Bottom. Click OK. If you want to change the coordinates you will need the metrics of the core , IO and pad cells. These metrics are described in Appendix C. Select Floorplan Automatic Floorplan Plan Design... in the main menu to execute the oorplanning. The memory macros are placed into the core area. You can move the memory cells if the initial placement does not suit you. Additionally, the command Floorplan Clear Floorplan... allows you to delete all or parts of the oorplan objects. With Floorplan Automatic Floorplan Finish Floorplan... halos around the macro cell can be specied to prevent placement of standardcells to close to the macro cells. Specify here a halo width of 28 um and leave everything else default. Now the gaps between the IO cells must be lled with IO-ller cells. Execute the llperi.tcl script by the following command on the command line: velocity> source PAR/BIN/llperi.tcl The display design area pane now shows the dened oorplan with the required number of rows.
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It is a good idea to save the design at that stage to allow restarting here quickly without needing to redo all the previous steps. Select File Save Design... in the main menu and save the current state in the le PAR/DB/lter_soc-fplan.enc. The data are actually saved in the directory PAR/DB/lter_soc-fplan.enc.dat. To restore design data, select File Restore Design... in the main menu and select the .enc le to read in the PAR/DB directory.
4.5
Global net connections
This step assigns pins or nets to global power and ground nets. The imported Verilog netlist does not mention any power and ground connections. However, the cells that will be placed do have power/ground pins that will need to be routed to the global power/ground nets dened for the block. Select Floorplan Connect Global Nets... in the main menu.
CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING The left pane (Connection List) is initially empty. For each VCC and ground net: Check the Pins eld and enter the pin name (VCC or GND). Fill the To Global Net eld with either VCC or GND. Click on Add to List. The left pane now includes the related global net connection. Repeat these actions with Tie High checked and nally with Tie Low checked. Click on Apply and then on Close.
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4.6
Power ring/stripe creation and routing
This step generates the VCC and GND power rings around the core and optionally adds a number of vertical and/or horizontal power stripes across the core. Stripes ensure a proper power distribution in large cores. They are not strictly required here as the design is small. Select Power Power Planning Add Rings... in the main menu.
The Net(s) eld denes the number and the kinds of rings from the core. In our case, there will be rst a ground ring around the core and a VCC ring around the ground ring. The net names should be consistent with the power net names in the cell LEF le. In the Ring Type eld check Core ring(s) contouring. The Ring Conguration eld should dene ring widths of 2.8 micron spaced by 1.12 micron. The rings will be placed either in the center of the channel between the core and the chip boundary (or the IO pads, if any) or at a particular offset from the core . Check the Specify in the Ring Conguration eld and specify an offset to the core of 28 m. It is possible to extend the ring segments to reach the core boundary. Click on the Advanced tab and click on the segments youd like to extend. Other power and ground side trunks can be dened by selecting only horizontal or vertical segments. Click OK to generate the rings.
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To add block rings around the memory blocks, select Power Power Planning Add Rings... in the main menu.
In the Ring Type eld check Block ring(s) around. The Ring Conguration eld should dene ring widths of 1.12 micron spaced by 0.56 micron. Check the Specify in the Ring Conguration eld and specify an offset to the block of 5.6 m. Click OK to generate the block rings. It is possible to measure sizes by using the ruler (or hit the k binding key). Hit K to remove the last ruler or press ESC to remove all rulers. To remove ring segments select them and hit the Delete key. To add power stripes, select Power Power Planning Add Stripes... in the main menu. The Set Conguration area denes the Net(s) pattern, direction, layer, width and spacing of the stripes. Our example does not need any stripes so click Cancel
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Now, it is possible to route the power grid. Select Route SRoute... in the main menu. All default values are ne. Click OK to do the routing. The design now looks like below:
It is recommended to save the new stage of the design. Select File Save Design... in the main menu and save the current state in the le PAR/DB/lter_soc-pplan.enc.
4.7
Operating conditions denition
The operating conditions dene the temperature, process and voltage conditions for the design. They impact the timing calculations and optimizations. Select the Options Set Mode Specify Operating Condition/PVT... in the main menu.
In the max tab, select the WCCOM operating condition for Timing Library: fsd0a_a_generic_core_ss0p9v125c. In the min tab, select the BCCOM operating condition for Timing Library: fsd0a_a_generic_core_ff1p1vm40c. Click OK. The max operating conditions will be used to meet setup timing constraints, while the min operating conditions will be used to meet hold timing constraints. The Encounter console summarizes the settings:

Set Min operating condition to fsd0a_a_generic_core_ff1p1vm40c/%NOM_PVT defined in Timing Library fsd0a_a_generic_core_ff1p1vm40c Process: 1.00 Temperature: -40.000 Voltage: 1.100 Set Max operating condition to fsd0a_a_generic_core_ss0p9v125c/%NOM_PVT defined in Timing Library fsd0a_a_generic_core_ss0p9v125c Process: 1.00 Temperature: 125.000 Voltage: 0.900 *** Calculating scaling factor for min libraries using operating condition: Name: fsd0a_a_generic_core_ff1p1vm40c/%NOM_PVT Process: 1.00 Temperature: -40.000 Voltage: 1.100 *** Calculating scaling factor for max libraries using operating condition: Name: fsd0a_a_generic_core_ss0p9v125c/%NOM_PVT Process: 1.00 Temperature: 125.000 Voltage: 0.900
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Running the following command in the Encounter console gives the active operating conditions:
velocity 1> getOpCond -v min: fsd0a_a_generic_core_ff1p1vm40c/%NOM_PVT proc: 1.0000 volt: 1.1000 temp: -40.0000 max: fsd0a_a_generic_core_ss0p9v125c/%NOM_PVT proc: 1.0000 volt: 0.9000 temp: 125.0000
4.8
Core cell placement
This step places the cells of the imported Verilog netlist in the rows. Select Place Standard Cells... in the main menu. By clicking the Mode button one can specify placement options. By default it will run in Timing Driven Placement Mode. Stick to the default options and click OK.
The Timing Driven Placement Mode option will optimize the placement of the cells that are on the critical path. Some cell instances may be replaced with cells having lower driving capabilities (downsizing) or stronger driving capabilities (upsizing). Buffers may be also added or deleted. The Velocity console noties such changes. Click OK to do the placement. It may take some time to complete, especially when the placement is timing driven and a high effort level is used . The placement should then look like below:
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It is recommended to save the new stage of the design. Select File Save Design... in the main menu and save the current state in the le PAR/DB/lter_soc-placed.enc.
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4.9
Post-placement timing analysis
The timing analysis engine in Encounter can now be run to get a relatively good idea of the timing performances of the design. It actually performs a trial routing and a parasitic extraction based on the current cell placement. Select Timing Report Timing... in the main menu. Dene the path for the slack report le. Click OK.
In the Encounter console window you get a summary of the timing analysis:
# ############################################################## # Generated by: Cadence E n c o u n t e r 09 .12 s159_1 # OS: L i n u x i 6 8 6 ( H o s t ID s a l s a ) # Generated on: Wed May 30 11 : 1 4 : 1 8 2012 # Command: t i m e D e s i g n preCTS i d e a l C l o c k p a t h R e p o r t s d r v R e p o r t . . . # ############################################################## t i m e D e s i g n Summary ++++++++ | S e t u p mode | all | reg2reg | in2reg | reg2out | in2out | clkgate | ++++++++ | WNS ( n s ) : | 2 . 0 8 2 | 3 .385 | 5 .841 | 2 .082 | N/A | N/A | | TNS ( n s ) : | 0 . 0 0 0 | 0 .000 | 0 .000 | 0 .000 | N/A | N/A | | Violating Paths: | 0 | 0 | 0 | 0 | N/A | N/A | | All Paths: | 200 | 102 | 98 | 18 | N/A | N/A | ++++++++ ++++ | | Real | Total | | DRVs +++ | | | Nr n e t s ( t e r m s ) | Worst Vio | Nr n e t s ( t e r m s ) | +++++ | max_cap | 2 (2) | 0.081 | 2 (2) | | max_tran | 4 (134) | 0.567 | 4 (134) | | max_fanout | 0 (0) | 0 | 0 (0) | +++++ D e n s i t y : 10 . 6 9 8% R o u t i n g O v e r f l o w : 0 . 0 0% H and 0 . 0 0% V
CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING The design is not critical as the slack is positive (2.082 ns). To get more details on the critical path execute the following commands in the Encounter console: velocity 16> report_timing The following report is then displayed in the console:
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# ############################################################## # Generated by: Cadence E n c o u n t e r 09 .12 s159_1 # OS: L i n u x i 6 8 6 ( H o s t ID s a l s a ) # Generated on: Wed May 30 11 : 2 4 : 5 9 2012 # Command: report_timing # ############################################################## P a t h 1 : MET L a t e E x t e r n a l D e l a y A s s e r t i o n Endpoint: DataInAckxSO ( ^ ) checked with l e a d i n g e d g e o f ClkxCI B e g i n p o i n t : i _ f i l t e r _ t o p / i _ f i l t e r / S t a t e x D P _ r e g _ 0 _ /QB ( v ) t r i g g e r e d by l e a d i n g e d g e o f ClkxCI O t h e r End A r r i v a l Time 0 .000 E x t e r n a l Delay 0 .800 + Phase S h i f t 8 .000 = R e q u i r e d Time 7 .200 A r r i v a l Time 5 .118 = S l a c k Time 2 .082 C l o c k R i s e Edge 0 .000 + C l o c k Network L a t e n c y ( I d e a l ) 0 . 0 0 0 = B e g i n p o i n t A r r i v a l Time 0 .000 + + | Instance | Arc | Cell | Delay | A r r i v a l | Required | | | | | | Time | Time | |+++++ | | i _ f i l t e r _ t o p / i _ f i l t e r / S t a t e x D P _ r e g _ 0 _ | CK ^ | | | 0 .000 | 2 .082 | | i _ f i l t e r _ t o p / i _ f i l t e r / S t a t e x D P _ r e g _ 0 _ | CK ^ > QB v | DFFRBX1 | 0 . 3 3 1 | 0 .331 | 2 .413 | | i _ f i l t e r _ t o p / i _ f i l t e r / U178 | I 2 v > O ^ | NR2X1 | 1 .383 | 1 .713 | 3 .795 | | io_DataInAckxSO_x0_op | I ^ > O ^ | VYA4GSGB | 3 . 4 0 5 | 5 .118 | 7 .200 | | | DataInAckxSO ^ | | 0 .000 | 5 .118 | 7 .200 | + +
If timing requirements are not met optimization is possible by selecting Optimize Optimize Design... in the main menu and check pre-CTS and click OK.
4.10
Clock tree synthesis (optional)
As the paths that will propagate the clock signal in the design are not necessarily balanced, some registers may receive the active clock edge later than others (clock skew) and may therefore violate the assumed synchronous design operation. For example, the original clock tree we can get from the previously placed design is shown below. To create a balanced clock tree, you have rst to create a clock tree specication le. Encounter can create a rst draft version of the le you can then edit to include design specic data. Here we will use a ready made specication le PAR/CTS/lter_soc-spec.ctstch Select Clock Synthesize Clock Tree... in the main menu. In the popup menu change the Results Directory to PAR/CTS/clock_report at Clock Specication Files: on the ... button to add the clock specication le PAR/CTS/lter_soc-spec.ctstch . Click OK to create the clock tree. To display the generated clock tree, select
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Clock Display Display Clock Tree ... in the main menu.
The clock paths have been balanced according to the clock tree specications. To get a report on the clock tree synthesis, enter the following command at the velocity prompt.
velocity 1> reportClockTree -report PAR/RPT/filter_soc.ctsrpt
The following report is also displayed in the Encounter console:

v e l o c i t y 10> r e p o r t C l o c k T r e e Redoing s p e c i f y C l o c k T r e e . . .

Checking spec f i l e integrity...
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reportClockTree Option : Look F o r R e c o n v e r g e n t C l o c k Component The c l o c k t r e e i o _ C l k x C I _ x 0 _ i p /O h a s no r e c o n v e r g e n t c e l l . # # Mode : Setup # L i b r a r y Name : fsd0a_a_generic_core_ss0p9v125c C l o c k i o _ C l k x C I _ x 0 _ i p /O Pre Route Timing A n a l y s i s Nr. of Subtrees : 1 Nr. of Sinks : 66 Nr. of Buffer : 1 Nr. of Level ( i n c l u d i n g g a t e s ) : 1 Root R i s e I n p u t T r a n : 0 . 1 ( ps ) Root F a l l I n p u t T r a n : 0 . 1 ( ps ) Max t r i g . e d g e d e l a y a t s i n k (R) : i _ f i l t e r _ t o p / i _ f i l t e r / AccuxDP_reg_15_ /CK 385 . 4 ( ps ) Min t r i g . e d g e d e l a y a t s i n k (R) : i _ f i l t e r _ t o p / i _ f i l t e r / OutRegxDP_reg_1_ /CK 364 . 5 ( ps )
Rise Phase Delay F a l l Phase Delay T r i g . Edge Skew R i s e Skew F a l l Skew Max. R i s e B u f f e r T r a n . Max. F a l l B u f f e r T r a n . Max. R i s e S i n k T r a n . Max. F a l l S i n k T r a n . Min. R i s e B u f f e r T r a n . Min. F a l l B u f f e r T r a n . Min. R i s e S i n k T r a n . Min. F a l l S i n k T r a n .
: : : : : : : : : : : : :
( Actual ) 364 . 5 ~385 . 4 ( p s ) 302 . 1 ~ 3 2 3 ( p s ) 20 . 9 ( p s ) 20 . 9 ( p s ) 20 . 9 ( p s ) 182 . 5 ( p s ) 156 . 6 ( p s ) 170 . 2 ( p s ) 76 . 4 ( p s ) 182 . 5 ( p s ) 156 . 6 ( p s ) 170 . 2 ( p s ) 76 . 2 ( p s )
( Required ) 0~8000( ps ) 0~8000( ps ) 300( ps )
400( ps ) 400( ps ) 400( ps ) 400( ps ) 0( ps ) 0( ps ) 0( ps ) 0( ps )
G e n e r a t i n g Clock A n a l y s i s Report f i l t e r _ s o c . c t s r p t C l o c k A n a l y s i s (CPU Time 0 : 0 0 : 0 0 . 0 )
....
End r e p o r t C l o c k T r e e ( c p u = 0 : 0 0 : 0 0 . 0 , r e a l = 0 : 0 0 : 0 0 . 0 , mem=476.0M )
Several clock report les are also available in the PAR/CTS/clock_report directory. It is recommended to save the new stage of the design. Select File Save Design... in the main menu and save the current state in the le PAR/DB/lter_soc-cts.enc.
4.11
Filler cell placement
Filler cells will ll remaining holes in the rows and ensure the continuity of power/ground rails and N+/P+ wells in the rows. To ll the holes with ller cells, select Place Physical Cell Add Filler... in the
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main menu. Select the cells FILLER64E, FILLER32E, FILLER16E, FILLER8E, FILLER4E, FILLER3, FILLER2 and FILLER1 and click OK to place the ller cells. Another way to add the ller cells is by executing the tcl script "llcore.tcl":
velocity 1> source PAR/BIN/fillcore.tcl
4.12
Design routing
This step generates all the wires required to connect the cells according to the imported gate-level netlist. To route the design, select Route Nanoroute... in the main menu, check the Timing Driven box and a maximum effort. Click OK to do the routing. You now get the routed design:
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It is recommended to save the new stage of the design. Select File Save Design... in the main menu and save the current state in the le PAR/DB/lter_soc-routed.enc.
4.13
Post-routing timing optimization and analysis
A nal timing optimization may be done on the routed design. Select Optimize Optimize Design... in the main menu. Select the postRoute box. Click OK. The results of the optimization is displayed in the Encounter console:
4.14
Design checks
The Verify menu has a number of items to check that the design has been properly placed and routed. Select Verify Verify Connectivity... in the main menu. Dene the report le as PAR/RPT/lter_socconn.rpt. Click OK. The console displays the results:
S t a r t : VERIFY CONNECTIVITY
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S t a r t T i m e : Wed May 30 12 : 4 9 : 4 5 2012 D e s i g n Name: f i l t e r _ s o c D a t a b a s e U n i t s : 1000 D e s i g n B o u n d a r y : ( 0 . 0 0 0 0 , 0 . 0 0 0 0 ) ( 1 8 7 2 . 0 8 0 0 , 1872 . 0 8 0 0 ) E r r o r L i m i t = 1 0 0 0 ; Warning L i m i t = 50 Check a l l n e t s VC E l a p s e d T i m e : 0 : 0 0 : 0 0 . 0 B e g i n Summary Found no p r o b l e m s o r w a r n i n g s . End Summary End T i m e : Wed May 30 12 : 4 9 : 4 5 2012 E n d : VERIFY CONNECTIVITY V e r i f i c a t i o n C o m p l e t e : 0 V i o l s . 0 Wrngs. (CPU T i m e : 0 : 0 0 : 0 0 . 1 MEM: 0 .008M )
Select Verify Verify Geometry... in the main menu. In the Advanced tab, dene the report le as PAR/RPT/lter_soc-geom.rpt. Click OK.
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The console displays the results:

VERIFY GEOMETRY VERIFY GEOMETRY VERIFY GEOMETRY VERIFY GEOMETRY VERIFY GEOMETRY VERIFY GEOMETRY VERIFY GEOMETRY VG: e l a p s e d t i m e : B e g i n Summary . . . Cells : 0 SameNet : 0 Wiring : 0 Antenna : 0 Short : 0 Overlap : 0 End Summary ...... ...... ...... ...... ...... ...... ...... 5 .00 Sub Area : 15 c o m p l e t e 0 V i o l s . 0 Wrngs. SubArea : 16 o f 16 Cells : 0 Viols. SameNet : 0 Viols. Wiring : 0 Viols. Antenna : 0 Viols. Sub Area : 16 c o m p l e t e 0 V i o l s . 0 Wrngs.
V e r i f i c a t i o n Complete : 0 V i o l s .
0 Wrngs.
E n d: VERIFY GEOMETRY v e r i f y g e o m e t r y ( CPU: 0 : 0 0 : 0 4 . 4 MEM: 3.8M )
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4.15
Report generation
A number of reports have been already generated in the previous steps. They should be located in the PAR/RPT directory. The Tools menu includes some additional reports: File Report Netlist Statistics gives the following output in the console:
v e l o c i t y 15> S t a t i s t i c s f o r n e t l i s t Number o f c e l l s = 2949 Number o f n e t s = 689 Number o f t r i n e t s = 18 Number o f d e g e n n e t s = 0 Number o f p i n s = 2411 Number o f i / o s = 38 Number Number Number Number Number Number Number Number Number of of of of of of of of of nets nets nets nets nets nets nets nets nets with 2 with 3 with 4 with 5 with 6 with 7 with 8 with 9 w i t h >=10 terms terms terms terms terms terms terms terms terms = = = = = = = = = f i l t e r _ s o c
419 ( 6 0 . 8 %) 147 ( 2 1 . 3 %) 38 ( 5 . 5 %) 18 ( 2 . 6 %) 12 ( 1 . 7 %) 8 ( 1 . 2 %) 4 ( 0 . 6 %) 6 ( 0 . 9 %) 37 ( 5 . 4 %)
69 P r i m i t i v e s u s e d : P r i m i t i v e PAD9M126G ( 5 6 i n s t s ) P r i m i t i v e VCCKGB ( 1 i n s t s ) P r i m i t i v e GNDKGB ( 1 i n s t s ) P r i m i t i v e VCC2IOGB ( 8 i n s t s ) P r i m i t i v e GND2IOGB ( 8 i n s t s ) P r i m i t i v e SPAA90_512X16BM1A ( 1 i n s t s ) P r i m i t i v e UYNGB ( 2 0 i n s t s ) P r i m i t i v e VYA4GSGB ( 1 8 i n s t s ) P r i m i t i v e SYAA90_128X16X1CM2 ( 1 i n s t s ) P r i m i t i v e EMPTY8GB ( 3 2 i n s t s ) P r i m i t i v e EMPTY4GB ( 3 2 i n s t s ) P r i m i t i v e EMPTY2GB ( 3 4 i n s t s ) P r i m i t i v e EMPTY1GB ( 4 4 i n s t s ) P r i m i t i v e EMPTY16GB ( 4 9 2 i n s t s ) P r i m i t i v e CORNERGB ( 4 i n s t s ) P r i m i t i v e XOR3X1 ( 4 i n s t s ) P r i m i t i v e XOR2X1 ( 8 i n s t s ) P r i m i t i v e XOR2CKX1 ( 1 i n s t s ) P r i m i t i v e TIE1X1 ( 2 i n s t s ) P r i m i t i v e TIE0X1 ( 2 i n s t s ) P r i m i t i v e QDFERBX1 ( 2 2 i n s t s ) P r i m i t i v e OR2X1 ( 1 i n s t s ) P r i m i t i v e OAI22XLP ( 1 i n s t s ) P r i m i t i v e OAI12XLP ( 2 i n s t s ) P r i m i t i v e OAI12X1 ( 1 5 i n s t s ) P r i m i t i v e OAI122X1 ( 7 i n s t s ) P r i m i t i v e OAI112XLP ( 3 i n s t s ) P r i m i t i v e OAI112X1 ( 1 i n s t s ) P r i m i t i v e OA12XLP ( 2 i n s t s )
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File Report Gate Count... gives the following output in the console:
v e l o c i t y 15> G a t e a r e a 2 . 3 5 2 0 um^2 [ 0 ] f i l t e r _ s o c G a t e s = 1 6 3 3 2 C e l l s = 5 0 4 A r e a = 3 8 4 1 4 . 3 um^2 [ 1 ] i _ f i l t e r _ t o p G a t e s = 1 6 3 1 4 C e l l s = 4 9 7 A r e a = 3 8 3 7 1 . 1 um^2 [ 2 ] i _ f i l t e r _ t o p / i _ f i l t e r G a t e s = 1 8 5 5 C e l l s = 4 9 3 A r e a = 4 3 6 3 . 7 um^2 [ 2 ] i _ f i l t e r _ t o p / i _ c o e f f _ a 9 d 1 6 G a t e s = 6 9 9 5 C e l l s = 0 A r e a = 1 6 4 5 3 . 7 um^2 [ 2 ] i _ f i l t e r _ t o p / i_dataRAM_i_dmem G a t e s = 7 4 6 1 C e l l s = 0 A r e a = 1 7 5 4 9 . 0 um^2
Finally, File Report Summary... displays the following window:

S t a t i s t i c s f o r n e t Number o f c e l l s = Number o f n e t s = Number o f t r i n e t s = Number o f d e g e n n e t s = Number o f p i n s = Number o f i / o s = Number Number Number Number Number of of of of of nets nets nets nets nets with with with with with l i s t f i l t e r _ s o c 2949 689 18 0 2411 38 2 3 4 5 6 terms terms terms terms terms = = = = = 419 ( 6 0 . 8 %) 147 ( 2 1 . 3 %) 38 ( 5 . 5 %) 18 ( 2 . 6 %) 12 ( 1 . 7 %)

Number Number Number Number of of of of nets nets nets nets with 7 with 8 with 9 w i t h >=10 terms terms terms terms = = = = 8 ( 1 . 2 %) 4 ( 0 . 6 %) 6 ( 0 . 9 %) 37 ( 5 . 4 %)
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69 P r i m i t i v e s u s e d : P r i m i t i v e PAD9M126G ( 5 6 i n s t s ) P r i m i t i v e VCCKGB ( 1 i n s t s ) P r i m i t i v e GNDKGB ( 1 i n s t s ) P r i m i t i v e VCC2IOGB ( 8 i n s t s ) P r i m i t i v e GND2IOGB ( 8 i n s t s ) P r i m i t i v e SPAA90_512X16BM1A ( 1 i n s t s ) P r i m i t i v e UYNGB ( 2 0 i n s t s ) P r i m i t i v e VYA4GSGB ( 1 8 i n s t s ) P r i m i t i v e SYAA90_128X16X1CM2 ( 1 i n s t s ) P r i m i t i v e EMPTY8GB ( 3 2 i n s t s ) P r i m i t i v e EMPTY4GB ( 3 2 i n s t s ) P r i m i t i v e EMPTY2GB ( 3 4 i n s t s ) P r i m i t i v e EMPTY1GB ( 4 4 i n s t s ) P r i m i t i v e EMPTY16GB ( 4 9 2 i n s t s ) P r i m i t i v e CORNERGB ( 4 i n s t s ) P r i m i t i v e XOR3X1 ( 4 i n s t s ) P r i m i t i v e XOR2X1 ( 8 i n s t s ) P r i m i t i v e XOR2CKX1 ( 1 i n s t s )
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4.16
Post-route timing data extraction
This step generates the post-route SDF le that includes both the actual interconnect and cell timing delays.
The parasitics must be rst extracted. Therefore set the extraction mode: Select Options Set Mode Specify RC Extraction Mode... in the main menu.
Check PostRoute, EffortLevel: Low, Extraction Type: Coupled RC And extract the netlist: Select Timing Extract RC... in the main menu. The generated Cap le includes the wired capacitance, pin capacitance, total capacitance, net length, wire cap per unit length and the fanout of each net in the design. The generated SPEF (Standard Parasitics Exchange Format) le includes RC values in a SPICE-like format. The SDF le may be then generated by selecting Timing Write SDF... in the main menu. The checked Ideal Clock switch means that ip-ops are considered as having 0ps rising and falling transition times.
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4.17
Post-route netlist generation
This steps generates a Verilog netlist of the routed design. The netlist may be different from the imported netlist as cells may have been added or replaced during clock tree synthesis and timing-driven optimizations.
Select File Save Netlist... in the main menu. Do not select Include Leaf Cell Denition as they are provided in a separate library. The generated le should go into the HDL/GATE directory.
4.18
GDS2 le generation
The placed and routed design can be exported in different formats for further processing outside the En-
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counter tool. The GDS2 binary format is a standard format for integrating the block in the top-level layout, doing DRC/LVS checkings, or delivering the layout to the foundry. To export the design in the GDS2 format, select File Save GDS/OASIS... in the main menu. The GDS map le has been copied by the tech_setup script into the PAR/DEX directory. The generated GDS2 le is written in the same directory. -
4.19
Using scripts
As for the synthesis step, it is much more convenient to capture the placement and routing ow in a script. Cadence Encounter also support sthe Tcl language for building scripts. An example of such a script for placement and routing of the Fir-Filter design has been installed in the PAR/BIN directory (see ?? VHDL example: FIR-Filter). The script must be run from the project top directory and it assumes a directory organization as described in 1.2 Design project organisation. To run the Tcl script, execute the following command in a Unix shell:
velocity -log PAR/LOG/encounter -overwrite -init PAR/BIN/top-level.tcl -win
The script top-level.tcl given below calls TCL subscripts, one for each design step. During an interactive session of Encounter you can source the scriptsi the proper sequence at the velocity command prompt. This allows for checking the result after each Place&Route step. By modifying parameters in a particular design step script you can dene design information and to control the ow to some extent. Note that a conguration le must exist before running the script. The conguration le name is in the PAR/CONF directory and its name is dened in the script. The script does a bit more than the steps described earlier. For example, it uses an I/O pin placement denition as provided by a PAR/CONF/lter_soc.io le.
s e t PROJECT_DIR [ pwd ] s e t PAR_BIN $ {PROJECT_DIR } / PAR / BIN # Import the design s o u r c e $ {PAR_BIN } / s t a r t . t c l # Create a f l o o r p l a n s o u r c e $ {PAR_BIN } / f p l a n . t c l # C r e a t e power / g r o u n d d i s t r i b u t i o n l i n e s s o u r c e $ {PAR_BIN } / p p l a n . t c l # Place standard c e l l s i n t o the core s o u r c e $ {PAR_BIN } / p l a c e . t c l # Create th e Clock Tree s o u r c e $ {PAR_BIN } / c t s . t c l # P l a c e F i l l e r C e l l s and r o u t e t h e d e s i g n s o u r c e $ {PAR_BIN } / r o u t e . t c l # V e r i f y C o n n e c t i v i t y and Geometry s o u r c e $ {PAR_BIN } / v e r i f y . t c l # Extract the c i r c u i t s o u r c e $ {PAR_BIN } / r e s u l t s . t c l
Appendix A
Appendix A: VHDL Netlists

A.1 File: lter.vhd
Listing A.1: RTL synthesisable model of the FIR-Filter.
library ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; use i e e e . n u m e r i c _ s t d . a l l ; entity f i l t e r is generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 3 2 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ; LutAddrxDO : o u t s t d _ l o g i c _ v e c t o r (CAW 1 downto 0 ) ; LutReadxDI : i n s t d _ l o g i c _ v e c t o r (CWIDTH1 downto 0 ) ; RamWriteEnxSO : o u t s t d _ l o g i c ; RamAddrxDO : o u t s t d _ l o g i c _ v e c t o r (DAW 1 downto 0 ) ; RamReadxDI : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; RamWritexDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ); end f i l t e r ; architecture r t l of f i l t e r i s 56
APPENDIX A. APPENDIX A: VHDL NETLISTS c o m p o n e n t d e c l a r a t i o n s S t a t e t y p e s t a t e _ t y p e i s ( i d l e , new_data , run , d a t a _ o u t ) ; s i g n a l S t a t e x D P , StatexDN : s t a t e _ t y p e ; R e g i s t e r s s i g n a l RamWriteEnxS : s t d _ l o g i c ; s i g n a l InRegEnxS : s t d _ l o g i c ; s i g n a l InRegxDN : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; C o u n t e r s s i g n a l OffsetDecxS : s t d _ l o g i c ; s i g n a l O f f s e t x D P , OffsetxDN : u n s i g n e d (DAW 1 downto 0 ) ; signal CounterIncxS : s t d _ l o g i c ; s i g n a l CounterxDP , CounterxDN : u n s i g n e d (CAW 1 downto 0 ) ; C o u n t e r s s i g n a l RamAddrxD : s t d _ l o g i c _ v e c t o r (DAW 1 downto 0 ) ; s i g n a l LutAddrxD : s t d _ l o g i c _ v e c t o r (CAW 1 downto 0 ) ; ALU signal signal signal signal signal signal signal signals SumxD : s i g n e d ( ( DWIDTH+CWIDTH) 1 downto 0 ) ; SumStdxD : s t d _ l o g i c _ v e c t o r ( ( DWIDTH+CWIDTH) 1 downto 0 ) ; RamReadxD : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; RamSignedxD : s i g n e d (DWIDTH1 downto 0 ) ; LutReadxD : s t d _ l o g i c _ v e c t o r (CWIDTH1 downto 0 ) ; L u t S i g n e d x D : s i g n e d (CWIDTH1 downto 0 ) ; MultxD : s i g n e d ( ( DWIDTH+CWIDTH) 1 downto 0 ) ;
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R e g i s t e r s s i g n a l AccuClrxS : s t d _ l o g i c ; s i g n a l AccuxDP , AccuxDN : s i g n e d ( ( DWIDTH+CWIDTH) 1 downto 0 ) ; R e g i s t e r s s i g n a l OutRegEnxS : s t d _ l o g i c ; s i g n a l OutRegxDP , OutRegxDN : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; begin RamWriteEnxSO <= RamWriteEnxS ; I n p u t r e g i s t e r InRegxDN <= D a t a I n x D I ; p _ i n r e g : p r o c e s s ( ClkxCI , R e s e t x R B I ) begin i f R e s e t x R B I = 0 t h e n RamWritexDO <= ( o t h e r s => 0 ) ; e l s i f ClkxCI e v e n t and ClkxCI = 1 t h e n i f InRegEnxS = 1 t h e n
APPENDIX A. APPENDIX A: VHDL NETLISTS RamWritexDO<= InRegxDN ; end i f ; end i f ; end p r o c e s s p _ i n r e g ; C o u n t e r s p _ d a t a : process ( OffsetxDP , OffsetDecxS ) begin OffsetxDN <= O f f s e t x D P ; i f OffsetDecxS = 1 then OffsetxDN <= O f f s e t x D P " 0000001 " ; end i f ; end p r o c e s s p _ d a t a ; p _ c o e f : p r o c e s s ( CounterxDP , C o u n t e r I n c x S ) begin CounterxDN <= CounterxDP ; i f CounterIncxS = 1 then CounterxDN <= CounterxDP + " 0000001 " ; end i f ; end p r o c e s s p _ c o e f ; C o u n t e r s two s i m i l a r r e g i s t e r s c o m b i n e d i n one p r o c e s s p _ a d r c l k : p r o c e s s ( ClkxCI , R e s e t x R B I ) begin i f R e s e t x R B I = 0 t h e n CounterxDP <= ( o t h e r s => 0 ) ; O f f s e t x D P <= ( o t h e r s => 0 ) ; e l s i f ClkxCI e v e n t and ClkxCI = 1 t h e n CounterxDP <= CounterxDN ; O f f s e t x D P <= OffsetxDN ; end i f ; end p r o c e s s p _ a d r c l k ; add and c o n v e r t t h e a d d r e s s RamAddrxDO <= s t d _ l o g i c _ v e c t o r ( O f f s e t x D P + CounterxDP ) ; LutAddrxDO <= s t d _ l o g i c _ v e c t o r ( CounterxDP ) ; ALU t y p e c o n v e r s i o n RamSignedxD <= s i g n e d ( RamReadxDI ) ; L u t S i g n e d x D <= s i g n e d ( LutReadxDI ) ; s i g n e d o p e r a t i o n s
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APPENDIX A. APPENDIX A: VHDL NETLISTS MultxD <= RamSignedxD L u t S i g n e d x D ; SumxD <= MultxD + AccuxDP ; t y p e c o n v e r s i o n SumStdxD <= s t d _ l o g i c _ v e c t o r ( SumxD ) ; s i m p l e t r u n c a t e OutRegxDN<= SumStdxD ( ( DWIDTH+CWIDTH ) 1 downto CWIDTH ) ; OutRegxDN<= SumStdxD (DWIDTH1 downto 0 ) ; ALU A c c u m u l a t o r n e x t s t a t e AccuxDN <= SumxD when AccuClrxS = 0 e l s e ( o t h e r s => 0 ) ; p _ a c c u : p r o c e s s ( ClkxCI , R e s e t x R B I ) begin i f R e s e t x R B I = 0 t h e n AccuxDP <= ( o t h e r s => 0 ) ; e l s i f ClkxCI e v e n t and ClkxCI = 1 t h e n AccuxDP <= AccuxDN ; end i f ; end p r o c e s s p _ a c c u ; O u t p u t r e g i s t e r p _ o u t r e g : p r o c e s s ( ClkxCI , R e s e t x R B I ) begin i f ResetxRBI= 0 then OutRegxDP <= ( o t h e r s => 0 ) ; e l s i f ClkxCI e v e n t and ClkxCI = 1 t h e n i f OutRegEnxS = 1 t h e n OutRegxDP <= OutRegxDN ; end i f ; end i f ; end p r o c e s s p _ o u t r e g ; DataOutxDO <= OutRegxDP ; C o n t r o l FSM p_fsm : p r o c e s s ( S t a t e x D P , D a t a I n R e q x S I , DataOutAckxSI , CounterxDP ) begin d e f a u l t s InRegEnxS <= 0 ; OutRegEnxS <= 0 ; AccuClrxS <= 0 ; O f f s e t D e c x S <= 0 ;
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APPENDIX A. APPENDIX A: VHDL NETLISTS C o u n t e r I n c x S <= 0 ; RamWriteEnxSO <= 0 ; DataInAckxSO <= 0 ; DataOutReqxSO <= 0 ; StatexDN <= S t a t e x D P ; c a s e s t a t e m e n t s case StatexDP i s when i d l e => i f DataInReqxSI = 1 then InRegEnxS <= 1 ; StatexDN <= n e w _ d a t a ; end i f ; when n e w _ d a t a => AccuClrxS <= 1 ; RamWriteEnxSO < = 1 ; DataInAckxSO <= 1 ; StatexDN <= r u n ; when r u n => C o u n t e r I n c x S <= 1 ; i f CounterxDP = " 1111111 " t h e n OutRegEnxS <= 1 ; O f f s e t D e c x S <= 1 ; StatexDN <= d a t a _ o u t ; end i f ; when d a t a _ o u t => DataOutReqxSO <= 1 ; i f DataOutAckxSI = 1 t h e n StatexDN <= i d l e ; end i f ; when o t h e r s => n u l l ; end c a s e ; end p r o c e s s p_fsm ; p _ c l k : p r o c e s s ( ClkxCI , R e s e t x R B I ) begin i f R e s e t x R B I = 0 t h e n S t a t e x D P <= i d l e ; e l s i f ClkxCI e v e n t and ClkxCI = 1 t h e n S t a t e x D P <= StatexDN ; end i f ; end p r o c e s s p _ c l k ; end r t l ;
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A.2
File: lter_top.vhd
Listing A.2: RTL top model of the FIR-Filter.
APPENDIX A. APPENDIX A: VHDL NETLISTS library ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; use i e e e . n u m e r i c _ s t d . a l l ; entity filter_top is generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 3 2 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ); end f i l t e r _ t o p ; architecture r t l of f i l t e r _ t o p i s c o m p o n e n t d e c l a r a t i o n s component c o e f f generic ( CWIDTH : i n t e g e r ; CAW : i n t e g e r ) ; port ( ClkxCI : i n s t d _ l o g i c ; AddrxDI : i n s t d _ l o g i c _ v e c t o r (CAW 1 downto 0 ) ; DataxDO : o u t s t d _ l o g i c _ v e c t o r (CWIDTH1 downto 0 ) ) ; end component ; component dataRAM generic ( DWIDTH : i n t e g e r ; DAW : i n t e g e r ) ; port ( AddrxDI : i n s t d _ l o g i c _ v e c t o r (DAW 1 downto 0 ) ; WExSI : i n s t d _ l o g i c ; WClkxCI : i n s t d _ l o g i c ; DinxDI : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DoutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ) ; end component ; component f i l t e r
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APPENDIX A. APPENDIX A: VHDL NETLISTS generic ( DWIDTH : i n t e g e r ; DAW : i n t e g e r ) ; port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ; LutAddrxDO : o u t s t d _ l o g i c _ v e c t o r (CAW 1 downto 0 ) ; LutReadxDI : i n s t d _ l o g i c _ v e c t o r (CWIDTH1 downto 0 ) ; RamWriteEnxSO : o u t s t d _ l o g i c ; RamAddrxDO : o u t s t d _ l o g i c _ v e c t o r (DAW 1 downto 0 ) ; RamReadxDI : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; RamWritexDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ) ; end component ;
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signal signal signal signal signal signal
RamWriteEnxS : s t d _ l o g i c ; RamAddrxD : s t d _ l o g i c _ v e c t o r (DAW 1 downto 0 ) ; RamReadxD : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; RamWritexD : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; LutAddrxD : s t d _ l o g i c _ v e c t o r (CAW 1 downto 0 ) ; LutReadxD : s t d _ l o g i c _ v e c t o r (CWIDTH1 downto 0 ) ;
begin Component I n s t a n t i a t i o n s i_coeff : coeff g e n e r i c map ( CWIDTH => CWIDTH, CAW => CAW) p o r t map ( ClkxCI => ClkxCI , AddrxDI => LutAddrxD , DataxDO => LutReadxD ) ; i_dataRAM : dataRAM g e n e r i c map ( DWIDTH => DWIDTH, DAW => DAW) p o r t map ( AddrxDI => RamAddrxD , WExSI => RamWriteEnxS , WClkxCI => ClkxCI , DinxDI => RamWritexD ,
APPENDIX A. APPENDIX A: VHDL NETLISTS DoutxDO => RamReadxD ) ; i_filter : filter g e n e r i c map ( DWIDTH => DWIDTH, DAW => DAW) p o r t map ( ClkxCI => ClkxCI , R e s e t x R B I => ResetxRBI , D a t a I n x D I => D a t a I n x D I , D a t a I n R e q x S I => D a t a I n R e q x S I , DataInAckxSO => DataInAckxSO , DataOutxDO => DataOutxDO , DataOutReqxSO => DataOutReqxSO , DataOutAckxSI => DataOutAckxSI , LutAddrxDO => LutAddrxD , LutReadxDI => LutReadxD , RamWriteEnxSO => RamWriteEnxS , RamAddrxDO => RamAddrxD , RamReadxDI => RamReadxD , RamWritexDO => RamWritexD ) ; end r t l ;
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A.3
File: lter_soc.vhd
Listing A.3: RTL top model of the FIR-Filter.
library ieee ; use i e e e . s t d _ l o g i c _ 1 1 6 4 . a l l ; u s e i e e e . n u m e r i c _ s t d . a l l ; l i b r a r y techmap ; u s e t e c h m a p . gencomp . a l l ; entity filter_soc is generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 1 6 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ;
APPENDIX A. APPENDIX A: VHDL NETLISTS DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ); end f i l t e r _ s o c ; architecture r t l of f i l t e r _ s o c i s c o m p o n e n t d e c l a r a t i o n s component f i l t e r _ t o p i s generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 1 6 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ); end component ; s i g n a l d e c l a r a t i o n s s i g n a l ClkxCI_s : s t d _ l o g i c ; s i g n a l ResetxRBI_s : s t d _ l o g i c ; s i g n a l D a t a I n x D I _ s : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; s i g n a l DataInReqxSI_s : s t d _ l o g i c ; s i g n a l DataInAckxSO_s : s t d _ l o g i c ; s i g n a l DataOutxDO_s : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; s i g n a l DataOutReqxSO_s : s t d _ l o g i c ; s i g n a l DataOutAckxSI_s : s t d _ l o g i c ; s i g n a l VCCIO : s t d _ u l o g i c _ v e c t o r ( 7 downto 0 ) ; s i g n a l GNDIO : s t d _ u l o g i c _ v e c t o r ( 7 downto 0 ) ; s i g n a l VCCCO : s t d _ u l o g i c ; s i g n a l GNDCO : s t d _ u l o g i c ; constant padtech : i n t e g e r := faraday ; constant p a d l e v e l : i n t e g e r := 0; begin Pad I n s t a n t i a t i o n s
64
APPENDIX A. APPENDIX A: VHDL NETLISTS
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Power Pads io_VCCIO : v c c i o p a d v g e n e r i c map ( w i d t h => 8 , t e c h => p a d t e c h , l i m i t => c o r e _ l i m i t e d ) p o r t map ( VCCIO ) ; io_GNDIO : g n d i o p a d v g e n e r i c map ( w i d t h => 8 , t e c h => p a d t e c h , l i m i t => c o r e _ l i m i t e d ) p o r t map (GNDIO) ; io_VCCCO : v c c c o p a d g e n e r i c map ( t e c h => p a d t e c h , l i m i t => core_limited ) p o r t map (VCCCO) ; io_GNDCO : g n d c o p a d g e n e r i c map ( t e c h => p a d t e c h , l i m i t => core_limited ) p o r t map (GNDCO) ; S i g n a l Pads i o _ C l k x C I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( ClkxCI , C l k x C I _ s ) ; i o _ R e s e t x R B I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( ResetxRBI , R e s e t x R B I _ s ) ; i o _ D a t a I n x D I : i n p a d v g e n e r i c map ( w i d t h => DWIDTH, t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( D a t a I n x D I , D a t a I n x D I _ s ) ; i o _ D a t a I n R e q x S I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( D a t a I n R e q x S I , D a t a I n R e q x S I _ s ) ; io_DataInAckxSO : o u t p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , s l e w => f a s t , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataInAckxSO , DataInAckxSO_s ) ; io_DataOutxDO : o u t p a d v g e n e r i c map ( w i d t h => DWIDTH, t e c h => p a d t e c h , l e v e l => p a d l e v e l , s l e w => f a s t , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataOutxDO , DataOutxDO_s ) ; io_DataOutReqxSO : o u t p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , s l e w => f a s t , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataOutReqxSO , DataOutReqxSO_s ) ; i o _ D a t a O u t A c k x S I : i n p a d g e n e r i c map ( t e c h => p a d t e c h , l e v e l => p a d l e v e l , l i m i t => c o r e _ l i m i t e d ) p o r t map ( DataOutAckxSI , D a t a O u t A c k x S I _ s ) ; Component I n s t a n t i a t i o n s i_filter_top : filter_top g e n e r i c map ( CWIDTH => CWIDTH, CAW => CAW, DWIDTH => DWIDTH, DAW => DAW) p o r t map ( ClkxCI => ClkxCI_s ,
APPENDIX A. APPENDIX A: VHDL NETLISTS R e s e t x R B I => R e s e t x R B I _ s , D a t a I n x D I => D a t a I n x D I _ s , D a t a I n R e q x S I => D a t a I n R e q x S I _ s , DataInAckxSO => DataInAckxSO_s , DataOutxDO => DataOutxDO_s , DataOutReqxSO => DataOutReqxSO_s , DataOutAckxSI => D a t a O u t A c k x S I _ s ); end r t l ;
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A.4
File: lter_soc_tb.vhd
Listing A.4: RTL testbench model of the FIR-Filter.
T i t l e : T e s t Bench f o r F i n i t e I m p u l s e R e s p o n s e ( FIR ) F i l t e r C o p y r i g h t ( c ) 1 9 9 8 , 1 9 9 9 by Mentor G r a p h i c s C o r p o r a t i o n . All rights reserved . T h i s s o u r c e f i l e may be u s e d and d i s t r i b u t e d w i t h o u t r e s t r i c t i o n provided t h a t t h i s c o p y r i g h t s t a t e m e n t i s n o t removed f r o m t h e f i l e and t h a t any d e r i v a t i v e work c o n t a i n s t h i s c o p y r i g h t n o t i c e .
LIBRARY USE i e e e USE i e e e USE i e e e USE i e e e
ieee ; . s t d _ l o g i c _ 1 1 6 4 . ALL ; . s t d _ l o g i c _ a r i t h . ALL ; . s t d _ l o g i c _ s i g n e d . ALL ; . m a t h _ r e a l . ALL ;
ENTITY f i l t e r _ s o c _ t b IS GENERIC ( c l o c k _ d e l a y : t i m e : = 16 n s ; CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 1 6 ; DAW : i n t e g e r : = 7 ); END f i l t e r _ s o c _ t b ;
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ARCHITECTURE b e h a v i o r a l OF f i l t e r _ s o c _ t b IS component f i l t e r _ s o c i s generic ( CWIDTH : i n t e g e r : = 1 6 ; CAW : i n t e g e r : = 7 ; DWIDTH : i n t e g e r : = 3 2 ; DAW : i n t e g e r : = 7 ); port ( ClkxCI : i n s t d _ l o g i c ; ResetxRBI : in s t d _ l o g i c ; D a t a I n x D I : i n s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : in s t d _ l o g i c ; DataInAckxSO : o u t s t d _ l o g i c ; DataOutxDO : o u t s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : o u t s t d _ l o g i c ; DataOutAckxSI : i n s t d _ l o g i c ); end component ; SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL BEGIN I n s t a n t i a t e d e v i c e under t e s t . dut : f i l t e r _ s o c g e n e r i c map ( CWIDTH => CWIDTH, CAW => CAW, DWIDTH => DWIDTH, DAW => DAW) p o r t map ( ClkxCI => ClkxCI , R e s e t x R B I => ResetxRBI , D a t a I n x D I => D a t a I n x D I , D a t a I n R e q x S I => D a t a I n R e q x S I , DataInAckxSO => DataInAckxSO , DataOutxDO => DataOutxDO , DataOutReqxSO => DataOutReqxSO , DataOutAckxSI => DataOutAckxSI ); ClkxCI : s t d _ l o g i c ; ResetxRBI : s t d _ l o g i c ; D a t a I n x D I : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataInReqxSI : s t d _ l o g i c ; DataInAckxSO : s t d _ l o g i c ; DataOutxDO : s t d _ l o g i c _ v e c t o r (DWIDTH1 downto 0 ) ; DataOutReqxSO : s t d _ l o g i c ; DataOutAckxSI : s t d _ l o g i c ;
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clock_generation : PROCESS BEGIN G e n e r a t e e q u a l d u t y c y c l e c l o c k . ClkxCI <= 0 ; WAIT FOR ( c l o c k _ d e l a y / 2 ) ; ClkxCI <= 1 ; WAIT FOR ( c l o c k _ d e l a y / 2 ) ; END PROCESS c l o c k _ g e n e r a t i o n ; generate_stimulus : PROCESS BEGIN I n i t i a l i z e i n p u t s i g n a l s . D a t a I n R e q x S I <= 0 ; DataInxDI <= ( OTHERS => 0 ) ; DataOutAckxSI <= 0 ; R e s e t t h e d e s i g n and w a i t f o r 2 c l o c k c y c l e s . R e s e t x R B I <= 0 ; WAIT FOR c l o c k _ d e l a y 2 ; R e s e t x R B I <= 1 ; W a i t f o r 2 more c l o c k c y c l e s b e f o r e b e g i n n i n g t e s t . WAIT FOR c l o c k _ d e l a y 2 ; DataInxDI <= ( 0 => 1 , OTHERS => 0 ) ;
WAIT FOR c l o c k _ d e l a y ; FOR I IN 127 DOWNTO 0 LOOP D a t a I n R e q x S I <= 1 ; WHILE DataInAckxSO= 0 LOOP WAIT FOR c l o c k _ d e l a y ; END LOOP ; D a t a I n R e q x S I <= 0 ; DataInxDI <= ( OTHERS => 0 ) ; WHILE DataOutReqxSO = 0 LOOP WAIT FOR c l o c k _ d e l a y ; END LOOP ; DataOutAckxSI <= 1 ; WAIT FOR c l o c k _ d e l a y ; DataOutAckxSI <= 0 ;
APPENDIX A. APPENDIX A: VHDL NETLISTS END LOOP ; W a i t f o r e v e r . WAIT ; END PROCESS g e n e r a t e _ s t i m u l u s ; END b e h a v i o r a l ;
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Appendix B
Appendix B: Tool Scripts

B.1
B.1.1
# # # I t i s assumed t h a t a p r o j e c t d i r e c t o r y s t r u c t u r e h a s a l r e a d y b e e n # c r e a t e d u s i n g c r e a t e _ p r o j e c t and t h a t t h i s s y n t h e s i s s c r i p t i s # e x e c u t e d f r o m t h e p r o j e c t r o o t d i r e c t o r y $PROJECT_DIR # s e t PROJECT_DIR [ pwd ] # # D e s i g n r e l a t e d i n f o r m a t i o n ( can be c h a n g e d ) # s e t DESIGN f i l t e r _ s o c s e t TIM_MAX_LIBRARY f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c s e t TIM_MIN_LIBRARY f s d 0 a _ a _ g e n e r i c _ c o r e _ f f 1 p 1 v m 4 0 c s e t TIM_OC_MAX WCCOM ; # TYPICAL | WORST | WORSTIND s e t TIM_OC_MIN BCCOM ; # TYPICAL | BEST | BESTIND # Floorplan s e t t i n g s # s e t FP_ASPECT_RATIO 1 s e t FP_ROW_DENSITY 0 . 8 5 ; # p e r c e n t s e t FP_CORE2IO 224 ; # m i c r o n # Power r i n g and s e t t i n g s # 70
Synopsys: Design Compiler

lter_soc_syn.tcl
APPENDIX B. APPENDIX B: TOOL SCRIPTS
71
s e t PR_WIDTH 2 . 8 ; # m i c r o n s e t PR_SPACING 1 . 6 8 ; # m i c r o n s e t PR_LAYER_TB ME7 ; # t o p and b o t t o m l a y e r s e t PR_LAYER_LR ME8 ; # l e f t and r i g h t l a y e r # Power s t r i p e s e t t i n g s # s e t ST_NUM_SETS 1 ; # number o f s e t s s e t ST_SPACING 1 . 1 2 ; # m i c r o n s e t ST_LAYER_V $PR_LAYER_LR s e t ST_WIDTH 1 . 4 ; # m i c r o n s e t ST_XOFS_R 0 ; # m i c r o n s e t ST_XOFS_L 280 ; # m i c r o n # Placement s e t t i n g s # s e t PL_EFFORT medium ; # low | medium | h i g h # Clock t r e e s y n t h e s i s s e t t i n g s # s e t CTS_BUFFER BUFCKX1 s e t CTS_INV INVCKX1 # # # # # # # # # # # # # # # # F l a g s t h a t d r i v e t h e s c r i p t b e h a v i o r ( can be c h a n g e d ) ADD_STRIPES ( 0 | 1 ) i f 1 , add s t r i p e s PLACE_TIMING ( 0 | 1 ) i f 1 , do a t i m i n g d r i v e n p l a c e m e n t CLOCK_TREE ( 0 | 1 ) i f 1 , create a clock tree CTS_CREATE_SPEC ( 0 | 1 ) i f 1 , create a clock tree s p e c i f i c a t i o n f i l e with d e f a u l t values ROUTE_TIMING ( 0 | 1 ) i f 1 , do a t i m i n g d r i v e n r o u t i n g OPT ( s t r i n g ) can be u s e d t o h a v e d i f f e r e n t g e n e r a t e d f i l e names set set set set set set # ADD_STRIPES 1 PLACE_TIMING 1 CLOCK_TREE 1 CTS_CREATE_SPEC 0 ROUTE_TIMING 1 OPT " " # F i l e names
APPENDIX B. APPENDIX B: TOOL SCRIPTS #
72
set set set set set set set set set set set set set set set set set set set set set set set set set set # CONF_FILE_NAME $ {DESIGN} . c o n f IO_FILE_NAME $ {DESIGN} . i o DESIGN_NAME $ {DESIGN} $ {OPT} SAVE_DESIGN_FP_NAME $ {DESIGN_NAME} f p l a n . e n c SAVE_DESIGN_PR_NAME $ {DESIGN_NAME} p p l a n . e n c SAVE_DESIGN_PL_NAME $ {DESIGN_NAME} p l a c e d . e n c SAVE_DESIGN_PF_NAME $ {DESIGN_NAME} p l a c e d _ f i l l e d . e n c SAVE_DESIGN_CT_NAME $ {DESIGN_NAME} c t s . e n c SAVE_DESIGN_RO_NAME $ {DESIGN_NAME} r o u t e d . e n c TIM_RCDB_NAME $ {DESIGN_NAME} . r c d b SDF_FILE_NAME $ {DESIGN_NAME} r o u t e d . s d f SPEF_FILE_NAME $ {DESIGN_NAME} r o u t e d . s p e f RPT_CHECK_TA_NAME $ {DESIGN_NAME} c h e c k t a . r p t RPT_REPORT_TA_NAME $ {DESIGN_NAME} t a . r p t RPT_SLACK_NAME $ {DESIGN_NAME} s l a c k . r p t RPT_GATE_COUNT_NAME $ {DESIGN_NAME} g a t e _ c o u n t . r p t RPT_NOTCH_NAME $ {DESIGN_NAME} n o t c h . r p t RPT_CONN_NAME $ {DESIGN_NAME} c o n n . r p t RPT_GEOM_NAME $ {DESIGN_NAME} g e o m . r p t RPT_DENSITY_NAME $ {DESIGN_NAME} d e n s i t y . r p t VLOG_NETLIST_SIM_NAME $ {DESIGN_NAME} r o u t e d . v VLOG_NETLIST_LVS_NAME $ {DESIGN_NAME} r o u t e d _ l v s . v CTS_SPEC_NAME $ {DESIGN_NAME} s p e c . c t s t c h CTS_RGUIDE_NAME $ {DESIGN_NAME} g u i d e . c t s CTS_RPT_NAME $ {DESIGN_NAME} c t s . r p t GDS_FILE_NAME $ {DESIGN_NAME} . g d s # Absolute paths # set set set set set set set set set set set set set set CONF_FILE $ {PROJECT_DIR } / PAR / CONF / $ {CONF_FILE_NAME} IO_FILE $ {PROJECT_DIR } / PAR / CONF / $ {IO_FILE_NAME} SAVE_DESIGN_FP_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_FP_NAME} SAVE_DESIGN_PR_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_PR_NAME} SAVE_DESIGN_PL_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_PL_NAME} SAVE_DESIGN_PF_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_PF_NAME} SAVE_DESIGN_CT_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_CT_NAME} SAVE_DESIGN_RO_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_RO_NAME} SDF_FILE $ {PROJECT_DIR } / PAR / TIM / $ {SDF_FILE_NAME} SPEF_FILE $ {PROJECT_DIR } / PAR / TIM / $ {SPEF_FILE_NAME} TIM_RCDB_FILE $ {PROJECT_DIR } / PAR / TIM / $ {TIM_RCDB_NAME} RPT_CHECK_TA_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_CHECK_TA_NAME} RPT_REPORT_TA_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_REPORT_TA_NAME} RPT_SLACK_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_SLACK_NAME}
APPENDIX B. APPENDIX B: TOOL SCRIPTS set set set set set set set set set set set set # RPT_GATE_COUNT_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_GATE_COUNT_NAME} RPT_NOTCH_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_NOTCH_NAME} RPT_CONN_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_CONN_NAME} RPT_GEOM_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_GEOM_NAME} RPT_DENSITY_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_DENSITY_NAME} VLOG_NETLIST_SIM_FILE $ {PROJECT_DIR } /HDL/ GATE / $ { VLOG_NETLIST_SIM_NAME} VLOG_NETLIST_LVS_FILE $ {PROJECT_DIR } /HDL/ GATE / $ { VLOG_NETLIST_LVS_NAME} CTS_SPEC_FILE $ {PROJECT_DIR } / PAR / CTS / $ {CTS_SPEC_NAME} CTS_RGUIDE_FILE $ {PROJECT_DIR } / PAR / CTS / $ {CTS_RGUIDE_NAME} CTS_RPT_FILE $ {PROJECT_DIR } / PAR / RPT / $ {CTS_RPT_NAME} GDS_FILE $ {PROJECT_DIR } / PAR /DEX/ $ {GDS_FILE_NAME} GDS_MAP_FILE $ {PROJECT_DIR } / PAR /DEX/ g d s 2 . m a p
73
# S u p p r e s s Messages # s u p p r e s s M e s s a g e NRDB 733 s u p p r e s s M e s s a g e NREX 4 28 30 s u p p r e s s M e s s a g e SOCEXT 3032 3080 s u p p r e s s M e s s a g e SOCLF 58 200 s u p p r e s s M e s s a g e SOCOPT 3544 s u p p r e s s M e s s a g e SOCPP 2008 s u p p r e s s M e s s a g e TCLNL 330 s u p p r e s s M e s s a g e TECHLIB 436 # # Procedures # # make_clock_tree # proc m a k e _ c l o c k _ t r e e c r e a t e _ s p e c { g l o b a l PROJECT_DIR CTS_BUFFER CTS_INV CTS_SPEC_FILE CTS_RGUIDE_FILE CTS_RPT_FILE i f { $ c r e a t e _ s p e c | | ! [ f i l e e x i s t s $CTS_SPEC_FILE ] } { # createClockTreeSpec \ # b u f F o o t p r i n t $CTS_BUFFER \ # i n v F o o t p r i n t $CTS_INV \ # o u t p u t $CTS_SPEC_FILE createClockTreeSpec \ o u t p u t $CTS_SPEC_FILE } s p e c i f y C l o c k T r e e f i l e $CTS_SPEC_FILE \
74
ckSynthesis \ r g u i d e $CTS_RGUIDE_FILE \ r e p o r t $CTS_RPT_FILE o p t D e s i g n postCTS drv o u t D i r $ {PROJECT_DIR } / PAR / RPT } ;# make_clock_tree # # Load c o n f i g u r a t i o n f i l e # l o a d C o n f i g $CONF_FILE # # Load IO f i l e # l o a d I o F i l e $IO_FILE # # Set operating conditions # setOpCond \ max $TIM_OC_MAX maxLibrary $TIM_MAX_LIBRARY \ min $TIM_OC_MIN m i n L i b r a r y $TIM_MIN_LIBRARY # s e t D e s i g n M o d e p r o c e s s 90 # # Set user grids # setPreference ConstraintUserXGrid 0 .28 setPreference ConstraintUserXOffset 0 .28 setPreference ConstraintUserYGrid 0 .28 setPreference ConstraintUserYOffset 0 .28 s e t P r e f e r e n c e SnapAllCorners 1 s e t P r e f e r e n c e BlockSnapRule 2 #
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# D e f i n e g l o b a l Power n e t s make g l o b a l c o n n e c t i o n s # clearGlobalNets g l o b a l N e t C o n n e c t VCC type g l o b a l N e t C o n n e c t GND type g l o b a l N e t C o n n e c t VCC type g l o b a l N e t C o n n e c t GND type # g l o b a l N e t C o n n e c t PD type { } verbose override applyGlobalNets setDrawView f p l a n fit
p g p i n pin VCC p g p i n pin GND t i e h i module t i e l o module p g p i n pin { IO
i n s t module {} v e r b o s e i n s t module {} v e r b o s e {} v e r b o s e {} v e r b o s e VCC2O} i n s t io_VCCIO module
B.2
B.2.1
# #
Cadence: SOC Encounter

start.tcl
# I t i s assumed t h a t a p r o j e c t d i r e c t o r y s t r u c t u r e h a s a l r e a d y b e e n # c r e a t e d u s i n g c r e a t e _ p r o j e c t and t h a t t h i s s y n t h e s i s s c r i p t i s # e x e c u t e d f r o m t h e p r o j e c t r o o t d i r e c t o r y $PROJECT_DIR # s e t PROJECT_DIR [ pwd ] # # D e s i g n r e l a t e d i n f o r m a t i o n ( can be c h a n g e d ) # s e t DESIGN f i l t e r _ s o c s e t TIM_MAX_LIBRARY f s d 0 a _ a _ g e n e r i c _ c o r e _ s s 0 p 9 v 1 2 5 c s e t TIM_MIN_LIBRARY f s d 0 a _ a _ g e n e r i c _ c o r e _ f f 1 p 1 v m 4 0 c s e t TIM_OC_MAX WCCOM ; # TYPICAL | WORST | WORSTIND s e t TIM_OC_MIN BCCOM ; # TYPICAL | BEST | BESTIND # Floorplan s e t t i n g s # s e t FP_ASPECT_RATIO 1 s e t FP_ROW_DENSITY 0 . 8 5 ; # p e r c e n t s e t FP_CORE2IO 224 ; # m i c r o n # Power r i n g and s e t t i n g s
76
# s e t PR_WIDTH 2 . 8 ; # m i c r o n s e t PR_SPACING 1 . 6 8 ; # m i c r o n s e t PR_LAYER_TB ME7 ; # t o p and b o t t o m l a y e r s e t PR_LAYER_LR ME8 ; # l e f t and r i g h t l a y e r # Power s t r i p e s e t t i n g s # s e t ST_NUM_SETS 1 ; # number o f s e t s s e t ST_SPACING 1 . 1 2 ; # m i c r o n s e t ST_LAYER_V $PR_LAYER_LR s e t ST_WIDTH 1 . 4 ; # m i c r o n s e t ST_XOFS_R 0 ; # m i c r o n s e t ST_XOFS_L 280 ; # m i c r o n # Placement s e t t i n g s # s e t PL_EFFORT medium ; # low | medium | h i g h # Clock t r e e s y n t h e s i s s e t t i n g s # s e t CTS_BUFFER BUFCKX1 s e t CTS_INV INVCKX1 # # # # # # # # # # # # # # # # F l a g s t h a t d r i v e t h e s c r i p t b e h a v i o r ( can be c h a n g e d ) ADD_STRIPES ( 0 | 1 ) i f 1 , add s t r i p e s PLACE_TIMING ( 0 | 1 ) i f 1 , do a t i m i n g d r i v e n p l a c e m e n t CLOCK_TREE ( 0 | 1 ) i f 1 , create a clock tree CTS_CREATE_SPEC ( 0 | 1 ) i f 1 , create a clock tree s p e c i f i c a t i o n f i l e with d e f a u l t values ROUTE_TIMING ( 0 | 1 ) i f 1 , do a t i m i n g d r i v e n r o u t i n g OPT ( s t r i n g ) can be u s e d t o h a v e d i f f e r e n t g e n e r a t e d f i l e names set set set set set set # ADD_STRIPES 1 PLACE_TIMING 1 CLOCK_TREE 1 CTS_CREATE_SPEC 0 ROUTE_TIMING 1 OPT " " # F i l e names
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set set set set set set set set set set set set set set set set set set set set set set set set set set # CONF_FILE_NAME $ {DESIGN} . c o n f IO_FILE_NAME $ {DESIGN} . i o DESIGN_NAME $ {DESIGN} $ {OPT} SAVE_DESIGN_FP_NAME $ {DESIGN_NAME} f p l a n . e n c SAVE_DESIGN_PR_NAME $ {DESIGN_NAME} p p l a n . e n c SAVE_DESIGN_PL_NAME $ {DESIGN_NAME} p l a c e d . e n c SAVE_DESIGN_PF_NAME $ {DESIGN_NAME} p l a c e d _ f i l l e d . e n c SAVE_DESIGN_CT_NAME $ {DESIGN_NAME} c t s . e n c SAVE_DESIGN_RO_NAME $ {DESIGN_NAME} r o u t e d . e n c TIM_RCDB_NAME $ {DESIGN_NAME} . r c d b SDF_FILE_NAME $ {DESIGN_NAME} r o u t e d . s d f SPEF_FILE_NAME $ {DESIGN_NAME} r o u t e d . s p e f RPT_CHECK_TA_NAME $ {DESIGN_NAME} c h e c k t a . r p t RPT_REPORT_TA_NAME $ {DESIGN_NAME} t a . r p t RPT_SLACK_NAME $ {DESIGN_NAME} s l a c k . r p t RPT_GATE_COUNT_NAME $ {DESIGN_NAME} g a t e _ c o u n t . r p t RPT_NOTCH_NAME $ {DESIGN_NAME} n o t c h . r p t RPT_CONN_NAME $ {DESIGN_NAME} c o n n . r p t RPT_GEOM_NAME $ {DESIGN_NAME} g e o m . r p t RPT_DENSITY_NAME $ {DESIGN_NAME} d e n s i t y . r p t VLOG_NETLIST_SIM_NAME $ {DESIGN_NAME} r o u t e d . v VLOG_NETLIST_LVS_NAME $ {DESIGN_NAME} r o u t e d _ l v s . v CTS_SPEC_NAME $ {DESIGN_NAME} s p e c . c t s t c h CTS_RGUIDE_NAME $ {DESIGN_NAME} g u i d e . c t s CTS_RPT_NAME $ {DESIGN_NAME} c t s . r p t GDS_FILE_NAME $ {DESIGN_NAME} . g d s # Absolute paths # set set set set set set set set set set set set set set CONF_FILE $ {PROJECT_DIR } / PAR / CONF / $ {CONF_FILE_NAME} IO_FILE $ {PROJECT_DIR } / PAR / CONF / $ {IO_FILE_NAME} SAVE_DESIGN_FP_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_FP_NAME} SAVE_DESIGN_PR_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_PR_NAME} SAVE_DESIGN_PL_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_PL_NAME} SAVE_DESIGN_PF_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_PF_NAME} SAVE_DESIGN_CT_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_CT_NAME} SAVE_DESIGN_RO_FILE $ {PROJECT_DIR } / PAR /DB/ $ {SAVE_DESIGN_RO_NAME} SDF_FILE $ {PROJECT_DIR } / PAR / TIM / $ {SDF_FILE_NAME} SPEF_FILE $ {PROJECT_DIR } / PAR / TIM / $ {SPEF_FILE_NAME} TIM_RCDB_FILE $ {PROJECT_DIR } / PAR / TIM / $ {TIM_RCDB_NAME} RPT_CHECK_TA_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_CHECK_TA_NAME} RPT_REPORT_TA_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_REPORT_TA_NAME} RPT_SLACK_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_SLACK_NAME}
APPENDIX B. APPENDIX B: TOOL SCRIPTS set set set set set set set set set set set set # RPT_GATE_COUNT_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_GATE_COUNT_NAME} RPT_NOTCH_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_NOTCH_NAME} RPT_CONN_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_CONN_NAME} RPT_GEOM_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_GEOM_NAME} RPT_DENSITY_FILE $ {PROJECT_DIR } / PAR / RPT / $ {RPT_DENSITY_NAME} VLOG_NETLIST_SIM_FILE $ {PROJECT_DIR } /HDL/ GATE / $ { VLOG_NETLIST_SIM_NAME} VLOG_NETLIST_LVS_FILE $ {PROJECT_DIR } /HDL/ GATE / $ { VLOG_NETLIST_LVS_NAME} CTS_SPEC_FILE $ {PROJECT_DIR } / PAR / CTS / $ {CTS_SPEC_NAME} CTS_RGUIDE_FILE $ {PROJECT_DIR } / PAR / CTS / $ {CTS_RGUIDE_NAME} CTS_RPT_FILE $ {PROJECT_DIR } / PAR / RPT / $ {CTS_RPT_NAME} GDS_FILE $ {PROJECT_DIR } / PAR /DEX/ $ {GDS_FILE_NAME} GDS_MAP_FILE $ {PROJECT_DIR } / PAR /DEX/ g d s 2 . m a p
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# S u p p r e s s Messages # s u p p r e s s M e s s a g e NRDB 733 s u p p r e s s M e s s a g e NREX 4 28 30 s u p p r e s s M e s s a g e SOCEXT 3032 3080 s u p p r e s s M e s s a g e SOCLF 58 200 s u p p r e s s M e s s a g e SOCOPT 3544 s u p p r e s s M e s s a g e SOCPP 2008 s u p p r e s s M e s s a g e TCLNL 330 s u p p r e s s M e s s a g e TECHLIB 436 # # Procedures # # make_clock_tree # proc m a k e _ c l o c k _ t r e e c r e a t e _ s p e c { g l o b a l PROJECT_DIR CTS_BUFFER CTS_INV CTS_SPEC_FILE CTS_RGUIDE_FILE CTS_RPT_FILE i f { $ c r e a t e _ s p e c | | ! [ f i l e e x i s t s $CTS_SPEC_FILE ] } { # createClockTreeSpec \ # b u f F o o t p r i n t $CTS_BUFFER \ # i n v F o o t p r i n t $CTS_INV \ # o u t p u t $CTS_SPEC_FILE createClockTreeSpec \ o u t p u t $CTS_SPEC_FILE } s p e c i f y C l o c k T r e e f i l e $CTS_SPEC_FILE \
79
ckSynthesis \ r g u i d e $CTS_RGUIDE_FILE \ r e p o r t $CTS_RPT_FILE o p t D e s i g n postCTS drv o u t D i r $ {PROJECT_DIR } / PAR / RPT } ;# make_clock_tree # # Load c o n f i g u r a t i o n f i l e # l o a d C o n f i g $CONF_FILE # # Load IO f i l e # l o a d I o F i l e $IO_FILE # # Set operating conditions # setOpCond \ max $TIM_OC_MAX maxLibrary $TIM_MAX_LIBRARY \ min $TIM_OC_MIN m i n L i b r a r y $TIM_MIN_LIBRARY # s e t D e s i g n M o d e p r o c e s s 90 # # Set user grids # setPreference ConstraintUserXGrid 0 .28 setPreference ConstraintUserXOffset 0 .28 setPreference ConstraintUserYGrid 0 .28 setPreference ConstraintUserYOffset 0 .28 s e t P r e f e r e n c e SnapAllCorners 1 s e t P r e f e r e n c e BlockSnapRule 2 #
80
# D e f i n e g l o b a l Power n e t s make g l o b a l c o n n e c t i o n s # clearGlobalNets g l o b a l N e t C o n n e c t VCC type g l o b a l N e t C o n n e c t GND type g l o b a l N e t C o n n e c t VCC type g l o b a l N e t C o n n e c t GND type # g l o b a l N e t C o n n e c t PD type { } verbose override applyGlobalNets setDrawView f p l a n fit
p g p i n pin VCC p g p i n pin GND t i e h i module t i e l o module p g p i n pin { IO
i n s t module {} v e r b o s e i n s t module {} v e r b o s e {} v e r b o s e {} v e r b o s e VCC2O} i n s t io_VCCIO module
B.2.2
#
fplan.tcl
# I n i t i a l i z e floorplan # # f l o o r P l a n b 0 .0 0 . 0 1872 . 0 8 1872 . 0 8 \ # 219 . 8 219 . 8 1092 . 2 8 1092 . 2 8 \ # 779 . 8 779 . 8 1092 . 2 8 1092 . 2 8 # f l o o r P l a n b 0 .0 0 . 0 1872 . 0 8 1872 . 0 8 \ # 219 . 8 219 . 8 1652 . 2 8 1652 . 2 8 \ # 261 . 8 261 . 8 1610 . 2 8 1610 . 2 8 # f l o o r P l a n d # 1872 . 0 8 1872 . 0 8 \ 280 . 0 280 . 0 280 . 0 280 . 0
f l o o r P l a n d
1872 . 0 8 1872 . 0 8 \ 560 . 0 560 . 0 560 . 0 560 . 0 3874 . 9 2 1874 . 8 8 \ 1400 . 0 560 . 0 1400 . 0 560 . 0
# f l o o r P l a n d #
# snapFPlanIO u s e r g r i d # snapFPlan all # setPlanDesignMode useExistingPowerRail t r u e # setPlanDesignMode fixPlacedMacros t r u e
APPENDIX B. APPENDIX B: TOOL SCRIPTS # s e t P l a n D e s i g n M o d e groupHardMacro t r u e e f f o r t medium b o u n d a r y P l a c e true s e t P l a n D e s i g n M o d e groupHardMacro t r u e b o u n d a r y P l a c e t r u e planDesign # f i n i s h F l o o r p l a n autoHalo a u t o B l o c k a g e s t a i r c a s e f i n i s h F l o o r p l a n addHalo 14 a u t o B l o c k a g e s o u r c e $ {PROJECT_DIR } / PAR / BIN / f i l l p e r i . t c l
81
s a v e D e s i g n $SAVE_DESIGN_FP_FILE setDrawView f p l a n fit
B.2.3
pplan.tcl
## F i l e : pwr.tcl # # C r e a t e d a t : Mon Jun 07 16 : 3 3 : 0 3 CEST 2010 # # C r e a t e d by : A l e x a n d e r de G r a a f p u t s " Power P l a n n i n g " set crwidth 2 .8 set crspace 2 .80 s e t c r o f f s e t 28 . 0 0 set brwidth 1 .12 set brspace 0 .56 set b r o f f s e t 4 .20 set vswidth 0 .94 set vsspace 1 .68 set v s o f f s e t 2 .80
set hswidth 0 .94 set hsspace 1 .68 set h s o f f s e t 2 .80 cutRow clearCutRow deselectAll # #################################################################################
# # Generate core r i n g s # # #################################################################################
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p u t s " Making Power R i n g s " setAddRingOption avoid_short 0 ignore_rows 0 a d d R i n g n e t s {GND VCC} around c o r e \ l a y e r _ t o p ME5 l a y e r _ b o t t o m ME5 \ l a y e r _ l e f t ME6 l a y e r _ r i g h t ME6 \ width_top $ c r w i d t h width_bottom $ c r w i d t h w i d t h _ l e f t $ c r w i d t h width_right $crwidth \ spacing_top $crspace spacing_bottom $crspace s p a c i n g _ l e f t $crspace spacing_right $crspace \ offset_top $ c r o f f s e t offset_bottom $ c r o f f s e t o f f s e t _ l e f t $croffset offset_right $croffset \ s n a p _ w i r e _ c e n t e r _ t o _ g r i d None # center 1 deselectAll # # #################################################################################
# # Generate block r i n g s # # ################################################################################# # # G e n e r a t e b l o c k r i n g a r o u n d b u f f e r memory s e l e c t I n s t i _ f i l t e r _ t o p / i_dataRAM_i_dmem setAddRingOption avoid_short 0 ignore_rows 0 extend_over_row 0 a d d R i n g n e t s {GND VCC} type b l o c k _ r i n g s around s e l e c t e d \ l a y e r _ t o p ME5 l a y e r _ b o t t o m ME5 \ l a y e r _ l e f t ME6 l a y e r _ r i g h t ME6 \ width_top $ b r w i d t h width_bottom $ b r w i d t h w i d t h _ l e f t $ b r w i d t h width_right $brwidth threshold auto \ spacing_top $brspace spacing_bottom $brspace s p a c i n g _ l e f t $brspace spacing_right $brspace \ offset_top $ b r o f f s e t offset_bottom $ b r o f f s e t o f f s e t _ l e f t $broffset offset_right $broffset \ use_wire_group 1 u s e _ i n t e r l e a v i n g _ w i r e _ g r o u p 0 u s e _ w i r e _ g r o u p _ b i t s 1 s n a p _ w i r e _ c e n t e r _ t o _ g r i d None deselectAll # # G e n e r a t e b l o c k r i n g a r o u n d c o e f f i c i e n t rom s e l e c t I n s t i _ f i l t e r _ t o p / i_coeff_a9d16 setAddRingOption avoid_short 0 ignore_rows 0 extend_over_row 0 a d d R i n g n e t s {GND VCC} type b l o c k _ r i n g s around s e l e c t e d \ l a y e r _ t o p ME5 l a y e r _ b o t t o m ME5 \ l a y e r _ l e f t ME6 l a y e r _ r i g h t ME6 \ width_top $ b r w i d t h width_bottom $ b r w i d t h w i d t h _ l e f t $ b r w i d t h width_right $brwidth threshold auto \
83
spacing_top $brspace spacing_bottom $brspace s p a c i n g _ l e f t $brspace spacing_right $brspace \ offset_top $ b r o f f s e t offset_bottom $ b r o f f s e t o f f s e t _ l e f t $broffset offset_right $broffset \ use_wire_group 1 u s e _ i n t e r l e a v i n g _ w i r e _ g r o u p 0 u s e _ w i r e _ g r o u p _ b i t s 1 s n a p _ w i r e _ c e n t e r _ t o _ g r i d None deselectAll # #################################################################################
# # Generate s t r i p e s # # #################################################################################
# # p u t s " Making Power S t r i p e s " # setAddStripeOption remove_floating_stripe_over_block 1 # a d d S t r i p e n e t s {GND VCC} d i r e c t i o n v e r t i c a l l a y e r ME4 \ # width $ v s w i d t h s p a c i n g $ v s s p a c e s e t _ t o _ s e t _ d i s t a n c e 300 . 1 6 \ # x l e f t _ o f f s e t 200 . 2 0 x r i g h t _ o f f s e t 84 . 0 \ # e x t e n d _ t o none m e r g e _ s t r i p e s _ v a l u e a u t o b r e a k _ s t r i p e s _ a t _ b l o c k _ r i n g s 1 s n a p _ w i r e _ c e n t e r _ t o _ g r i d None #deselectAll # #################################################################################
# # R o u t e VCC and GND c o r e r i n g s t o pad p i n s o f VCC /GND I O c e l l s # # ################################################################################# # # s r o u t e noCorePins noPadRings n o S t r i p e s j o g C o n t r o l { p r e f e r W i t h C h a n g e s d i f f e r e n t L a y e r } n e t s {GND VCC} s r o u t e a l l o w J o g g i n g 1 a l l o w L a y e r C h a n g e 1 n e t s {GND VCC} # s a v e D e s i g n $SAVE_DESIGN_PR_FILE setDrawView f p l a n fit p u t s " Power P l a n n i n g done "
B.2.4
place.tcl
84
# Core c e l l p l a c e m e n t # i f { $PLACE_TIMING } { # specifyCellPad 1 # s p e c i f y I n s t P a d MBLITE_SOC_INST / 1 # s e t P l a c e M o d e t d I n s t P a d d i n g t r u e padForPinNearBorder t r u e # s e t P l a c e M o d e c o n g E f f o r t $PL_EFFORT t i m i n g D r i v e n t r u e i g n o r e S c a n t r u e t d I n s t P a d d i n g t r u e padForPinNearBorder t r u e # s e t P l a c e M o d e c o n g E f f o r t $PL_EFFORT t i m i n g D r i v e n t r u e i g n o r e S c a n t r u e modulePlan t r u e s e t P l a c e M o d e c o n g E f f o r t $PL_EFFORT t i m i n g D r i v e n t r u e modulePlan t r u e placeDesign } else { # s e t P l a c e M o d e c o n g E f f o r t $PL_EFFORT i g n o r e S c a n t r u e s e t P l a c e M o d e c o n g E f f o r t $PL_EFFORT placeDesign } # s e t O p t M o d e y i e l d E f f o r t none # setOptMode h i g h E f f o r t # s e t O p t M o d e maxDensity 0 . 9 5 # s e t O p t M o d e drcMargin 0 . 0 # setOptMode holdTargetSlack 0 . 0 s e t u p T a r g e t S l a c k 0 . 0 # setOptMode n o S i m p l i f y N e t l i s t # clearClockDomains # setClockDomains all # s e t O p t M o d e noUsefulSkew # o p t D e s i g n preCTS s e t u p drv \ # outDir $ { PROJECT_DIR } / PAR / RPT # Save t h e d e s i g n so f a r s a v e D e s i g n $SAVE_DESIGN_PL_FILE p u t s "Done P l a c i n g Cells " setDrawView p l a c e fit
B.2.5
#
cts.tcl
# Create clock t r e e ( o p t i o na l ) #
85
s e t D e s i g n M o d e p r o c e s s 90 i f { $CLOCK_TREE } { m a k e _ c l o c k _ t r e e $CTS_CREATE_SPEC s a v e D e s i g n $SAVE_DESIGN_CT_FILE }
B.2.6
#
route.tcl
# Route design ( Nanoroute ) # p u t s "Add F i l l e r Cells" # # Add f i l l e r c e l l s # s o u r c e $ {PROJECT_DIR } / PAR / BIN / f i l l c o r e . t c l p u t s "Routing" # # Unfix the clock nets to avoid routing problems. c h a n g e U s e C l o c k N e t S t a t u s noFixedNetWires setNanoRouteMode d r o u t e F i x A n t e n n a t r u e setNanoRouteMode r o u t e A n t e n n a C e l l N a m e "ANT" setNanoRouteMode r o u t e I n s e r t A n t e n n a D i o d e t r u e i f { $ROUTE_TIMING } { # C o n f i g u r e NanoRoute t o do t h e f i n a l r o u t i n g setNanoRouteMode q u i e t t i m i n g E n g i n e CTE setNanoRouteMode q u i e t r o u t e W i t h T i m i n g D r i v e n t r u e setNanoRouteMode q u i e t r o u t e T d r E f f o r t 0 } s e t D e s i g n M o d e p r o c e s s 90 # Do t h e a c t u a l r o u t i n g globalDetailRoute p u t s " Postroute optimize " #
APPENDIX B. APPENDIX B: TOOL SCRIPTS # The f i n a l o p t i m i z a t i o n s t e p p o s t r o u t e # s e t O p t M o d e y i e l d E f f o r t none # setOptMode h i g h E f f o r t # s e t O p t M o d e maxDensity 0 . 9 5 # s e t O p t M o d e drcMargin 0 . 0 # setOptMode holdTargetSlack 0 . 0 s e t u p T a r g e t S l a c k 0 . 0 # setOptMode n o S i m p l i f y N e t l i s t # clearClockDomains # setClockDomains all # s e t O p t M o d e noUsefulSkew # o p t D e s i g n p o s t R o u t e drv p r e f i x T i m i n g R e p o r t s \ # outDir $ { PROJECT_DIR } / PAR / RPT # s a v e D e s i g n $SAVE_DESIGN_PF_FILE o p t D e s i g n p o s t R o u t e drv o u t D i r $ {PROJECT_DIR } / PAR / RPT s a v e D e s i g n $SAVE_DESIGN_RO_FILE setDrawView p l a c e p u t s " Routing done"
86
B.2.7
#
pplan.tcl
# Verifications # # Connectivity f i l l N o t c h r e p o r t $RPT_NOTCH_FILE verifyConnectivity \ type a l l \ e r r o r 1000 \ warning 50 \ connectPadSpecialPorts \ r e p o r t $RPT_CONN_FILE # Geometry verifyGeometry \ allowSameCellViols \ allowRoutingBlkgPinOverlap \ allowRoutingCellBlkgOverlap \ r e p o r t $RPT_GEOM_FILE
B.2.8
#
verify.tcl
87
# Extract parasitics # # rcdb $TIM_RCDB_FILE # reduce 5 # for 9 .1 # engine p o s t R o u t e [ e f f o r t L e v e l <low | medium | h i g h | # engine p o s t R o u t e e f f o r t L e v e l low \ # for 8 .1 # engine d e t a i l s e t D e s i g n M o d e p r o c e s s 90 setExtractRCMode \ engine d e t a i l \ coupled t r u e \ relative_c_th 0 .01 \ total_c_th 5 .0 extractRC # # G e n e r a t e RC and t i m i n g f i l e s # r c O u t spef $SPEF_FILE # d e l a y C a l sdf $SDF_FILE w r i t e _ s d f $SDF_FILE # # Generate r e p o r t s # r e p o r t G a t e C o u n t o u t f i l e $RPT_GATE_COUNT_FILE # Timings # setCteReport s e t A n a l y s i s M o d e checkType s e t u p asyncChecks a s y n c skew t r u e clockPropagation forcedIdeal sequentialConstProp true # s e t A n a l y s i s M o d e domain a l l C l o c k D o m a i n checkType s e t u p skew t r u e u s e f u l S k e w f a l s e log t r u e warn t r u e c a s e A n a l y s i s t r u e s e q u e n t i a l C o n s t P r o p t r u e moduleIOCstr t r u e c l o c k P r o p a g a t i o n f o r c e d I d e a l clkSrcPath t r u e timingSelfLoopsNoSkew f a l s e asyncChecks a s y n c useOutputPinCap t r u e l a t c h t r u e l a t c h D e l a y C a l I t e r a t i o n 2 timeBorrowing t r u e latchFullDelayCal
APPENDIX B. APPENDIX B: TOOL SCRIPTS f a l s e clockGatingCheck t r u e enableMultipleDriveNet t r u e a n a l y s i s T y p e bcWc cppr f a l s e c l k N e t s M a r k i n g b e f o r e C o n s t P r o p h o n o r V i r t u a l P a r t i t i o n f a l s e honorClockDomains t r u e
88
reportAnalysisMode buildTimingGraph c h e c k _ t i m i n g v e r b o s e > $RPT_CHECK_TA_FILE report_timing \ format { h p i n a r c c e l l d e l a y a r r i v a l r e q u i r e d s l e w f a n o u t l o a d } \ late \ max_points 10 \ net \ > $RPT_REPORT_TA_FILE # # Save n e t l i s t # s a v e N e t l i s t e x c l u d e L e a f C e l l $VLOG_NETLIST_SIM_FILE s a v e N e t l i s t p h y s i c a l $VLOG_NETLIST_LVS_FILE # # S a v e GDS2 # s t r e a m O u t $GDS_FILE \ mapFile $GDS_MAP_FILE \ libName D e s i g n L i b \ s t r u c t u r e N a m e $DESIGN_NAME \ outputMacros \ uniquifyCellNames \ stripes 1 \ u n i t s 1000 \ mode ALL
Appendix C
Appendix C: Design Metrics

A design begins with the planning of the die. The mini@sic program from EuroPractice is a multiproject wafer where a minimum area of 1875 x 1875 um2 is required. This area constraint is the startpoint for planning the whole chip. Another important issue is the cell library metrics. The metrics of Faraday L90_SP library are:
Description Grid Core Cell IO Cell Corner Cell Pad Cell
Width 0.28 um x * 0.28 um 60.48 um 142.8 um 64 um
Height 0.28 um 2.8 um 142.8 um 142.8 um 77 um
89

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Code ET4351

Digital Design Flow

Delft University of Technology

Ir. A.C. de Graaf Dr. ir. T.G.R. van Leuken

Figure 1.1: Top-down design ow

Design project organisation

Figure 1.2: Design project structure.

EDA tools and design kit conguration

VHDL example: FIR-Filter

Figure 1.3: VHDL design hierarchy

VHDL and Verilog simulation

Starting the Modelsim graphical environment

Figure 2.1: Modelsim console window

CHAPTER 2. VHDL AND VERILOG SIMULATION

Simulation of (pre-synthesis) RTL VHDL models

, to select the les to compile in the HDL/RTL

CHAPTER 2. VHDL AND VERILOG SIMULATION

CHAPTER 2. VHDL AND VERILOG SIMULATION

Simulation of the post-synthesis Verilog model with timing data

CHAPTER 2. VHDL AND VERILOG SIMULATION

Simulation of the post-route Verilog model with timing data

CHAPTER 2. VHDL AND VERILOG SIMULATION

or execute the shell script compile_msim_far_routed.sh.

Starting the Design Vision graphical environment

CHAPTER 3. LOGIC SYNTHESIS

RTL VHDL model analysis

CHAPTER 3. LOGIC SYNTHESIS

Design environment denition

CHAPTER 3. LOGIC SYNTHESIS

Design constraint denitions

CHAPTER 3. LOGIC SYNTHESIS

CHAPTER 3. LOGIC SYNTHESIS

Design mapping and optimization

CHAPTER 3. LOGIC SYNTHESIS

CHAPTER 3. LOGIC SYNTHESIS

Report : timing p a t h f u l l d e l a y max m a x _ p a t h s 1 s o r t _ b y group

CHAPTER 3. LOGIC SYNTHESIS

CHAPTER 3. LOGIC SYNTHESIS

A new window and the console now display the report:

CHAPTER 3. LOGIC SYNTHESIS

C e l l I n t e r n a l Power Net S w i t c h i n g Power T o t a l Dynamic Power

(95%) (5%) (100%)

CHAPTER 3. LOGIC SYNTHESIS

CHAPTER 3. LOGIC SYNTHESIS

Design constraints generation for placement and routing

Design optimization with tighter constraints

CHAPTER 3. LOGIC SYNTHESIS

Standard cell placement and routing

Starting the Encounter graphical environment

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

Generate uniquied netlist

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

Global net connections

Power ring/stripe creation and routing

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

Operating conditions denition

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

Core cell placement

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING

CHAPTER 4. STANDARD CELL PLACEMENT AND ROUTING