Analog Circuit Design in Nanoscale CMOS Technologies

Opportunities and Challenges

Trond Ytterdal Circuits and Systems Group Department of Electronics and Telecommunication Norwegian University of Science and Technology (NTNU) 2006-2007: Sabbatical at UofT Room: BA5106 trond@eecg.toronto.edu
October 11, 2006

Trond Ytterdal, Department of Electronics and Telecommunication

Outline
Introduction Transistor performance
How does transistor performance change as technology is scaled down to nanoscale* nanoscale dimensions

Analog circuit performance

How does analog circuit performance change as technology is scaled down

*The

term nanoscale is used for dimensions less than 100nm

Trond Ytterdal, Department of Electronics and Telecommunication

CMOS technology downscaling

10 Printed gate length P h [ m] 3m 1 2m Data from INTEL ITRS Roadmap 1.5m 0.8 0 8m 0.5m 0.35m 0.18m 0.1 90nm 45nm 32 32nm 18nm 0.01 1970 1975 1980 1985 1990 Year
10

1995

2000

2005

2010

2015

Vdd [V]

0.1 1970 1975 1980 1985 1990 Year 1995 2000 2005 2010 2015

Gate length divided by two approximately every 5 years

3 Trond Ytterdal, Department of Electronics and Telecommunication

Transistor performance
Transistor performance metrics for analog and RF design:
Transconductance Intrinsic gain (gm/gds) Capacitances Maximum operating p g frequency q y Efficiency (gm/Id) Linearity Noise Mismatch Gate leakage

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Transconductance and intrinsic gain

1.E-03 1.E 03 65 nm 1.E-04 90 nm 0.13 um 0.18 um 1.E-05

Transconductance is, for f all practical purposes, independent of the technology node F a velocity For l it saturated t t d channel: h l

gm [S]

1.E-06

I d = WcoxVeff vs g m = Wcox vs
Minimum gate length, same W /L V ds = 1/2V DD

1.E-07

1.E-08

1.E-09 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

W L; cox

Drain current [A]

70 60 50 40 30 20 10 0 1.E-10

1 L g m does d not t scale l

Minimum gate length, same W /L V ds = 1/2V DD

65 nm 90 nm 0.13 um 0.18 um

Intrinsic gain is reduced as technologies are scaled down down. At the 65nm node the maximum intrinsic gain is reduced by more than 80% compared to the g gain at the 0.18m node.

gm /gds

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

Drain current [A]

Trond Ytterdal, Department of Electronics and Telecommunication

Transistor capacitances
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 90nm 0.13um 0.18um
Cgs Cdb
Minimum gate length, same W /L ; V ds = 0

Capacitances extracted from NMOS having minimum drain and source areas for the given W/L (~3).

Capacitance e [fF]

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Maximum operating frequency

The maximum speed of an amplifier is limited by the ratio of the transconductance and the capacitance of a transistor:
fT =
1.0E+12

gm 2(C gs + C gd + Cdb )
2.5E-04

(1)

65 nm
1.0E+11

90 nm 0.13 um

Minimum Mi i gate length, l h same W /L V ds = 1/2V DD

2.0E-04

gm /(Cgs +Cdb )/2 [Hz]

1.0E+10 1.0E+09

0.18 um

1 5E-04 1.5E 04

1.0E+08 1.0E+07 1.0E+06 1.0E+05 1.E-10

Id [A]
1.0E-04

Minimum gate length, same W /L Vds = 1/2V DD

1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

5.0E-05

90nm 130nm 180nm

0.0E+00 1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

D i current Drain t [A]

f T [Hz]

Trond Ytterdal, Department of Electronics and Telecommunication

Potential speed improvement

6.0

Potential spe eed improvem ment of scaling

65 nm 5.0

90 nm

0 13 um 0.13

0 18 um 0.18

4.0

3.0

20 2.0

By scaling down a potential improvement in speed can be obtained compared to realization in a 0.18m technology
1.E-03

1.0

Minimum gate length, same W /L ; V ds = 1/2V DD Speed potential normalized to the 0.18m node
0.0 0 0 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04

Drain current [A]

Trond Ytterdal, Department of Electronics and Telecommunication

Transistor efficiency (gm/ID)

35

Minimum gate length; W /L = 5; V ds = 1V

30 25

90nm 0.13um 0.18um 0.25um

gm /ID [ [1/V]

20 15 10 5 0 1.0E-12

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

Drain current [A]

The transistor is most efficient (maximum bang for the buck) in weak inversion Maximum value is nearly independent of technology
9 Trond Ytterdal, Department of Electronics and Telecommunication

Linearity (1)
The Taylor expansion of the small signal drain current of a MOS transistor can be written as: 2 id = g m v gs + a 2 g m v gs + a3 g m v 3 gs + L
2 3 + g ds vds + a 2 g ds vds + a3 g ds vds +L 2 3 + g mb b vbs b + a 2 g mb vbs b + a3 g mb vbs b +L 2 2 + a 2 g m g ds v gs vds + a32 g m g ds v gs vds + a3 g m 2 g ds v gs vds +L 2 2 + a 2 g m g mb v gs vbs + a32 g m g mb v gs +L vbs + a3 g m 2 g mb v gs vbs 2 2 + a 2 g ds g mb vds vbs + a32 g ds g mb vds vbs + a3 g ds 2 g mb vds vbs +L

+ a3 g m g ds g mb v gs vds vbs + L

Here, the coefficients are the higher order derivatives of the total drain current with respect to one or more of the control voltages. voltages For example:
1 2Id a2 g m = 2 2 Vgs
10 Trond Ytterdal, Department of Electronics and Telecommunication

Linearity (2)
1.0E-03 1.0E-04 1.0E-05

|a 2gds| [S/V V]

1 0E 06 1.0E-06 1.0E-07 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 1.E-10

90nm 0.13um 0.18um

Second order nonlinearity in channel conductance (gds) increases as t h l technology i is scaled down.
1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

1.E-09

Id [A]
1.0E-02

1 0E 03 1.0E-03

a 2g gm [S/V]

90nm 0 13um 0.13um 0.18um

1.0E-04

1 0E 05 1.0E-05

1.0E-06

Second order nonlinearity li it i in transconductance almost independent of technology

1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03

1.0E-07 1 0E 07 1.0E-10

1.0E-09

Id [A]
11 Trond Ytterdal, Department of Electronics and Telecommunication

Noise
Equivalent noise PSD (power spectral density) referred to the gate of a transistor connected in a common-source configuration*:
K 2 = 4 k BT + Vng g m WLcox f ; K process dependent

Si-SiO2 interface noise Channel noise Increases at low current Minimum in weak inversion for given current Traditionally [1], the following expression is used for :
2n / 3 in strong inversion = n / 2 in weak inversion

*Transform

valid up to a frequency ~ gm/Cgd

Trond Ytterdal, Department of Electronics and Telecommunication

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Potential SNR (1)

Thermal noise
1 = 2 gm I nd 4 k BT Id Id
2 Id
120 65nm 100 90nm 0.13um 0.18um 80

10log( (10-6Id 2/Ind 2) [ [dB]

60

D Decreases at tl low current Minimum in weak inversion for a given current

40

20

Minimum gate length, same W /L ; V ds = 1V

0 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

Drain current [A]

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Trond Ytterdal, Department of Electronics and Telecommunication

Potential SNR (2)

Flicker noise
2 Id 2 I nd

WLf
10log(Id 2/(Ind 2Agate )) [dB]

80
65nm

gm 4k BTK I d

75

90nm (L = 0.1um) 0.13um 0.18um

70

65

D Decreases at tl low current Minimum in weak inversion for a given current

60

55

Minimum gate length, same W /L ; V ds = V DD /2

50 1.E-11 1.E-09 1.E-07 1.E-05 1.E-03

Drain current [A]

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Trond Ytterdal, Department of Electronics and Telecommunication

Mismatch (1)
Mismatch of two matched transistors identical by design can be characterized by:
VT = VT 1 VT 2 with VT = (VT ) = AVT / WL / = 2(1 2 ) /( (1 + 2 ) with = ( /) = A / WL

AVT and A depends on process, layout and more Based on the quadratic MOS model, one can derive the following well known formulas:
Same gate voltage:
I d I d gm 2 = + VT Id
2

Same drain current:

Id 2 (VG ) = VT + g m
2

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Mismatch (2)
Mismatch per unit area decreases as technologies are scaled down
From theory and ideal scaling:

AVT tox Lmin

In reality I lit AVT does d not t scale l as fast as Lmin
100

Gate area required for any given (VT) normalized to the Lmin = 70nm
1000

Relative gate area

100

AVT [mV Vm]

10

10
1 0.01 0.1 1 10

Minimum g gate length g [ m] ]

1 0.01

0.1

10

Minimum gate length [m] Experimental Data from [2]

16 Trond Ytterdal, Department of Electronics and Telecommunication

Gate leakage current (1)

Gate current can NOT be neglected in scaled down technologies. Dominated by tunneling current => Relatively insensitive to device temperature.
1.E-04 1.E-05 1.E-06

Minimum gate length, gate width = 100m

90nm (simulated) 0.13um 0.13um (simulated) 0.18um

VG

Gate current [A]

IG

1.E-07 1.E-08 1.E-09 1.E-10 1.E-11 1.E-12 1.E-13 1.E-14

0.5

1.5

Gate voltage [V]

g-flavor technologies
17 Trond Ytterdal, Department of Electronics and Telecommunication

Gate leakage current (2)

VG IG
Small signal equivalent circuit assuming low to moderate frequencies and strong inversion

vg ig

ic

itunnel gtunnel

Cox

At a given frequency the impedance of the two branches have the same magnitude g and the currents ic and itunnel will be equal q in magnitude. This frequency is given by
gateCox = gtunnel 1 gtunnel f gate = 2 Cox

Above this frequency, frequency the total gate current is dominated by ic as in the traditional case.
18 Trond Ytterdal, Department of Electronics and Telecommunication

fgate versus technology

fgate is almost gate area i d independent d t and d an approximate i t expression is given in [3] as:
fgate [Hz]
104 103 102 101 100 10-1 10-2 10-3
4 10-4

90nm 0.13m 0.18m

2 ox f gate t K fg f Vgs e

t (V gs 13.6)

Here, tox is the oxide thickness in nm and Kfg is 1 1.5 51016 for NMOS and 0.51016 for PMOS. A plot of this expression is shown to the right for three different technologies.

10-5 10-6 10-7 10-8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Veff [V]

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Analog circuit performance

Analog and RF circuit performance metrics:
Accuracy (Dynamic range) Speed Power consumption

Accuracy

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FOM definition
One commonly used Figure-of-merit (FOM) definition:
FOM = P DR 2 f

Here, P is the power consumption, DR is the dynamic range and f is the highest signal frequency that can be processed by the circuit Small is GOOD.

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Dynamic range (1)

Here, we define the dynamic range (DR) as the ratio of the largest to the smallest possible signal amplitudes.* If we assume that DR is limited by noise on the lower side and the power supply voltage on the upper side, we can write
DR = V pp / 2 Vn _ rms = vVDD 2Vn _ rms
(2)

where, Vpp is the maximum peak-to-peak value of the signal, Vn_rms is the RMS noise voltage, v is the voltage l efficiency ffi i defined d fi d by b Vpp/VDD.

*The

ratio of squared amplitudes is also a common definition

Trond Ytterdal, Department of Electronics and Telecommunication

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Dynamic range (2)

If we assume that matching limits DR on the lower side we can write side,
DR = V pp / 2 (Vos ) = vVDD 2 (Vos )
(3)

where is a yield parameter and (Vos) is the standard deviation of a critical offset voltage in the circuit. We observe for both ( (2) ) and (3) ( ) that DR scales with VDD and v For the rest of the talk we assume that DR is limited by noise on the lower side
23 Trond Ytterdal, Department of Electronics and Telecommunication

Signal-to-noise ratio (SNR)

SNR is defined as the ratio of the signal power to the noise power power. For a sinusoidal signal, signal the maximum SNR given by
SNR =
2 V pp 2 8Vn _ rms

(vVDD ) 2
2 8Vn _ rms

(4)

If we compare (4) with (2), we see that

DR = 2 SNR
(5)

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SNR versus power

VDD IDD i(t)
Gm

Vpp

vout

vin VSS

vout 1/f

Power: P = VDD I DD = VDD

1 1 1 1 2 fq = VDD fV pp C = fV pp C i i v i Here, i is the current efficiency of the transconductor and q/i is the charge transferred from the power supply in one period and. and We have assumed that VSS = 0

SNR:

SNR =

k T 2 V pp = 8 B SNR k BT / C C

2 V pp /8

Only thermal noise is considered.

Combining the two equations we get the power required per pole versus SNR:
P=
Based on [1] and [4]
25

8k BT f SNR i v

(6)

Trond Ytterdal, Department of Electronics and Telecommunication

Theoretical FOM
Rewriting (6) in terms of FOM:
P 8k BT P 4 k BT = = 2 f SNR i v i v f DR 4k T FOM = B i v

Ideal world (v = i = 1):

FOM i = 4k BT
(7)

Hence, H one i important question i becomes: b How does i and v depend on technology?
26 Trond Ytterdal, Department of Electronics and Telecommunication

FOMs based on measurements

FOMs calculated based on measured performance of CMOS circuits are always larger than values obtained using (7) due to one or more of the following:
DR limited by distortion Additional noise sources (e.g. flicker noise) Clock power in switched-capacitor circuits Poor current efficiency of MOS transistors (it is even bi dependent) bias d d t) Parasitic capacitances Matching requirements
Smaller mismatch => larger dimensions => larger parasitic capacitors

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Reported FOMs for ADCs

1.0E+14

2 EN O B Fs FM = Pdiss
Philips ISSCC04

Fig gure of merit t FM [Convers sions/J]

1.0E+13

State-of-the-art 2004

Balmelli ISSCC04 Moyal ISSCC03 Miyazaki ISSCC02 Kwak (97)

1997 1998 1999 2000 2001 2002 2003 2004 Selection from Walden

Gaggl, ISSCC04

This design(03)

Bjrnsen ESSCIRC05[5]
Kelly, ISSCC01 nAD12110-18(03) AD9245(03) H Hernes ISSCC04 nAD10120-13(03)

1.0E+12

Philips ISSCC03 Kulhalli ISSCC02

1.0E+11

Siragusa ISSCC04

1.0E+10

1 MHz

10 MHz

Conversion Rate [Sample/s]

100 MHz

1 GHz

From [5]
28 Trond Ytterdal, Department of Electronics and Telecommunication

Voltage efficiency (v)

Assume that
V pp = VDD 2Vdsat d t
0.30

65nm
0.25

90nm 0.13um

where Vdsat is the saturation voltage of our transistors To keep v unchanged when we scale down technology, Vdsat must be scaled down at the same rate as VDD.

0.20

Vdsatt [V]

0.15

0.10

0.05

0.00 -0.6

-0.4

-0.2

0.2

0.4

0.6

Veff [V]

Not possible to scale Vdsat much lower than 75mV

v expected to decrease FOM degrades

29 Trond Ytterdal, Department of Electronics and Telecommunication

Current efficiency (i)

Assuming CMOS implementation:
The gain bandwidth (GBW) product of a single stage OTA is given by
GBW = gm 2C

(8)

Here gm is the transconductance of the input transistor and C is the load capacitance. Writing the square of the noise RMS voltages as: k BT 2 , Vn _ rms = C Inserting this equation in (2), (2) solving for C and inserting in (8) yields
GBW = g m (vVDD ) 2 8k BT DR
2

(9)

Hence, if DR and gm is kept constant, the speed of the circuit decreases with the square of the supply voltage.

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Scenario 1: Dividing VDD by 2

while keeping GBW and DR:
To keep it simple, assume that v does not change. From (9) we note that to keep GBW when supply voltage is reduced by a factor of 2, gm has to be increased by a factor of 4. It is common to change the W/L ratio and the drain current by th same relative the l ti amount t in i order d to t keep k Veff unchanged h d (adding devices in parallel). Hence, to increase gm by a factor of 4, , bias current and W/L are increased by y a factor of 4. If we assume that all stages of the amplifier are scaled in the same way, the current consumption will be increased by a factor of four. four

Power consumption doubles i decreases FOM degrades Downscaling will not help

31

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Scenario 2: Increasing speed (1)

35

while keeping DR and VDD:

Assume that the frequency of the first non-dominant pole is given by (1) and that phase margin requirements forces a fixed ratio between fT and GBW . Assume that the required speed eed is i such h that th t we e have h e to t push the transistor deep into strong g inversion.
Id [A]
gm /ID [1/V]

Minimum gate length; W /L = 5; V ds = 1V

30 25 20 15 10 5 0 1.0E-12

90nm 0.13um 0.18um 0.25um

1.0E-10

1.0E-08

1.0E-06

1.0E-04

1.0E-02

Drain current [A]

2.5E-04

Minimum gate length, same W /L V ds = 1/2V DD

2.0E-04

1.5E-04

1.0E-04

5.0E-05

90nm 130nm 180nm

i decreases FOM degrades g Downscaling will probably help

32

0.0E+00 1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

f T [Hz]

fTmax@90nm

Trond Ytterdal, Department of Electronics and Telecommunication

Scenario 2: Increasing speed (2)

Watch out for gain degradation when increasing speed If speed increase is y increasing g obtained by Veff, gain will decrease
gm /gds
70 60 50 40 30 20 10 0 1.E-10

Minimum gate length, length same W /L V ds = 1/2V DD

65 nm 90 nm 0.13 um 0.18 um

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

i decreases FOM degrades Downscaling will not help

Drain current [A]

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Maximizing FOM
Some guidelines for maximizing FOM in nanoscale CMOS circuits: Circuit level:
Maximize v by using as low Veff ff as possible Identify fTmax in your technology. Stay well below this frequency to maximize i * Use U as hi high h supply l voltage lt as possible ibl (maybe ( b even higher than allowed by the foundry)

Architecture level:
Avoid high gain requirements (use, for example, gain calibration) ) Go to interleaved architectures if speed requirements cause you to move dangerously close to fTmax*
*or
34

switch to a finer technology

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Summary
Back to near constant voltage scaling (at least for a while) Back to near constant voltage scaling
Reliability issues: Have to verify circuits versus age

Speed of transistors SNR/DR Mismatch Linearity Potential for FOM improvement in some circuits by scaling down technology*
*One

example is ADCs where transistors are biased in regions of low current efficiency
35 Trond Ytterdal, Department of Electronics and Telecommunication

List of symbols
Parameter Agate Cgs Cgd Cdb cox Cox f gm gds Id kB L Lmin Gate area coxW/L Gate-source capacitance Gate-drain capacitance Drain-bulk capacitance Oxide capacitance per gate area O id capacitance Oxide it Frequency Transconductance Channel conductance Drain current Boltzmanns l constant Gate length Minimum g gate length g Description Parameter n T tox VDD Vds Veff Vgs vs VT W Mobility Subthreshold ideality factor Absolute temperature Oxide thickness Supply voltage Drain-source voltage Vgs VT Gate-source voltage Saturation velocity Threshold voltage Gate width Description

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References
[1] E.A. Vittoz, Low Power Design: Ways to Approach the Limits, SolidState Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC, pp 14 pp. 14-18, 18 Feb Feb. 1994. 1994 [2] K. Bult, Analog Design in Deep Sub-Micron CMOS, in Proc. ESSCIRC 2000, pp. 11-17. [3] A. Annema et al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. of Solid-State Circuits, vol. 40, no. 1, Jan. 2005. [4] E.A. E A Vittoz, Vittoz Low Low-power power Low Low-Voltage Voltage Limitations and Prospects in Analog Design, in Analog Circuit Design, Editors R.S. van de Plaasche, W.M.C. Sansen, and J.H. Huijsing, Kluwer Academic Publishers, 1994. [5] J. Bjrnsen, . Moldsvor, T. Sther, T. Ytterdal, A 220mW 14b 40MSPS Gain Calibrated Pipelined ADC, in Proc. European Solid-State Circuits Conference f (ESSCIRC) ( ) 2005, Grenoble, Sept. p 12-14, pp pp. 165-168, 2005.

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