Welcome to DCIS 2009

On behalf of the Organizing and the Steering Committee, we have the great pleasure in welcoming all of
you to the Design of Circuits and Integrated Systems Conference, DCIS 2009. This is the 23th DCIS.
The Conference is being held in the old Building of the Universidad de Zaragoza, the Paraninfo. This
Building is very conveniently located in the centre of the city of Zaragoza.

The Program Chairs and the Program Committee have prepared a rich and very interesting program
following the same scheme of previous conferences. Each day of the conference a plenary session is
scheduled. This year we have invited one academic researcher, Wouter Serdijn from TUDelft and two
industry researches Andreia Cathelin from ST microelectronics and José Ramón García from Bosh
Siemens Hausgeräte.

This Year the conference has been affected by the world economic crisis. Less than one hundred papers
have been presented, but the quality of all of them is very high. The blind reviewers have given high
scores to almost all of them, and the Steering Committee has rejected very few papers.

Because of the economic crisis, the Organizing Committee have done a great effort to keep the inscription
fees low and negotiating very low prices with the recommended hotels.

Last year a World Exhibition took place in Zaragoza. The city has changed its urban panorama. New
bridges over the Ebro river, new airport terminal and new river sides parks and terraces are
infrastructures that have left the World Expo in the city.

The Organising Committee wishes to the conference attendants a fruitful work in the DCIS 2009 and a
good and enjoyable stay in Zaragoza.

Armando Roy Yarza

General Chair
 Program
Schedule Wednesday, Nov. 18 Thursday, Nov. 19 Friday, Nov. 20

8:00 – 9:00 Registration

9:00 – 9:30 Opening Session Invited Talk.: Wouter Serdijn

Invited Talk.: Andreia Cathelin
(Delft University of Technology,
9:30 – 10:00 (STMicroelectronics, Grenoble)
Invited Talk.: José Ramón García The Netherlands)
(BS Home Appliances, Zaragoza)
10:00 – 10:30 Break Coffee Break
 RF IC Design (I)  Analog & Mixed-Signal IC Design (I)  Analog & Mixed-Signal IC Design (III)
10:30 – 12:00  Embedded Design & SoC  MEMs  System Design Methods
 Industrial Applications  Failure Analysis & Reliability  Digital Signal Processing
12:00 – 12:15 Break
Coffee Break Coffee Break
12:15 – 12:30  Reconfigurable Computing & Digital IC
Design
 RF IC Design (II)  Analog & Mixed-Signal IC Design (II)  HW-SW Codesign
12:30 – 13:30  Modelling, Simulation and Synthesis  Bioinspired Systems & Integrated  Smart Objects & Wireless Applications
Techniques (I) Sensors
13:30 – 14:00  Programmable Devices and Systems  Vision & Image Processing Closing Remarks

14:00 – 16:00 Lunch Lunch Lunch

 Low Power Design
 Communications Systems
 Modelling, Simulation and Synthesis
16:00 – 17:30 Techniques (II)
 Analog-Digital Interface Design
 Defect & Fault Tolerance Techniques
 Testability & Test Techniques
18:00 Welcome Reception Social Event & Gala Dinner
 Openning Session

Opening Session.
Chaired by Armando Roy

Invited Talk:
Chaired by Armando Roy

Power Converters for Induction Cookers

José Ramón García

(BSH Bosch und Siemens Hausgeräte GmbH)

Induction cookers market is growing very fast. Power electronics plays an important role in this field. The
principles of induction cookers and the market evolution is discussed. A comparison between the most
succesfull topologies and controls is shown. Trends in electronic developments for this field is analysed.

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 RF IC Design I
Chaired by José M. de la Rosa (IMSE-CNM,CSIC) and Arturo Mediano (U. Zaragoza)

1. A DUAL-GAIN LNA WITH INTEGRATED ANTENNA SENSOR FOR HIGH SENSITIVITY APPLICATIONS
Aitor Juanicorena, Unai Alvarado, Guillermo Bistué, Joaquín De Nó, Juan Meléndez
• This paper presents a dual-gain LNA with integrated antenna sensor for GPS and GALILEO navigation systems. The integrated sensor detects if the receiver
antenna is either active or passive and generates either a control voltage, which can directly drive the gain switching stage of the LNA, or the signal to be sent to the
DSP in order the gain to be selected in the digital domain. The amplifier has been fabricated in a standard 0.35 μm SiGe BiCMOS process and consumes 8 mA from
a 3 V supply. It provides a power gain of 18 dB and a noise figure of 3.3 dB for the high gain mode of operation. A measured -11 dBm IIP3 makes this LNA suitable
for high sensitivity applications such as Global Navigation Satellite Systems (GNSS).

2. A MULTIBAND LNA WITH SWITCHED LOADS AND WIDEBAND INPUT IMPEDANCE MATCHING
Gustavo Pérez Ruiz, Sunil L. Khemchandani, Roberto Díaz Ortega, Rubén Pulido Medina, Dailos Ramos Valido, Javier Del Pino Suárez
• A fully-integrated multiband low noise amplifier topology is proposed. This configuration combines a wideband input impedance with two switched resonant circuits in
the load of the amplifier. The use of reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. The proposed multiband
LNA is implemented in BiCMOS 0.35 µm process. Simulations, including technology parasitics, show a maximum gain of 16 and 12 dB at 1.8 and 2.4 GHz
respectively. The minimum NF for both frequencies are 2.5 and 3.4 dB, and the input IP3 at 1.5 GHz is 1.5 dBm. The chip size is 0.771 × 0.848 mm2 and the total
power consumption is 16 mW without the output buffer at the DC voltage supply of 3.3 V

3. A LOW COST INDUCTORLESS LOW NOISE AMPLIFIER FOR ISM BANDS

Pedro Jesus, Miguel Martins, Jorge Fernandes
• In this paper, we present a low-cost wideband inductorless low noise amplifier for applications operating in the ISM sub-GHz bands. The low cost is pursued by using
a 0.35 µm CMOS technology without RF options, and by using an inductorless circuit topology which leads to a final active area of 150×120 µm2 for the complete
LNA, which is in the order of the area of a single inductor. The LNA exhibits a voltage gain of 15 dB, a S11 below -10dB and a noise figure under 3 dB in a 1 GHz
band. The power consumption is 12.4 mW from a 1.8 V voltage supply.

4. A 2.5 GB/S CMOS TRANSIMPEDANCE AMPLIFIER WITH WIDE INPUT DYNAMIC RANGE
Francisco Aznar, Wolfgang Gaberl, Horst Zimmermann, Santiago Celma, Belen Calvo
• A new transimpedance amplifier (TIA) for 2.5 Gbit/s optical communications is presented in this paper. The conventional structure for the TIA with an inverting voltage
amplifier and a feedback resistor is improved, incorporating a new technique to prevent the TIA saturation at high input currents, enhancing the input dynamic range.
Post-layout results show an optical sensitivity of -30 dBm for a BER = 10-12 and a maximum input current of 1 mApp, what leads to an optical power dynamic range
above 27 dB. The power consumption, realized in a standard 90 nm CMOS process, is only 4.3 mW with single supply voltage of 1 V.

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 Embedded Design & SoC
Chaired by by José Silva Matos (U. Porto) and Luis A. Barragán (U. Zaragoza)

1. AN INTEGRATED SOLUTION FOR OFDM NARROW BAND PLC COMMUNICATION SYSTEM

Santiago Miguel, Alfredo Sanz, J.Ignacio Garcia, Pedro Estopiñan
• This paper describes the process of evolution of PRIME from the early definition state to the first implementation of a SoC solution. PRIME is the Draft Standard for
Power-line-Related Intelligent Metering Evolution. It is a complete draft standard for a new OFDM-based power line technol-ogy for the provision of all kinds of Smart
Grid services over electricity distribution networks. Both PHY and MAC layers according to IEEE conventions, plus a Convergence layer, are described in the
standard. PRIME is the base line technology of the new Open Meter project supported by the larger European utilities.

2. DESIGN OF AN INTEGRATED LIQUID LENS FOR DRIVER A VISION SYSTEM OF AN ENDOSCOPIC CAPSULE
Lluís Freixas, Oscar Alonso, Angel Dieguez
• The paper describes the electronics used to drive a liquid lens for a vision system of an endoscopic capsule. The liquid lens ARCTIC 416 works with high voltage
signals. For this reason the driver integrates a boost converter to generate a supply voltage of 50 V from 3.3 V. An H-Bridge is the main block of the driver to drive the
liquid lens. The H-Bridge transistors are controlled with specific level-shifters. An integrated 5 V Dickson charge pump is integrated to feed the level-shifters acting on
the LV part of the H-bridge. Voltages to drive the level-shifters acting on the HV part of the H-Bridge are obtained from the boost. An ASIC has been fabricated to test
the liquid lens driver designed.

3. ENABLING ACTIVE LOCOMOTION IN CAPSULAR ENDOSCOPY

Oscar Alonso, Lluís Freixas, Angel Diéguez
• It is described the architecture of the electronics for the control of a wireless endoscopic capsule with locomotive capabilities and advanced sensing and actuating
functions. Special emphasis is done to the description of the driver used for locomotion, which is the most innovative element in the capsule.

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 Industrial Applications
Chaired by Abelardo Martínez Iturbe (U. Zaragoza) and Estanislao Oyarbide (U. Zaragoza)

1. ELECTRONIC DEVICE FOR CONTINUOUS CONTROLLING OF FRYING COOKING PROCESSES

Miquel Tarzan-Lorente, Joan Ceravalls, Ines Fernandez, Jose Bosch, Jose María Gómez, Antonio Pardo
• Cooking temperature is related with the prevention of foodborne illness and also with the appetizing look and taste of food.
In this paper we present a system to continuous monitoring and controlling cooking processes for both safety and consumer satisfaction. The system is based on two
thermocouples for measuring temperatures, a variable resistance to measure food thickness, and an algorithm to estimate next steps of the cooking process. The
actual development comprises a system for the cooking control of food in pans. The system can be used continuously during the cooking process and it implements
RF communications for the transmission of information to a central system. The aims of the development are to provide: Food safety to guarantee suitable and
secure cooking temperatures, process control to assure the costumer desired point of cooking, electronic recipes for reproducibility.

2. VERSATILE POWER ELECTRONICS PROTOTYPING TEST-BENCH: APPLICATION TO DOMESTIC INDUCTION

HEATING
Óscar Lucía, José Miguel Burdío, Jesús Acero, Diego Puyal, Ignacio Millán, Sergio Llorente
• Domestic induction heating is a promising technology which requires versatile power electronics converters. Most of the appliances are based on a DC-link inverter
which supplies currents between 20 kHz and 100 kHz to an inductor, which heats up the pan by means of Eddy Currents. The design of the converter must be carried
out considering the output power, the amount and nature of loads, and the desired cost, size and efficiency. As a consequence, different power converter topologies
must be evaluated in order to obtain the most suitable implementation.
The development of several ad-hoc prototypes can be a very time-consuming task and lead to increased product developing times. In this paper, a versatile
prototyping architecture is proposed. It is based on modular IGBT/MOSFET driver boards controlled through a Field Programmable Gate Array based versatile Digital
Pulse Width Modulator.

3. DESIGN AND TEST OF A LIMB SENSOR FOR THE SO/PHI INSTRUMENT

Ana Masriera, Jose Bosch, Atila Herms, Francisco Palacio, Manuel Lopez, Michael Sigwarth, Johann Hirzberger, José María Gómez Cama
• Extremely stable pointing is required for images on Polarimetric Imagers to obtain accurate measures using a telescope. An Image Stabilization System (ISS) is
installed in a solar telescope to stabilize the image on the focal plane. Part of this System consists of a Limb Sensor based on a Quad Cell photodiode. The
generated photocurrent in each of the four sections of the photodiode is converted to voltage and processed in a microcontroller with 16 bits ADCs. This paper
reports the implementation of the prototype and obtained measurements of noise and position detection that have been taken using an optic bench.

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 RF IC Design II

Chaired by José Machado da Silva (FEUP/INESC Porto) and J.M. López Villegas (U. Barcelona)

1. A DVB-H RF-VGA BASED ON CURRENT CONVEYORS

Jonathan Arias Perez, Rubén Pulido Medina, Hugo García Vázquez, Sunil Lalchand Khemchandani, Javier Del Pino Suárez, Antonio
Hernández Ballester
• A DVB-H RF-VGA implemented in a low-cost Si-Ge 0.35 μm process is presented. It utilizes current conveyors as building blocks. The main features are an easy gain
control over wide ranges (0 to 18 dB) and minimal power consumption, only 1.7mA from a 1.5 voltage supply. The input impedance is controlled by a bias current,
which means total absence of passive elements. Chip dimensions are 62 x 44 μm2.

2. DESIGN OF A CURRENT-MODE CLASS-D POWER AMPLIFIER IN RF-CMOS

Daniel Oliveira, Cândido Duarte, Vítor Grade Tavares, Pedro Guedes De Oliveira
• The present paper addresses the implementation of a radio-frequency power amplifier operating in current-mode class-D. In particular, this paper focuses the
technical issues concerning the design of a fully-integrated version of the amplifier in a RF-CMOS technology. It is demonstrated that the parasitic series resistance of
an integrated load inductor has great impact in the drain efficiency value. In order to compensate for this effect, the reduction of the load network QL has been
adopted. A RF- CMCD power amplifier has been designed in 90-nm CMOS including all the inductors on-chip. Simulation results demonstrate drain-efficiency values
over 76%, for up to 16-dBm output power at 2.45-GHz operation frequency.

3. DESIGN CONSIDERATIONS OF INTEGRATED INDUCTORS FOR HIGH PERFORMANCE RF CMOS POWER

AMPLIFIERS
Erik Fernández, Roc Berenger, Joaquín De No, Joseba García, Héctor Solar
• This paper presents the design rules of high performance integrated inductors intended for radio-frequency (RF) power amplifiers (PA) in standard silicon processes.
Following these rules several integrated inductors have been fabricated in a standard 0.18 um CMOS process achieving quality factors (Qs) of 13 at 14 GHz.
Furthermore, in order to validate the proposed design rules, the designed inductors have been implemented in a 0.5 W fully integrated CMOS PA. The measured
results show a power added efficiency (PAE) of 32 %, a 1 dB compression point (P1dB) of 23 dBm and a saturated output power (PSAT) of 27.3 dBm. These results
are among the best ones for fully integrated linear PAs.

4. LOW POWER CONSUMPTION MIXER BASED ON CURRENT CONVEYOR FOR WIRELESS SYSTEMS
Roberto Díaz Ortega, Albano Castillo García, Hugo García Vazquez, Dailos Ramos Valido, Sunil Lalchand Khemchandani, Javier Del Pino
Suárez
• This paper presents a design of a low power consumption mixer based on a switching quad and a transimpedance current conveyor stage. This mixer has
been implemented in a 0.35 µm CMOS process. The whole mixer draws 580 µA from the ±1.65V voltage supply, with a total gain of 23.2 dB, a noise figure around
31.26 dB and an IIP3 of 0 dBm. The developed mixer is suitable for the most usual wireless communications standards like DVB-H,WiFi, Bluetooth etc…
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 Modelling, Simulation and Synthesis
Techniques I
Chaired by Alkis Hatzopoulos (Aristotle Univ. of Thessaloniki) and Carlos Bernal (U. Zaragoza)

1. A NEW RECONFIGURABLE CASCADE SD MODULATOR ARCHITECTURE WITH INTER-STAGE RESONATION

AND NO DIGITAL CANCELLATION LOGIC
Alonso Morgado, J. Gerardo García, Rocío Del Río, José M. De La Rosa
• This paper presents a new two-stage cascade SD modulator architecture that uses inter-stage resonation to increase its effective resolution as compared to
conventional cascades and avoids the need for digital filtering in the error cancellation logic. The combination of these two strategies, together with the use of unity
signal transfer function in all stages, make the presented modulator highly tolerant to noise leakages, very robust to non-linearities and mismatches of the loop-filter
circuitry, and especially suited for low-voltage implementations at low oversampling ratios. In addition, the use of loop filters based on Forward-Euler integrators,
instead of Backward-Euler integrators, simplifies the switched-capacitor implementation of the resonation and makes the presented architecture very suited for
reconfigurable multi-standard applications. Besides, several practical details about the implementation of the modulator are given throughout the paper. As an
illustration, a Beyond-3G case study is shown to demonstrate the benefits of the presented approach.

2. TAKING INTO ACCOUNT SWITCHING EVENTS IN FIXED TIME-STEP VHDL SIMULATION OF POWER
ELECTRONIC CIRCUITS
Luis A. Barragán, Denis Navarro, Isidro Urriza, José I. Artigas, Óscar Lucía, José M. Burdío
• Digital controllers implemented in an FPGA for switching power converters are becoming an important alternative to the traditional analog solutions. It is assumed that
the digital controller is described using a hardware description language and that the simulation as a whole of the digital controller with the power electronic circuit is
done in an HDL simulator. This work shows how to take into account switching instants in a fixed time-step VHDL simulation of the power electronic converter. It is
analyzed how this strategy allows increasing the simulation time step while maintaining accuracy.

3. ELECTRODE CONTACT IMPEDANCE MEASUREMENT IN THROUGH-THE-EARTH COMMUNICATIONS

Vanessa Bataller, Antonio Muñoz, Pilar Molina, Arturo Mediano, José Antonio Cuchí, José Luis Villarroel
• In order to improve the communication range of Through-The-Earth (TTE) radio using electrodes, the load impedance seen by power stage must be minimized.
Although this impedance depends on the wires, contact electrode and earth path between the electrodes, we cannot act over the last component. This paper
presents a method to measure the contact electrode impedance, applying it with several electrodes in different terrains. Thanks to these measurements circuital
models for contact electrodes impedances are obtained.

4. VHDL-AMS DESCRIPTION OF A BIOSIGNAL MONITOR INTEGRATED CIRCUIT

Gines Domenech-Asensi, Ramon Ruiz-Merino, Jose Angel Diaz-Madrid, Juan Zapata-Perez
• Acquisition, transfer and processing of biosignals are the main tasks of any biomedical system. Generally, these systems require high demanding specifications in
several matters (security, robustness, noise tolerance, low power, etc.), which are magnified when trying to design portable systems for monitoring tasks in out-of-
hospital environments. Designing such circuits, devoted to the acquisition and digital processing of biosignals, is a challenging task which requires a combination of
the most advanced digital techniques and the analog expertise knowledge. However, in such circuits the analog part represents only a portion of the total die, but it is
a bottleneck which dominates the total design time. To reduce the simulation time it becomes necessary to use high level models with a good trade off between
accuracy and simulation speed. In this paper, we propose the use of VHDL-AMS as a framework to develop the high level synthesis of a microelectronic circuit used
for monitoring biosignals. The circuit is described and simulated using a top-down approach which combines pure behavioural and structural descriptions of
subcircuits and devices.
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 Programable Devices and Systems
Chaired by Teresa Riesgo (U. Politécnica de Madrid) and José Ignacio Artigas (U. Zaragoza)

1. A PROGRAMMABLE DEVICE FOR CHARACTERISING A POLYMERIC PYROELECTRIC SENSOR

Yamani Dalila, Kendil Djamel, Meraghni Abd El Hamid, Bousbiat Essaid
• Pyroelectric detection is based on the absorption of an incident radiation which produces a temperature rise in the sensitive element and modifies its internal dipolar
moment by inferring an electrical signal proportional to the temperature variation. Performance of a pyroelectric sensor depends on its pyroelectric coefficient.
In practice, several techniques are used to estimate this coefficient and the most wide-spread one is the optical technique, where the sensor is excited by an external
thermal radiation chopped at a fixed frequency; the pyroelectric coefficient is proportional to the pyroelectric response measured and which depends on the amount of
thermal radiation absorbed by the sensor’s frontal electrode. In reality, this technique presents the disadvantage of radiation loss during transfer from source to
sensor and then the pyroelectric coefficient value measured will not be very exact.
In this paper, we present another way to measure the pyroelectric coefficient; it consists of a dielectric absorption technique where the sensor is excited directly by
applying a relatively high frequency electrical field during a short period of times. We obtain the pyroelectric coefficient by measuring the sensor response. The
originality of our work is the programmable device that we designed to generate the excitement signal, it is based on an FPGA programmable circuit. We opted for
this solution in the aim of integrating another measurement and signal conditioning stages in the same circuit.

2. FPGA EMBEDDED SOFT-CORE PROCESSOR IMPLEMENTATION OF A DIGITAL CONTROLLER FOR A DC-DC

CONVERTER
Isidro Urriza, Luis A. Barragán, Denis Navarro, José I. Artigas, Óscar Lucía, Óscar Jiménez
• This paper presents the implementation of a digital controller in an FPGA for a switching power converter. The design consists of a MicroBlaze embedded soft-core
processor that executes the control algorithm, and a customized peripheral that generates the PWM and drives the ADC. This customized peripheral is described
using a Hardware Description Language (VHDL). The control algorithm is written in C and uses floating point math what makes straightforward the implementation
with regard to fixed-point implementations. Numerical format conversions must be done since PWM and ADC work with unsigned integer data. These format
conversions are performed in different ways and its impact on control code execution time and FPGA resources utilization is analyzed. The closed loop system as a
whole is simulated and the firmware debugged. Finally, the digital circuit is implemented in the FPGA, and the simulations are experimentally verified.

3. INTELLECTUAL PROPERTY PROTECTION OF ΜP CORES

Luis Parrilla, Encarnación Castillo, Antonio García, Elías Todorovich, Daniel González, Antonio Lloris
• Microprocessor and microcontroller cores are widely used in digital design. In this paper, a new protection scheme for intellectual protection of microprocessor cores
is presented. The procedure can perform this task in two ways: the hosting of a digital signature using watermarking techniques, that allows claiming authorship
rights; and the introduction of additional hardware limiting the functionality of the core until the correct activation code is entered. This last feature enables the
distribution of cores in “demo” mode. The protection method, named µIPP@HDL provides a robust protection system, while maintaining low overhead and a
reasonable area increase, as experimental results show.

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 Low Power Design
Chaired by Manuel Delgado Restituto (U. Sevilla)
1. A NOVEL SWITCHED CAPACITOR FREQUENCY TUNING TECHNIQUE FOR CONTINUOUS-TIME GM-C FILTERS
Trinidad Sanchez Rodriguez, Fernando Muñoz Chavero, Antonio Torralba Silgado, Ramon Gonzalez Carvajal
A novel approach for the automatic frequency tuning of Continuous Time Filters is presented. This approach is based on a switched capacitor
circuit and only needs three capacitors, some switches and a replica transconductor to adjust the pole frequency of the filter. Despite the
simplicity of the scheme, the accuracy of the proposed system is under 1% of frequency error. To evaluate the idea a version of the circuit
has been designed in a 0.5 µm CMOS technology with a 3.3 V power supply and simulation results are provided.

2. RAIL-TO-RAIL CLASS AB CMOS TUNABLE TRANSCONDUCTOR WITH -52DB IM3 AT 1MHZ

Lucia Acosta, Antonio Lopez-Martin, Ramon G. Carvajal, Jaime Ramirez-Angulo
• A novel CMOS tunable transconductor is presented. The circuit operates in class AB hence featuring power efficiency. The internal feedback employed and the use
of a linearized triode transistor for voltage-to-current conversion allows achieving high linearity. Rail-to-rail input range is obtained by using floating-gate transistors.
Measurement results for a test chip prototype in a 0.5um standard CMOS process show an IM3 of -52.13dB at 1MHz for a 2Vpp input and a static power
consumption of 2.2mW.

3. EFFECT OF THE CAPACITORS IN THE INPUT IMPEDANCE OF UHF RFID PASSIVE TAGS
Andoni Beriain, Alexander Vaz, Ivan Rebollo, Alejandro Asensio, Iñigo Gutiérrez
• The voltage multiplier is one of the key factors in the range definition of UHF RFID passive systems. The effect of the voltage multiplier input impedance in the system
range is presented. Different impedance models found in the bibliography are shown and evaluated. The effect in the input impedance of different capacitor-to-
substrate in the voltage multiplier is simulated. The effect of the capacitor technology/size selection in the input impedance is demonstrated and is used to suggest
the use capacitors with low capacitor-to-substrate looses in order to improve the system range.

4. TUNABLE CLASS AB CMOS GM-C CHANNEL FILTER FOR A BLUETOOTH ZERO-IF RECEIVER
Coro Garcia-Alberdi, Lucia Acosta, Antonio Lopez-Martin, Jaime Ramirez-Angulo, Ramon G. Carvajal
• A novel tunable third order low-pass Gm-C filter is introduced. Programmable transconductors operating in class AB have been used for its implementation hence
featuring low quiescent power consumption. The operation in class AB is achieved using quasi-floating gate transistors. This filter is suitable for channel filtering of
highly integrated, ultra low power wireless receivers e.g. for Bluetooth and Zigbee. Measurement results for a test chip prototype in a low-cost 0.5um standard CMOS
process are presented.

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 Modelling, Simulation and Synthesis
Techniques II
Chaired by Linda Milor (Georgia Tech.)

1. COMPLETE OPTIMAL EDP TRADEOFF CURVE BASED IN GATE SIZING, VDD AND VTH TUNING AND LINEAR
PROGRAMMING
J. Sosa, Saeid Nooshabadi, Juan-A. Montiel-Nelson, H. Navarro, J.C. Garcia-Montesdeoca
• In this paper, we present a novel methodology to obtain the complete tradeoff curve of Energy Delay Product (EDP). It is based on a iterative algorithm that first
obtain the minimum EDP design point and then traces the complete optimal tradeoff curve. We apply our methodology to ISCAS'99 benchmark circuits. The target
technology is the commercial standard cell library of 65nm from ST Microelectronics. Results and comparisons demonstrate the usefulness of our methodology.

2. EXPERIMENTAL ANALYSIS OF CMOS SHORT-CHANNEL GATE ENCLOSED TRANSISTORS

Paula López Martínez, Johann Hauer, Beatriz Blanco Filgueira, Diego Cabello Ferrer
• The outstanding benefits of standard deep submicron CMOS technologies for the design of radiation tolerant devices can be further exploited by means of the use of
special layout styles, such as the gate-enclosed transistors. This work constitutes a study of the impact of technology downscaling on the performance of this type of
devices, particularly the threshold voltage roll-off due to short-channel effects and the drain-induced barrier lowering. Theoretical predictions have been validated with
experimental data in a commercial CMOS process.

3. A QUICK AND EFFICIENT CAPACITANCE EXTRACTION METHOD FOR ANALYTICAL DELAY MODELS IN
NANOMETER CMOS ICS
Salvador Barceló, José Luis Rosselló, Jaume Segura
• With CMOS features shrinking down to the nanometer regime and the increasing impact of parameter variations, accurate delay estimation is becoming a complex
task in design closure and test planning. Given the complexity of today ICs, critical path determination and accurate delay estimation requires precise models that
capture both the device and interconnect characteristics. These models must also yield a quick delay computation to fulfill the design-cycle timing. Accurate analytical
models have been shown to be a valid alternative for delay estimation, and most of the published techniques include input-output gate capacitance as an input
parameter. Given the voltage dependence of such capacitances (due to the logic gate contribution), accurate parasitic capacitance estimation is key for accurate
delay estimation. Such a calculation must provide an effective value whose computation method does not add on the overall delay estimation. In this work we present
a very simple and effective method to extract the effective gate input and output capacitance values for any component of the CMOS library. These capacitances are
computed from electrical simulations, and are calculated once for each library component. Results from a 130nm and 90nm technologies show the validity and
affectivity of the method.

4. THE EKV CMOS EQUATIONS AS A COMPACT MODEL FOR SIMULATING A VARIETY OF FET BASED NANO
DEVICES
Teresa Serrano Gotarredona, Bernabe Linares Barranco, Guillaume Agnus, Vincent Derycke, Jean-Phillipe Bourgoin, Dominique Vuillaume
• In this paper we explore the possibility of using the equations of a well known compact model for CMOS transistors as a parameterized compact model for a variety of
FET based nano-technology devices. This can turn out to be a practical preliminary solution for system level architectural researchers, who could simulate
behaviorally large scale systems, while more physically based models become available for each new device. We have used a four parameter version of the EKV
model equations and verified that fitting errors are similar to those when using them for standard CMOS FET transistors. The model has been used for fitting
measured data from three types of FET nano-technology devices obeying different physics.

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 Testability & Test Techniques

Chaired by Luz Balado (U. Politècnica de Catalunya) and Miquel Roca (U. Illes Balears)

1. PATTERN RECOGNITION METHODS APPLICATION FOR ANALOG CIRCUIT FAULT DETECTION

Dimitrios Konstantinou, Michael Dimopoulos, Dimitris Papakostas, Sotiris Stathis, George Goudelis, Alkis Hatzopoulos
• In this paper analog circuit fault detection using pattern recognition methods is presented. These methods, which include linear and non-linear discrimination of
patterns, are applied here to emergency luminaire circuit testing. The presented methods are based on power supply current (IPS) measurements and may easily be
adapted to test various other analog and mixed-signal systems. Experimental results are presented utilizing several pattern recognition methods. These results
suggest as the most efficient method the Perceptron algorithm combined with a Gaussian Kernel function which offers the highest detectability percentage.

2. ESTIMATION OF RF PA'S’ NONLINEARITIES AFTER CROSS-CORRELATING POWER SUPPLY CURRENT AND

OUTPUT VOLTAGE
Ricardo Veiga, José Machado Da Silva, Pedro Mota
• The present paper describes developments carried-out on estimating 1 dB compression and third-order intercept points after the cross-correlation between dynamic
current and output voltage of radio-frequency power amplifiers. The underlining theory and a circuit that allows implementing this measurement on-chip are
presented. Simulation results, including the analysis of optimum stimuli amplitudes and the effect of noise in estimation accuracy, are presented. These show that
good accuracy can be obtained with relatively simple measurement conditions.

3. DIAGNOSIS OF FULL OPEN DEFECTS IN INTERCONNECT LINES WITH LARGE FAN-OUT

Daniel Arumi, Rosa Rodríguez-Montañés, Joan Figueras
• Failures associated with open defects are common in CMOS technologies. Among open defects, interconnect opens have focused significant effort, since this class
of opens has become more frequent with technology shrinking due to the increasing number of vias/contacts and the replacement of aluminum with copper in metal
interconnections. In this context, the diagnosis of interconnect open defects is important for solving process problems and yield improvement.
In the presence of an interconnect full open defect, the defective line is reported to depend on the parasitic capacitances from neighbouring structures, parasitic
capacitances of the transistor driven by the floating node and the trapped charge. In this work, a diagnosis methodology is proposed considering both, the impact of
neighbouring capacitances and transistor capacitances. Furthermore, an example from a real defective device where the methodology is successfully applied is
presented.

4. VERIFYING ANALOG CIRCUITS BASED ON A DIGITAL SIGNATURE

Alvaro Gomez, Ricard Sanahuja, Luz Balado, Joan Figueras
• The verification of analog circuit specs is a challenging task requiring costly analog AATE equipment and time consuming procedures. The paper presents a low cost
parameter verification method based on the statistical analysis of a digital signature of the Circuit under Test. A CMOS on chip monitor and sampler circuit generates
the digital signature of the CUT. The monitor divides the X-Y plane with non linear boundaries into zones in order to generate a digital output code for each analog
(x,y) location. A metric to be used in golden-defective signature comparison is proposed. The metric is based on the definition of a discrepancy factor and performs
circuit parameter identification via statistical and circuit pre-training methods. The proposed method is applied to the verification of possible deviations of the natural
frequency in a BIQUAD filter implementation. The simulation results show the possibilities the proposal.

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 Invited Talk

Wearable and Implantable Medical Devices

-- towards better monitoring, treatment and care --

Wouter Serdijn
(Delft University of Technology, The Netherlands)

Induction In the design process of wearable and implantable medical devices (WIMDs), such as pacemakers, cochlear implants
and neurostimulators, the trade off between performance and power consumption is a delicate balancing act and yet today’s
devices all fall short on one or more of the following aspects: number of electrodes, ability to detect morphological features of the
incoming signal, ability to generate a variety of impulses in a closed-loop (thus adaptive) fashion, ability to transmit and receive
reliably over a radio-harsh, signal-blocking radio channel, power consumption, and form factor.
Most of these shortcomings originate from the way the current sensor, pulse generator and transceiver electronics, are specified,
designed and tested: in the time or frequency domain; they are therefore successful in the creation and analysis/detection of
artificial signals, such as square and sinusoidal waves as, e.g., occur in various communication systems (e.g., for mobile
telephony, fiber-optic communication, etc.). However, they are less successful in dealing with more natural signals, such as the
non-stationary electrophysiological signals entering WIMDs.
In this presentation we will cover some recent techniques to deal with the acquisition and generation of electrophysiological
signals and to provide reliable communication through the body. We will discuss analog wavelet filters and signal-specific analog-
to-digital converters that preserve the main features of the signal while removing noise and interference. It will be shown how
analog pre- or post-processing can lead to tremendous gains in power efficiency because of the exploitation of analog primitives
for computation..

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 Analog & Mixed-Signal IC Design (I)
Chaired by Antonio López Martín (U. Pública de Navarra) and Manuel Delgado Restituto (U. Sevilla)

1. NOISE PERFORMANCE OF TRANSIMPEDANCE AMPLIFIERS FOR RADIATION DETECTORS

Manuel Silva, Carlos Leitão, Luís Oliveira
• A low noise transimpedance amplifier (TIA) is used in a radiation detector to transform the current pulse produced by a photo-sensitive device into an output voltage
pulse with a specified amplitude and shape. In this survey paper we consider the specifications of a PET (positron emission tomography) system and investigate the
following five TIA circuits: feedback TIA (using an operational amplifier), common-gate TIA, regulated common-gate TIA, TIA with a current pre-amplifier realized
either by a simple (two-transistor) current mirror or by a current-mirror with reduced input impedance. For each circuit we derive the transimpedance function (the
poles of which determine the pulse shaping); we identify the transistor in each circuit that has the dominant noise source, and we obtain closed-form equations for the
rms output noise voltage.
We find that in all five circuits the output noise voltage due to the transistor that dominates the noise production is inversely proportional to the square root of the
transistor transconductance. In the common-gate TIA and in the TIA with a simple current pre-amplifier the transconductance is not free to minimize the noise, since it
is linked to one of the poles of the TIA transimpedance function. In the other three circuits, the same dominant noise contribution is obtained if the same maximum
transconductance value is considered.

2. A NOVEL CMOS TRIODE TRANSCONDUCTOR BASED ON CURRENT DIVISION

José Mª Algueta Miguel, Carlos A. De La Cruz Blas, Antonio J. López-Martín
• In this paper a compact transconductor based on transistors operating in the triode region is presented. A novel V-I conversion stage made up of current dividers is
proposed. The circuit allows tunability through a dc current and the transconductance parameter ideally does not depend on W/L ratio of the triode transistors.
Besides, the circuit is simple, occupying a reduced area and featuring low power consumption. Simulation results are presented and analyzed for validating the
proposed technique.

3. RBF CIRCUITS BASED ON DIFFERENTIAL PAIR TRANSCONDUCTANCE APPROXIMATION

Marcio Lucks, Nobuo Oki
• In this paper, we propose new circuits for the implementation of radial basis functions using the transconductance characteristic of CMOS differential pairs. This
approximation is obtained by the subtraction of the output currents of two differential pairs. The functionality of the circuits is demonstrated by SPICE simulation and
by experimental results with breadboard implementation. The results obtained indicate good functionality. A multidimensional version is proposed using the cascading
of unidimensional circuits. These circuits are intended to be applied in the implementation of radial basis function networks.

4. A TUNABLE FLOATING-GATE CMOS TRANSCONDUCTOR BASED ON CURRENT MULTIPLICATION

José Mª Algueta Miguel, Antonio J. López Martín, Jaime Ramírez Angulo, Ramón González Carvajal
• In this paper a novel transconductor based on floating gate techniques that performs current multiplication for tuning is presented. The multiplication is achieved using
transistors operating in weak and moderate inversion together with floating voltage sources implemented conveniently by floating capacitors. Besides, a tuning
scheme is proposed to set the transconductance parameter accurately. The resulting circuit features compactness, low voltage operation, and rail-to-rail input range.
Measurement and simulation results using a 0.5um CMOS technology are presented to confirm all the circuits and strategies proposed.

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 MEMs
Chaired by Arantxa Uranga (U. Autònoma de Barcelona) and María Villarroya Gaudó (U. Zaragoza)

1. A CMOS MEMS VHF ELECTROSTATIC COUPLED FILTER

Joan Giner, Arantxa Uranga, Jaume Verd, Gonzalo Murillo, Eloi Marigó, Francesc Torres, Nuria Barniol, Gabriel Abadal
• This work presents a fully integrated second-order electrostatic coupled filter, built from two clamped-clamped beam resonators. It has been fabricated using a
commercial CMOS technology from Austria Microsystems (AMS 0.35 µm). The electrostatic coupling allows the coupling of the resonators without any physical
coupling element, enabling a tunable bandwidth and center frequency by means of the external biasing voltages after its fabrication. It is demonstrated how this
flexible approach allows us obtaining very narrow bandwidth filters (120 KHz with a 50 MHz center frequency), compared to the mechanical coupling.

2. MONOLITHIC CMOS-MEMS OSCILLATOR IN LINEAR REGIME OPERATION

Carles Pey, Arantxa Uranga, Jaume Verd, Gabriel Abadal, Núria Barniol
• The present paper presents steps and considerations taken into account to design a 26 MHz monolithic CMOS-MEMS
oscillator, using AustriaMicroSystems (AMS) 0.35 μm technology and aiming to minimize the MEMS biasing voltage, improve
phase noise and lower at the same time the power consumption.

3. FEEDBACK-INDUCED PHASE NOISE IN RESONATOR-BASED OSCILLATORS

Javier Malo, José Ignacio Izpura
• When electronic feedback is used around resonant microcantilevers, their native resonance frequency f0 and that of the feedback loop fFB=f0±Δf will differ in general
because the 0º or 360º phase condition aimed in the loop gain uses to have some small phase offset Φε;. This feedback-induced frequency shift Δf, that is static in
constant-gain loops, becomes a frequency noise when the loop gain changes randomly as in oscillating loops by the action of noise on the Automatic Level Control
(ALC) of the loop. The phase offset Φε; allows the ALC to modulate randomly the output frequency around its fFB value while it modulates in the same manner the
feedback factor of the loop to keep constant the output amplitude. This phenomenon is thus an added source of phase noise in resonator-based oscillators,
especially when the signals within the loop are noisy as those giving the instantaneous displacement of small microdevices like resonant MEMS (Micro-Electro-
Mechanical Systems).

4. DESIGN AND IMPLEMENTATION OF A MEMS WIRELESS CAPACITIVE PRESSURE SENSOR

Javier Ramos, Antonio Luque, José M. Quero, José L. Ausín
• In this paper, a MEMS capacitive pressure sensor is designed as a RF capacitor for radio telemetry. The sensor is a variable capacitor composed of two electrodes: a
conductive membrane, which deflects due to pressure difference applied over it, and a fixed electrode. The integration of multiple functionality in MEMS devices,
which will contribute to power saving, is also explored in this paper. The goal of this approach is to maximize the integration level by simplifying the global system
architecture. Experimental results obtained from a discrete RF oscillator prototype validate this approach that opens new alternatives to single-device RF-sensor
designs.

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 Failure Analysis & Reliability

Chaired by Michel Renovell (LIRM) and Linda Milor (Georgia Tech.)

1. CIRCUIT RELIABILITY SIMULATION INCLUDING MOSFET RELATED VARIABILITY AND WEAR-OUT EFFECTS
Javier Martin-Martinez, Rosana Rodriguez, Montse Nafria, Xavier Aymerich
• With the continuous transistor scaling, device mismatch related to intrinsic process variability increases and becomes one of the most important problems to be faced
during circuit design. In addition, gate oxide wear-out (induced by the high electric fields in the device) strongly affects the device reliability and adds a time
dependence to device mismatch. In this work, the impact on circuit functionality of process variability and gate oxide degradation is studied. Firstly, CMOS inverters
have been electrically stressed to experimentally study the effect of the gate oxide damage on the NMOS and PMOS transistor characteristics and circuit response.
Secondly, a methodology based on combined SPICE and Monte Carlo simulations is presented to analyse the time-dependent variability at device and circuit levels,
which has allowed to reproduce the experimental data. Finally, using the proposed methodology, the influence of the process variability and gate oxide wear-out on
the functionality of an amplifier circuit was investigated.

2. STATIC-NOISE MARGIN ANALYSIS DURING READ OPERATION OF 6T SRAM CELLS

Bartomeu Alorda, Gabriel Torrens, Sebastia Bota, Jaume Segura
• SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read
operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM
during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word- and bit-
line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing current leakage, as opposed to current methods
that improve cell read stability at the cost of leakage increase.

3. DATA RETENTION FAILURES IN SRAMS CAUSED BY LOWERING THE POWER SUPPLY VOLTAGE
Elena Ioana Vatajelu, Joan Figueras
• With the shift towards nanometric technologies the need of smaller and power efficient operating memories is very stringent. In order to achieve power efficient
operation the leakage has to be substantially reduced and this can be achieved by lowering the supply voltage. In these conditions, operating under process-voltage-
temperature (PVT) variations, a non-defective memory in standby can experience failures. The paper analysis the impact of reducing the supply voltage on the
robustness of a 6-transistors Static Random Access Memory (6T-SRAM). The Static Noise Margin (SNM) is evaluated analytically and compared with HSPICE
simulations for 65nm and 45nm Berkeley Predictive Technology Models (BPTM). The impact of process and temperature variations is evaluated using corner and
Monte Carlo analysis. Our results show that a well designed non-defective, robust memory, operating at low supply voltage, under process and temperature
variations can experience failures during the memorization phase of the device.

4. ANALYSIS OF ON CHIP DETECTION OF VIA WEAROUT

Fahad Ahmed, Linda Milor
• This project aims to detect the onset of chip failure due to via voiding through monitoring the delays of paths in a chip. The proposed method relates the probability of
failure of individual vias to an increase in delay for monitors of the system using data for 65nm technology. The delay increase as a function of the failure distribution
parameters, the path length, and gate type have been investigated.

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 Analog & Mixed-Signal IC Design (II)

Chaired by José Luis Ausín (U. Extremadura) and Eduard Alarcon (U. Politècnica de Catalunya)

1. A 0.18UM CMOS LOW-POWER AND COMPACT DPS FOR X-RAY IMAGING

Roger Figueras, Justo Sabadell, Josep Maria Margarit, Elena Martín, Lluís Terés, Francisco Serra-Graells
• This paper presents a new CMOS active pixel sensor specifically for digital X-ray imagers. The proposed DPS architecture includes a novel lossless A/D conversion
scheme, a dark current self-cancellation mechanism, as well as self-biasing and built-in test capabilities, all at pixel level. Furthermore, FPN compensation is achieved
by introducing gain programmability inside the A/D converter of each individual pixel. The proposed CMOS circuits make extensive use of subthreshold transistor
operation and circuit reuse to obtain a low-power and compact DPS cell. A circuit implementation in standard 0.18um CMOS 1-polySi 6-metal technology is presented
together with some preliminary results.

2. THREE NOVEL IMPROVED CMOS CAPACITANCE SCALING SCHEMES

Jesus Aguado Ruiz, Antonio J. Lopez Martin, Jaime Ramirez Angulo
• A comparison between some different classic and novel capacitance scaling schemes is presented. The novel topologies which use a modified CCII, an improved
current mirror and a current steering configuration of OTAs provide higher values of Q and better frequency responses than the classical structures using basic
current mirror schemes, as the simple current mirror and two different cascode current mirrors. Simulation results and some measurements for the six different
studied schemes are presented.

3. MODELLING AND IMPLEMENTATION OF CAPACITOR TO DIGITAL CONVERTERS

Johann Hauer, Stefan Mödl, Robert Dorn
• For capacitive measurement applications different methods were proposed recently. One of the most promising architecture to achieve high resolution is the delta
sigma capacitance to digital converter (CDC). It offers a multitude of architectural variants – order of modulator, oversampling ratio, multibit feedback and digital filter
functions to design for a requested specification. VHDL-AMS circuit block models were developed to allow for fast simulation and evaluation of different architectures.
Implementations have been done for first order, second order und fourth order modulators on a 350nm CMOS technology. For the fourth order modulator a resolution
of 52 aF was achieved with an oversampling ratio (OSR) of 50 @ 1 MHz modulator clock and 19.3 aF for the second order modulator with OSR 500 @ 10 MHz
modulator clock rate, corresponding to a noise level of 0.2 aF/sqrt(Hz).

4. ACCURATE DYNAMIC-FEEDBACK CMOS CROSS-QUAD SUITABLE FOR LOW-VOLTAGE OPERATION

Belen Calvo, Jaime Ramirez-Angulo, Antonio Lopez-Martin, Ramon G. Carvajal
• This paper presents the implementation of a cross-quad circuit suitable for low-voltage operation. The proposed cell exploits a dynamic positive feedback gm
boosting technique to achieve linear voltage-to-current conversion, while it manages to work with low-voltage with no extra bias current and minimal additional
hardware. Results for a 0.5 um CMOS implementation supplied at 3 V show a 0.972 % voltage-to-current accuracy, improving the 0.867 % accuracy of a previously
reported cross-quad topology also suitable for low-voltage operation which is based on folded transistors.

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 Bioinspired Systems &
Integrated Sensors
Chaired by Atila Herms (U. Barcelona) and Gustavo Liñán-Cembrano (IMSE-CNM, CSIC)

1. EXPLOITING MEMRISTANCE FOR IMPLEMENTING SPIKE-TIME-DEPENDENT-PLASTICITY IN NEUROMORPHIC

NANOTECHNOLOGY SYSTEMS
Bernabe Linares-Barranco, Teresa Serrano-Gotarredona
• In this paper we show that STDP can be implemented using a crossbar memristive array combined with neurons that asynchronously generate spikes of a given
shape. An attenuated version of such spikes needs to be sent back through the neurons input terminal. The shape of the spikes turns out to be very similar to the
neural spikes observed in biology for real neurons. The STDP learning function obtained by combining such neurons with memristors is exactly that of the STDP
learning function obtained from neurophysiological experiments on real synapses.

2. LOW-FREQUENCY NOISE IMPACT ON CMOS IMAGE SENSORS

Philippe MARTIN-GONTHIER, Pierre MAGNAN
• CMOS image sensors are nowadays extensively used in imaging applications even for high-end applications. This is really possible thanks to a reduction of noise
obtained, among others, by Correlated Double Sampling (CDS) readout. Random Telegraph Signal (RTS) noise has thus become an issue for low light level
applications especially in the context of downscaling transistor size. This paper describes the analysis of in-pixel source follower transistor RTS noise filtering by CDS
circuit. The measurement of a non Gaussian distribution with a positive skew of image sensor output noise is analysed. Impact of dimensions (W and L) of the in-pixel
source follower is demonstrated. Circuit to circuit pixel output noise dispersion on 12 circuits coming from 3 different wafers is also analysed and weak dispersion is
seen.

3. PIXEL DESIGN AND EVALUATION IN CMOS IMAGE SENSOR TECHNOLOGY

Sonia Vargas-Sierra, Elisenda Roca, Gustavo Liñán-Cembrano
• A chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor
(APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel
architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses.
Besides, structures to study the influence of crosstalk between pixels have been incorporated.

4. DIGITAL MAPPING OF A REALISTIC SPIKE TIMING PLASTICITY MODEL FOR REAL-TIME NEURAL
SIMULATIONS
Bilel Belhadj, Jean Tomas, Yannick Bornat, Adel Daouzli, Olivia Malot, Sylvie Renaud
• We develop the major steps taken to map a realistic spike timing-dependent plasticity (STDP) model into digital hardware architecture. Several types of mappings are
implemented and tested on FPGA device. We compare their applicability to a real-time spiking neural network (SNN) simulator running in biological time-scale.

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 Vision & Image Processing
Chaired by Roberto Sarmiento (IUMA) and Francisco Serra-Graells (IMB-CNM, CSIC)

1. A SPATIAL CALIBRATED AER CONTRAST RETINA WITH ADJUSTABLE CONTRAST THRESHOLD

Juan Antonio Leñero-Bardallo, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
• Address Event Representation (AER) is an emergent technology for assembling modular multi-blocks bio-inspired sensory and processing systems. Visual sensors (retinae) are among the
first AER modules to be reported since the introduction of the technology. Spatial contrast AER retinae are of special interest since they provide highly compressed data flow without reducing
the relevant information required for performing recognition. Reported AER contrast retinae perform a contrast computation based on the ratio between a pixel’s local light intensity and a
spatially weighted average of its neighbourhood. This results in compact circuits, but with the penalty of all pixels generating output signals even if they sensed no contrast. In this paper we
present a spatial contrast retina with bipolar output: contrast is computed as the relative difference between a pixel’s local light and its weighted spatial average. As a result, contrast includes
a sign and the output will be zero if there is no contrast. Furthermore, an adjustable thresholding mechanism has been included, such that pixels remain silent until they sense an absolute
contrast above the adjustable threshold. The pixel contrast computation circuit is based on Boahen’s Biharmonic operator contrast circuit, which has been improved to include mismatch
calibration and adaptive current based biasing. As a result, the contrast computation circuit shows much less mismatch, is almost insensitive to ambient light illumination, and biasing is much
less critical than in the original voltage biasing scheme. A full AER retina version has been fabricated. In the present paper we provide simulation and preliminary experimental results.

2. ON-CHIP RETINAL IMAGE PROCESSING: PERFORMANCE ANALYSIS ON DIFFERENT APPROACHES

Alejandro Nieto, Roberto Osorio, Victor Brea, David L. Vilariño
• In this paper, the implementation of an algorithm for retinal vessel tree segmentation on three different hardware architectures is addressed. Particularly, a focal-plane processors array, a
FPGA-based coarse grain parallel computer and a manycore processing system have been considered. Furthermore, three different computation paradigms have been approached, based
on the features of any of the platforms: pixel-parallel single instruction and multiple data (SIMD), coarse-grain SIMD and stream processing. The algorithm consists of a set of low-level image
processing steps, very common in any early vision computing. Therefore, even if this is an application oriented research, the experimental results and conclusions from the analysis are also
extensive to other applications involving low-level image processing.

3. LOW POWER LVDS TRANSCEIVER FOR AER LINKS WITH BURST MODE OPERATION CAPABILITY
Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
• This paper presents the design and simulation of an LVDS transceiver intended to be used in serial AER links. Traditional implementations of LVDS serial interfaces require a continuous data
flow between the transmitter and the receiver to keep the synchronization. However, the serial AER-LVDS interface proposed in [2] operates in a burst mode, having long times of silence
without data transmission. This can be used to reduce the power consumption by switching off the LVDS circuitry during the pauses. Moreover, a fast recovery time after pauses must be
achieved to not slow down the interface operation. The transceiver was designed in a 90 nm technology. Extensive simulations have been performed demonstrating a 1 Gbps data rate
operation for all corners in post-layout simulations. Driver and receiver take up an area of 100x215 um2 and 100x140 um2 respectively.

4. IMPROVED AER CONVOLUTION CHIP FOR VISION PROCESSING WITH HIGHER RESOLUTION AND NEW FUNCTIONALITIES
Luis Alejandro Camuñas-Mesa, Alejandro Linares-Barranco, Antonio Acosta-Jiménez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco
• We present a new neuromorphic fully digital convolution microchip for Address Event Representation (AER) spike-based processing system. This chip computes 2-D convolutions with a
rogrammable kernel in real time. Previously, we designed and tested another convolution chip with a size of 32 x 32 pixels [1] and, based on the information obtained from this test, we have
designed a new chip with larger resolution (64 x 64 pixels), improved behavior and new functionalities included. This chip receives and generates data in AER format, which is an
asynchronous protocol, implementing the convolution of the input images with a programmable kernel. The most important new functionality included in this chip is the multikernel capability,
which allows us to program several kernels (up to 32) so that each input event will be processed with the corresponding kernel, depending on the origin of the input event. The paper
describes the architecture of the chip, with special emphasis to the new improvements.

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 Analog-Digital Interface Design
Chaired by Adoración Rueda (IMSE-CNM, CSIC) and Eugeni García (U. Illes Balears)

1. OVERSAMPLED TRACKING QUANTIZERS IN CONTINUOS-TIME SD MODULATORS TO REDUCE THE NUMBER

OF COMPARATORS
Francisco Colodro, Antonio Torralba
• Using a tracking ADC as the quantizer of a Sigma-Delta modulator has been shown to be an efficient method to reduce the number of comparators. In this paper a
new Continuous-Time Sigma-Delta Modulator is proposed where a large reduction in the number of comparators is obtained by clocking the quantizer tracking loop
at a high frequency rate. The output of the tracking quantizer can be down-sampled so that the modulator output has the same resolution and sampling rate as the
original modulator. In this way the design of the Digital-to-Analog converters in the feedback loop and the decimator filter at the modulator output are not penalized.

2. ANALOG SQUARING CIRCUIT BASED ON TIME ENCODING

Francisco Colodro, Antonio Torralba, J.L. Mora, J.M. Martinez-Heredia
• Accurate analog squarers are required for different signal processing functions, like amplitude modulation, frequency shifting, signal power estimation, and neural
and image processing. Transistor-level analog squarers suffer from limited accuracy, especially in modern deep submicron technology where the squared law of the
MOS transistor in the saturation region is no longer valid. Based on the Asynchronous Sigma-Delta Modulator (ASDM), a new circuit which provides the squared
value of the input signal is proposed. In this paper, the proposed analog squarer is studied, and the analytical results are validated by simulation in the time domain.
The effect of analog imperfections on the accuracy of the squarer is also analyzed showing that a high Signal to Noise plus Distortion Ratio can be obtained for
typical values of the mismatch and up to frequencies near half the maximum frequency of the ASDM limit cycle.

3. RANDOM CHOPPING IN SIGMA-DELTA MODULATORS

Gildas Leger, Antonio Gines, Eduardo Peralías, Adoración Rueda
• Sigma-Delta modulators make a clever use of oversampling and exhibit inherent monotonicity, high linearity and large dynamic range but a restricted frequency
range. As a result Sigma-Delta modulators are often the preferred option for sensor and instrumentation. Offset and Flicker noise are usual concerns for this type of
applications and one way to minimize their effects is to use a chopper in the front-end integrator of the modulator. Frequency-shaped random chopping has been
proposed to minimize the impact of reference voltage interference. It is shown in this paper that the chopper signal is not the only term that modulates the offset and
Flicker noise and that unwanted crosstalk can significantly degrade the performance of the modulator.

4. HIGH FREQUENCY ANALOG-TO-DIGITAL CONVERSION BASED ON SUBSAMPLING

José Ramón García Oya, Antonio Jurado Díez, Fernando Muñoz Chavero, Antonio Torralba Silgado
• The focus of this work is the implementation of a Analog-to-Digital Converter System using techniques based on subsampling. Its main objective is to improve the
features of a receiver used for wideband communications reducing the number of elements of the system with a higher flexibility and resolution. This proposed
system is based on commercial devices, mainly a Low Jitter and Wideband Sample&Hold and a High Resolution Intermediate-frequency Analog-to-Digital
Converter.

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 Defect & Fault Tolerance
Techniques
Chaired by Ainhoa Galarza (CEIT, TECNUN) and Eugeni Isern (U. Illes Balears)

1. NEW REDUNDANT LOGIC FUNCTION DESIGN METHOD FOR EXTREMELY HIGH NOISE AND LOW-VOLTAGE
SCENARIOS
Lancelot Garcia, Antonio Calomarde, Francesc Moll, Antonio Rubio
• The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several
areas of design. The intrinsic variability problem is aggravated by variations caused by the difficulties of controlling Critical Dimension (CD) in nanometer
technologies. The effect of variability is the difficulty in predicting and designing circuits with precise device and circuit characteristics. In this paper, a new logic gate
implementation methodology oriented to special applications or technologies is presented, to improve the gate tolerance to errors due to noise, defects or
manufacturability errors. The methodology is based on reinforcement of valid input-output combinations by means of logic feedback functions. Simulations show an
excellent performance of our approach in the presence of large random noise at the inputs.

2. FAULT INJECTION TECHNIQUES FOR THE SAFETY AND AVAILABILITY CHARACTERIZATION OF AN N OUT OF
M SYSTEM
Almir Villaro, Jon Mendizabal, José Ramón Martín, Iñigo Adin, Ahinoa Galarza
• A new method to characterize fault tolerant systems is presented. The fault injection tests can be done with minimal modification to the hardware of the system and
no modification of the software. These tests are made using the internal and external communications of the device under test. Communications are modified using
an interleaved element that analyze messages and change them. An overview of the Measure tool that controls the fault injection is also presented.

3. IDSM: AN IMPROVED CONTROL FLOW CHECKING APPROACH WITH DISJOINT SIGNATURE MONITORING
Salma BERGAOUI, Regis LEVEUGLE
• Soft errors have become a significant threat in embedded systems. Multiple errors have furthermore become a
real concern. New approaches must therefore be proposed to detect errors in a system without assumptions on the error multiplicity. Control flow error detection is
one possible approach for processor-based systems but most revious
techniques modify the initial system and are therefore not compatible with norms such as IEC 61508. We propose here a new technique based on disjoint signature
monitoring and detecting also errors in the most critical system variables.
Comparisons are made with previous techniques.

4. BUILT-IN SELF TEST CIRCUIT FOR DELAY DEGRADATION DETECTION

Fahad Ahmed, Linda Milor
• This work presents the design of an on-chip ring oscillator based device wearout monitoring circuit. The proposed scheme monitors the delay through a data path
using a delay detection circuit (DDC). The circuit can be used to monitor a variety of wearout mechanisms that impact delay, such as electromigration, negative bias
temperature instability, and hot carrier injection.

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 Communications Systems

Chaired by Andoni Irizar (CEIT, TECNUN) and Pilar Molina (U. Zaragoza)

1. MEASURING FPGA SOFT PROCESSOR PERFORMANCE IN STREAMING APPLICATIONS

Sergio Costas-Rodríguez, Rafael Martínez-Álvarez, Francisco J. González-Castaño, Felipe Gil-Castiñeira
• This paper analyzes a low-cost streaming server based on a FPGA virtual processor, or soft processor. We measure the performance of a soft processor server
implementation to
bring development costs down, and compare it with a fully hardware-oriented implementation.

2. HARDWARE IMPLEMENTATION OF A LOW-COMPLEXITY SYNCHRONIZER FOR A WLAN 802.11A

TRANSCEIVER
Aritz Alonso, Andoni Irizar, Jose Ramón Martín, Igone Vélez, Ainhoa Cortés, Naiara Arrue
• In this paper we are presenting a hardware implementation of a synchronizer for a WLAN 802.11a compliant transceiver based on the algorithm proposed by J. Liu
and J. Li. The architecture of the synchronizer has been designed
with simplicity in mind and to reuse as many blocks as possible from the existing transceiver. The synchronizer has been described in VHDL.

3. TRADEOFFS IN THE DESIGN OF A VITERBI DECODER FOR A MB-OFDM RECEIVER

Mário Véstias, Hugo Santos, Helena Sarmento, Horácio Neto
• MB-OFDM is an ultra wide band technology for low power, short range and high speed wireless communications, using the 3.1 GHz-10.6 GHz band. It is a promising
technology to be used in Wireless Personal Area Networks, permitting data rates up to 480 Mbit/s.
This paper analyses the tradeoffs involved in the design of a Viterbi decoder using FPGA technology. The number of soft bits, the traceback length and the code
rates are the parameters considered in this analysis.

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 Invited Talk

Millimeter wave design in bulk-CMOS and CMOS-SOI

Andreia Cathelin
(STMicroelectronics, Grenoble)

The presentation will start with a short notice about mmW applications targeting CMOS integration: high data rate WLAN/WPAN
communications, low data date sensor applications and THz imaging. Then, an overview of deep submicron CMOS technologies
(bulk and SOI) will be presented. Insights on the SOI specific devices will be given. The HF behavior of active devices will be out
lighted via the well-known figures of merit: fT, fmax and NFmin. The design of passive devices for mmW will also be presented,
taking into account all the constraints coming from the BEOL of digital deep-submicron technologies. Active and passive devices
design hints for mmW will finalise this section. The following section presents mmW building blocks on CMOS: LNA, mixer, VCO,
Rx Front-End, ... Design techniques will be discussed, based on the information presented in the previous section, together with
technical implementation details and measurement results.

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 Analog & Mixed-Signal IC Design (III)

Chaired by Ramón Carvajal (U. Sevilla) and Concepción Aldea (U. Zaragoza)

1. SELF-CALIBRATING FILTER BY USING OSCILLATION-BASED TEST

Joan Font, Eugeni Isern, Miquel Roca, Rodrigo Picos, Eugeni Garcia
• We have designed a second-order band-pass filter which can provide itself information about its central frequency when it is led to an specific operation mode (test
mode). The filter has been built with discrete components around a TL071 OpAmp. When a control digital signal toggles the test mode, the filter components are
reordered thanks to analog switches into an oscillator. The oscillation frequency allows to predict the filter central frequency with an rms error of 0.2%. As there are
many possibilities to reconfigure the filter into an oscillator we have found out a simple criterion to choose the best scheme in order to improve the prediction
accuracy.

2. NEW HIGH PERFORMANCE SECOND GENERATION CMOS CURRENT CONVEYOR

Swathi Marri, Jaime Ramirez-Angulo, Antonio Lopez-Martin, Ramon Carvajal
• A new high performance second-generation CMOS current conveyor architecture is presented. It is built using a differential flipped voltage follower as its input buffer
stage and a cascode current mirror as output stage. It is characterized by very low output impedance. It provides gain independent high bandwidth when used to
implement a programmable gain voltage amplifier. Simulation and experimental results in AMI 0.5µm CMOS technology are provided to validate the characteristics of
the design.

3. A TWO SECTION PHASE-SHIFT OSCILLATOR

Jose Salvado, Joaquim Oliveira, Gilberto Martins
• Phase-Shift Oscillators are very popular,normally with Op Amp based confugurations, using inverting amplifiers and three RC sections. This paper proposes an
alternative configuration which only uses two RC sections and an non-inverting amplifier. Instead of using a single Op Amp stage we propose the use of composite
Op Amps arrangment, in order to extend the frequency range.
Basic theory and configuration is explained,preliminary experimental results are shown. Further research is being carried in order to improve the oscillator
performance.
The proposed configuration is suitable for analog IC design.

4. A HIGH-PERFORMANCE CMOS VOLTAGE-TO-FREQUENCY CONVERTER FOR LOW-POWER SYSTEMS

Belen Calvo, Nicolas Medrano, Cristina Azcona, Santiago Celma, M. De Rodanas Valero, M. Teresa Sanz
• This paper presents a low-cost high-speed CMOS voltage-to-frequency converter (VFC) which targets front-end sensor interfacing in wireless sensor networks
applications. The proposed VFC, designed in a 0.35 um CMOS technology supplied at 3 V, is very simple, obtaining at the same time high performance
characteristics: it operates with a power consumption below 0.65 mW at output frequencies ranging from 1.204 MHz to 2.192 MHz given a 1.0-2.0 V input (1 MHz/V
sensitivity) with an accuracy better than 0.4 %.

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 Digital Signal Processing

Chaired by Ainhoa Cortés (CEIT, TECNUN) and Sebastián López (IUMA)

1. HIGH-DEFINITION BELIEF-PROPAGATION BASED STEREO MATCHING FPGA ARCHITECTURE

Jesus Perez, Pablo Sanchez, Marcos Martinez
• Nowadays 3D systems are starting to be included in real applications. One of the most used groups of 3D algorithms is the stereo matching one. The stereo matching algorithm obtains a
stereoscopic image, which includes information about the distance from the camera to the objects in the image (i.e. depth information). This information combined with the original image
creates the 3D images as seen, for example, in 3D movies.
Several algorithms have been proposed to obtain an accurate depth map. Among all of them, those based on energy minimization using Belief Propagation message passing have shown
great performance and quality. However, the iterative process carried out leads to high consumption of resources. Implementations in CPU are very slow. Moreover, the inherent parallelism
this algorithm shows makes it a good candidate either for GPU or FPGA implementations. There have been several attempts to implement in GPU platforms, but the memory bottleneck limits
the speed when high-definition images are used. A few implementations on FPGA have been presented, but always with low-resolution images. In this paper we present a high-definition
depth estimation architecture based on BP for FPGA platforms. The architecture proposed uses a bank of DDR2 memories able to work at 200Mhz to reduce the execution time required for
obtaining high-definition depth maps. Moreover, to generate data at the maximum frequency allowed by the DDR2 memory, several improvements in the algorithm architecture are proposed.
The architecture has been implemented in a Xilinx Virtex 5 330 VLX FPGA with speed grade -1. As a result, a high-definition depth map can be obtained in only 0.32 seconds, outperforming
the FPGA-based architectures presented up to date.

2. COMPLEMENTARY CODE COMBINING IN DVB-SH

Cinta Oria, José García, Patricio López, Darío Pérez-Calderón, Joaquín Granado, Vicente Baena, David Ortiz
• Complementary Code combining diversity is a simple and efficient technique to exploit the advantages of a hybrid satellite/terrestrial system. In this paper, the application of code combining
diversity to Digital Video Broadcasting Satellite to Handheld (DVB-SH) systems is investigated. It is shown that a meaningful diversity gain can be obtained in multiple frequency networks by
combining the terrestrial and satellite signals. This gain allows an improvement of the receiver robustness in both static and mobile scenarios. Furthermore, in terminals with two receiver
branches, a common situation in DVB-SH, this gain can be easily obtained without increasing the hardware complexity.

3. HARDWARE-AWARE ALGORITHMIC IMPROVEMENTS OF VOXEL-BASED VISUAL HULL RECONSTRUCTION

Pablo Garralda, Jesús M. Pérez, Pablo P. Sánchez, Marcos Martínez
• Visual hull (VH) reconstruction has become one of the most important issues in 3D vision applications. Many vision applications perform VH from a set of silhouette images with a method
called “shape from silhouette” (SfS) to carry out their functions.
High-definition 3D video for real-time applications is one of the features that the next generation of telecommunication systems is exploring. All existent methods based on SfS have similar
limitations when working under such conditions. On the one hand, the latency in real-time video applications must allow the processing of 25/30 frames per second. On the other hand, there
are strict limitations of quantity of memory required and number of operators used to perform VH reconstruction. These limitations makes hardware design difficult using CPUs, GPUs or
FPGAs as hardware support. Therefore, any improvement carried out on these points is worth to be considered.
In this paper we describe a group of algorithmic improvements to reconstruct VH using a voxel-based approach. The aim of these improvements is to generate high-definition VH in real-time
systems with low hardware cost by means of the reduction and simplification of necessary operations to make this process possible. Our improvements reduce the number of adds by roughly
60% and almost all multiplications.

4. ROTATED CONSTELLATIONS FOR DVB-T2

Darío Perez-Calderón, Cinta Oria, José García, Patricio López, Vicente Baena, Ignacio Lacadena
• In this paper, the performance of the rotated constellation technique is analyzed in the context of the forthcoming Second Generation Digital Video Broadcasting (DVB-T2) standard. This
technique increases the robustness of the DVB-T2 receiver in severe multipath propagation scenarios. Although the rotated constellations improve the performance of the system in all the
simulated multipath channels, this improvement is particularly great in channels with erasure events where for some coding rates the non-rotated constellations are not able to correctly
decode the received information.

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 System Design Methods

Chaired by Marisa López Vallejo (UPM) and Encarnación Castillo (U. de Granada)

1. DEVELOPMENT OF A STANDARD SINGLE FLOATING POINT LIBRARY AND ITS ENCAPSULATION FOR REUSE
Pedro Echeverria, Miguel A. Sanchez, Marisa Lopez-Vallejo, Carlos A. Lopez-Barrio
• Nowadays the integration degree achieved by deep sub-micron technologies allows the implementation of complex applications in current FPGAs. This is the case of
computations that use floating-point arithmetic, which require large amounts of resources and long design times. Thus, the availability of libraries of floating-point
operators can significantly help designers when dealing with this kind of applications. Furthermore, the encapsulation of the components of this library becomes a
must to ease the automation of the design cycle, which is currently under research. In this work we present a standard floating-point library fully compliant with the
IEEE standard. The multiple design choices of the designed operators have been collected and encapsulated through the definition of a high level interface using the
xHDL language. This encapsulation considerably simplifies the handling of the floating-point operators carried out by system tools.

2. EMBEDDING MATLAB IN SYSTEMC TRANSACTION LEVEL MODELING FOR VERIFICATION

Koldo Tomasena, Juan Francisco Sevillano, Naiara Arrue, Ainhoa Cortes, Igone Velez
• This paper presents an approach to perform the verification of correct algorithm cooperation to achieve system functionality using executable models. The approach
employs a description of the architecture of the system as a SystemC transaction level model; and a description of the algorithms as Matlab M-files. It is proposed to
perform simulations where the SystemC architectural elements use a Matlab engine to execute their Matlab algorithm specifications. A library is proposed to abstract
the SystemC developer from the low level SystemC-Matlab interaction. This way, both the system and algorithm teams can work efficiently in their preferred
environments, to perform early architecture-algorithm optimization.

3. A DEPENDABLE STACK PROCESSOR CORE FOR MPSOC DEVELOPMENT

Mohsin AMIN, Abbas RAMAZANI, Fabrice MONTEIRO, Camille DIOU, Abbas DANDACHE
• Multiprocessor System-on-Chip (MPSoC) architectures are a promising solution to fulfill ever-increasing performance requirements of embedded systems, as these
mega architectures provide high level computing and a flexible design. Another aspect becoming increasingly important is dependability. Indeed, as semiconductor
technologies continue to scale down, soft error rate in logic circuits is rapidly increasing, setting the need for fault tolerant systems very high. Processing nodes are
the backbone of MPSoCs, so they should be simple and fault tolerant.
This paper presents the design methodology for a dependable processor core to be used as a processing node in a MPSoC. Here, we are choosing a stack
processor architecture as it can be very simple and yet achieve a quite reasonable level of performance. Actually, simplicity is an important aspect helping to integrate
a large number of nodes in a reasonable small area MPSoC and to fulfill dependability. The stack processor dependability is achieved with the help of some extra
hardware that adds online checking and rollback capacity. The main idea is based on the use of a specially designed on-chip journal memory cache inserted between
the stack processor and the main memory in write operations. The role of this cache memory is not to increase the processing speed but to support an effective re-
execution model of instruction sequences in the case of error detection.

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 Reconfigurable Computing &
Digital IC Design
Chaired by Antonio Rubio (U. Barcelona) and Joan Figueras (U. Politècnica de Catalunya)

1. DYNAMICALLY RECONFIGURABLE ARCHITECTURES FOR MULTIMEDIA APPLICATIONS

Teresa G. Cervero, Sebastián López, Roberto Sarmiento
• The relevance of the multimedia in our society has motivated an increase in the research activity within the reconfigurable computing area. As a consequence, during
last decades a lot of papers have been published, generating an important knowledge in this area. However, there is a lack of uniform criteria in order to classify
these contributions, as a way of understanding its potential advantages and disadvantages. This paper reviews the most relevant dynamically reconfigurable
architectures for multimedia applications, sorting them according to their hardware elements and their disposition. Finally, this paper exposes advantages and
disadvantages of these reconfigurable architectures for implementing real-time multimedia applications according to their hardware classification.

2. A NEW EFFECTIVE PARALLEL-PIPELINED ARCHITECTURAL SCHEME FOR HIGH-SPEED SMALL-AREA IIR

DIGITAL FILTERS
Houssein JABER, Fabrice MONTEIRO, Abbas DANDACHE
• The demand for high-speed small-area digital filters has been recently boosted by the emergence of applications such as software defined radio in mobile
communication systems. Actually, the higher frequency range signals in these applications used to be handled by analog parts. However, the extensive use of analog
parts, reducing the flexibility and adaptability of these applications, is a major disadvantage in current and future multi-standard systems targeting versatile operation.
Hence the increasing demand for (almost) all-digital systems.
This paper focuses on the implementation of infinite impulse response (IIR) filters to be used in the higher frequency stages of mobile communication systems.
Actually, the very high sampling frequencies to be handled require parallel architectural techniques to be used, which generally result in extensive area consumption.
Herein, we propose two variant of a new parallel-pipelined design scheme for IIR filter architectural offering a very effective trade-off between speed performance and
area consumption.
In order to evaluate the speed/area trade-off and validate the architecture, several IIR filters have been implemented for different parallelization levels on FPGA
devices of the Altera Stratix II family. The experimental results show clearly that, according to the speed/area criteria, one of the architecture variants outperforms the
other one, faster sampling rates being achieved (up to 2.49 GHz on 32-parallel input implementations) with noticeable area consumption reduction (30% smaller
average area).

3. A RECONFIGURABLE FAST FOURIER TRANSFORM IMPLEMENTATION FOR MULTI-STANDARDS

APPLICATIONS
Florent Camarda, Jean-Christophe Prévotet, Fabienne Nouvel
• This paper deals with the implementation of a new reconfigurable architecture for the computation of Fast Fourier Transform (FFT) in the context of Digital Terrestrial
Television Broadcasting (DTTB). The proposed architecture, implemented in a Field Programmable Gate Array (FPGA) device allows various possibilities in the
choice of the FFT size. In this paper, two algorithms (Radix algorithm and Winograd Fourier Transform Algorithm (WFTA)) are presented. These may be used to
compute FFT of size 2048 (2K), 4096 (4K), 8192 (8K) or 3780 that are utilized in three of the most important DTTB standards. An original reconfigurable architecture
is presented with possible optimizations according to the applications' constraints. Timing performances and resources requirements are provided in comparison with
classical architectures.

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 HW-SW Codesign

Chaired by Juan Carlos López (U. Castilla la Mancha) and Eugenio Villar (U. de Cantabria)

1. MULTIMEDIA IP EMULATION ENVIRONMENT USING CHIPIT PLATFORM

Lucana Santos, Valentín De Armas, Félix Tobajas, Roberto Sarmiento
• In this article, a methodology is set for rapid IP and System-On-Chip (SoC) verification. The CHIPit Platinum Edition- a high-speed and high-capacity emulation and
prototyping system- is the tool which is used in order to design that methodology. It has been applied to multimedia systems, specifically to an IP called Loop Filter,
which is a low-pass filter used for the H.264/AVC video compression. It is shown that, using the CHIPit platform and following the designed methodology, the design
process can be shortened and the finding of mistakes in the design can be made easier.

2. AUTOMATIC GENERATION OF MODIFIABLE PLATFORM MODELS IN SYSTEMC FOR AUTOMATIC SYSTEM

ARCHITECTURE EXPLORATION
Héctor Posadas, Gerardo De Miguel, Eugenio Villar
• Early Design Space Exploration (DSE) is crucial to achieve optimal designs in large, configurable embedded systems. In platform-based design, the exploration
process must cover two areas: selecting the base platform and customizing the configuration parameters. Although exploring the optimal parameters' configuration is
a well-known topic, there is a lack of works exploring both areas together. There are no mechanisms to describe all the platform possibilities or simulation
infrastructures capable of supporting automatic DSE of both areas. This work proposes a XML-based methodology oriented to describe and automatically create
system models of fully configurable systems. The XML descriptions are adequate to be handled by common multi-objective exploration tools. The simulation
infrastructure developed automatically creates the models of the different possible architectures and obtains their performance features to perform the exploration. To
allow efficient architecture exploration, the high-level system model is automatically built at run-time, avoiding recompiling times.

3. CO-DESIGN METHODOLOGY FOR REAL-TIME AND HIGH-DEFINITION 3D RECONSTRUCTION ALGORITHMS

Cristina Fernández, Jesús M. Pérez, Pablo P. Sánchez, Marcos Martínez
• The next generation of telepresence systems are more focused on 3D high-definition and real-time features. Execution time requirements in a real-time
videoconference system are limited to 40 milliseconds in order to guarantee an appropriate sensation of presence. High definition requirements lead to image sizes of
at least 1280 x 720 pixels.
There are some problems when it comes to unifying all these requisites, such as memory dataflow bottlenecks, high execution times or high area cost. This paper
reports a co-design methodology for performance analysis of a set of 3D reconstruction algorithms, written in C/C++. This is the first time this has been done within a
telepresence environment. Traditional analysis have treated real-time systems or high-quality formats separately. In our methodology, there is an execution time
evaluation and time analysis of the code. Moreover, temporal results are analysed under a virtual platform and a specific hardware platform with very similar results.
This proves the validity of the virtual platform. Finally, our solution proposes clear hardware and software partitions that will implement the most time consuming
functions of the “visual hull” and “depth estimation” algorithms in a FPGA or a DSP.

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 Smart Objects &
Wireless Applications
1. Chaired by Antonio Torralba (U. Sevilla) and Bonifacio Martín (U. Zaragoza)

2. A COMPARATIVE OVERVIEW AND ANALYSIS OF RECONFIGURABLE TUNING NETWORKS BASED ON GAAS

MMIC AND MEMS RF SWITCHES
César Sánchez, Jesús De Mingo, Paloma García, Pedro Carro, Antonio Valdovinos
• Reconfigurable tuning networks are becoming widely used in wireless communication systems to improve the effciency. In this paper, two reconfigurable tuning
networks based on different switching technologies are presented. The former is based on GaAs MMIC RF switches and the latter is based on RF MEMS switches.
The same topology in the tuning network is used in both alternatives and a comparative overview is established between the two networks. A complete methodology
for the evaluation and analysis for this kind of networks is presented, independently of the technology employed.

3. BIOBEE: A WIRELESS BIOELECTRICAL IMPEDANCE MONITORING SYSTEM

Javier Ramos, Jose Luis Ausin, Guido Torelli, Juan Francisco Duque-Carrillo
• In this work, we present a ZigBee-based wireless bioelectrical impedance system for monitoring physiological parameters in a wide variety of applications, ranging
from monitoring high-risk patients to sensing levels of physical activity in sports personnel. The measurement principle is based on the magnitude-ratio and phase-
difference detection method. The system is composed of an application-specific integrated circuit, designed in 0.35-μm CMOS technology, that implements the
analog parts for the sensing section, and a transceiver chip that provides reliable wireless communication.

4. ON THE WIRELESS SENSOR NETWORKS LIFETIME DEPENDENCE WITH THE ROUTING ALGORITHM:
COMPARISON WITH ZIGBEE
Manel Lopez, José María Gomez, Jordi Sabater, Josep Sabater, Sergio Martinez, Lluisa Climent, Atila Herms
• Wireless Sensor Networks is one of the most interesting research fields of the last years. The major focal point is the routing algorithm that is usually implemented in
the network layer of the communication protocol. Routing analysis focuses on several issues: routing mechanism, cost and maintenance, power consumption and so
on. In this paper we have designed and implemented a proactive routing algorithm based on the global state of the network. We have designed and simulated
software strategies to minimize the power consumption because of this are of a great importance for this kind of networks. Finally, The routing protocol designed was
compared with one of the most commonly used protocols for wireless sensor networks: Zigbee. The results seems indicate that for low density uniform distributed
networks Zigbee has a better behaviour in terms of lifetime, but for Poisson distributed networks, the protocol presented here behaves better.

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