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International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012

Bin packing approach for solving VLSI circuit partitioning problem using Genetic algorithm
Prof. Sharadindu Roy University of Calcutta
.

Prof. Samar Sen sarma University of Calcutta

Siddhartha Das Calcutta university

Abstract:

In this paper,the circuit partitioning using genetic algorithm with bin packing concept has been attempted. In this practical paper solution is easy and we can easily apply genetic operator in this type of problem. The bin packing problem is to find the Index terms: minimum number of bins needed to pack a given set of objects Partitioning, Genetic Algorithm, NP-hard, Net list, of known sizes so they do not exceed the capacity of each bin. Crossover, Mutation, cut size, in packing. Complexity is both time in space, provided size of problem an Genetic algorithm: as integer (count is infinite).This problem is known NP-hard. The genetic algorithm involves the following basic The technique of our approach is to be design module trick. We stepscan be realizing with self standard IC chip. Obviously we have Evaluation. taken into account minimum power conjunction. The solution Crossover of a circuit partitioning problem is global optimum. Like circuit Mutation. partitioning is the more critical step in the physical design of Crossover: various circuit in VLSI.In the partitioning main objective is to One point crossover : minimize the number of cuts.This chapter addresses the Part of the first parent copied rest is taken in the same problem of partitioning and particular the use of the genetic order as in second parent. algorithms for circuit partitioning.The object to be partitioned in Two point crossover :VLSI design are typically logic gates or instances of standard Two part of the first parent are copied and the rest cell. between is taken in the second parent in same order. Circuit partitioning is one of the important parts in chip designing. We let, the number of bins will be needed equal to be number of genes divided by number of bins. At first the genes will be insert in first bin until the bin is not full, when bin is full then insert second bin and so on. Our method calculates the fitness value and discards solution with low fitness value. The increase in number of crossover point does not necessarily increase the fitness, as the fitness achieved depends on crossover as well as mutation probability. Especially in the paper find minimum cut size. If we get, cut size is same on generation than change the crossover boundary. This paper shows bin packing approach for the circuit partitioning using genetic algorithm . Genetic algorithm is an evolutionary optimization technique based on Darwinian Theory of natural evolution and its concept of survival of the fittest. The main advantage of circuit partitioning using bin packing areInitial partition is not required, there are no need to encoding chromosome with block number also chromosome will be encoded by gate or node name with BFS and 493 | P a g e

Any sequence. Also the main superiority over circuit partitioning using GA is we can do easily multi way partitioning in many types of VLSI circuit, there is no need to do initial partitioning.

Mutation:
A few genes are chosen and exchanged. But the number of bit will be changed depends on mutation probability.

Mutation probability (Pm):Mutation rate is the probability of mutation which is used calculates number of bits to be muted. The mutation operator preserves the diversity among the population which is also very important for the search. Mutation probabilities are smaller in natural population leading us to conclude that mutation is appropriately considered a secondary mechanism of genetic algorithm adoption. Individual 011101001011 and Pm = 0.25 Then we say, 3 bit will be inverted.

Cut size:
Cut size is number of edge between partitions. In the following graph total node is 4 Total edge 6 Cut size 4 www.ijctonline.com

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International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012 emerging technique. This technique has been applied to Introduction: several problems, most of which are graph related The advancement in VLSI semiconductor technology has led to because the genetic metaphor can be most easily applied a phenomenal development in Electronics Industry, leading to to these types of problems. Genetic requires more more chip complexity and higher integration. However as the memory but take less time. The main advantage of chip density increases numerous issues like ease of design, circuit partitioning using bin packing aretesting, increased delay, interconnect area optimization arise Initial partition is not required, there are no need to which need to be handled at the design stage. Improved encoding chromosome. Moreover,we can do easily physical design tools are necessary to handle these issues. multiway partitioning in many types of VLSI circuit, Circuit net list partitioning is an important step in VLSI physical there is no need to do initial partitioning. design. Solution methodology: The circuit partitioning for system on a chip (SOC) At first, the net-list is traversed in a breadth-firstintegrated circuit had become more and more complicated. search order and the cells are assigned to the chromosome This technology is very useful for IC design. Among steps in the in this order. If two cells are directly connected to each design process the circuit partitioning which is required as the other, there is a high probability that there partition bits first step in physical design has especially become very will be closed to each other in the chromosome. The BFS important. A better circuit partitioning will reduce connection sequence of the net-list will be parent 1 and any among sub-circuits and result in better routing area of layout. sequence of the net-list will be parent2. Apply crossover The partitioning will say better if reduce the interconnection operator on parent 1 and parent 2 for creates offspring. between bins. Minimization of delay due to inter connection In mutation Section, the number of bit or gene inverted between partitions and ratio-cut minimization. Efficient easily depends on mutation probability. Hence, genaration1 applied algorithms for optimal clustering to minimize delay in contain 6 individual. Count cut size in geanaration1 for digital networks were developed by Lawler at al .Kernighan and each chromosome. Take two best chromosomes for Lin proposed heuristic for two ways partitioning which was the generation 2 from generation 1. Take bins for partitioned. first iterative algorithm based on swapping of vertices. And serially gene will be inserted until the bin is not full, when first bin is full then insert second bin and so on. The Circuit partitioning consist of dividing a circuit into parts each genetic algorithm are not guaranteed to find the minimum of which can be implemented as a separate component (e.g. cost (optimum), but able to find very good solutions for a a chip, in) that satisfies certain design constraints one wide range of problem. Each generation choice to best search constraints is the area of the component. The limited chromosome (Best fitness) from previous generation for area of a component forces the designer to lay out a circuit parent. on several components. There has been a larger amount of Chromosome representation: work done in the area of circuit partitioning and clustering. In circuit partitioning, the circuit is divided into two (Bipartitioning) or more (Multi-way partitioning) parts. In each B A individual the gene is not copy two times so clustering will h F not occur. The different objectives that may be satisfied partitioning are:1. The minimization of number of cuts: C E The number of interG D connection among partitioning has to be minimized. Reducing the inter-connection not only reduce the delay but also reduce the interface between the partitioned making it easier for independent design and fabrication. It is also called min-cut problem. N O 2. Area of each partition is used as a constraint to L reduce the fabrication cost with minimum area or as a K balance constraint so that partitions are of all most equal size. Various researchers have achieved varying level of success using various optimization techniques. The current work attempts to use simple genetic J M I P algorithm with bin packing concept for multiway VLSI circuit partitioning. Because genetic algorithm is an 494 | P a g e www.ijctonline.com

Council for Innovative Research www.cirworld.com on the above circuit, the corresponding graph will be-----A B F H

International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012 Algorithm: Start Traversed the graph of corresponding circuit (BFS and Any sequence)

Select parent1 (as a BFS) and parent 2 (as a any sequence) Define crossover type, mutation probability and bin size

Apply crossover operator on parents (created offspring) P M I K Apply mutation operator on offspring (created child)

Total node 16, Pm=0.25 , Apply one point cross over, Apply crossover operation on two parents then creates offspring. Selected bit of offspring will inverted by using mutation operator. BFS A C D B O E P M N G H F J I K L DFS A C O P M J K L I N E G H F D B Parent1- A C D B O E P M N G H F J I K L Patrent2- A C O P M J K L I N E G H F D B Crossover: Offspring1- A C D B O E P M I N G H F J K L Offspring2-A C O P M J K L N G H F I D B F Mutation: Child 1-A C D B O I P M E N K H F J G L Child2- A C O P M N K L J G B F I D H E INDIVIDUAL ACDBOEPMNGHFJIKL ACOPMJKLINEGHFDB ACDBOEPMINGHFJKL ACOPMJKLNGHFIDBE ACDBOIPMENKHFJGL ACOPMNKLJG BFIDH FITNESS 10 17 16 16 15 15 15.83
N

Count fitness for each individual in generation (cut size)

Y

If optimum result is found N

STOP

Chose two best fitness chromosomes for next generation

N

If two chromosomes are equal with each other Y

AVG.COST

Chose next best chromosome (choice3) until the choice1=! choice3 and set choice2=choice3

If choice1 & choice2 are equal with previous generation choice1 & choice2 Y Change crossover boundary and mutation probability

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International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012

Experimental result & Discussion: The genetic algorithm has been used to minimize the interconnections that are the min cut problem with a balance constraint. The coding has been done using MATLAB r2012a(7.3 version).The following graph contain 16 gates and apply algorithm on the graph and get iteration results in following table. We assume that the bin size is 4. So 4 bin required for this problem. There is no possibility of the clustering; this is the special Advantage of this algorithm.

Parent1= [1 3 4 2 1 5 5 16 13 14 7 8 6 10 9 11 12]; Parent2= [1 3 15 16 13 10 11 12 9 14 5 7 8 6 4 2]; Parent1 as a BFS order and parent2 as a DFS order On the above circuit, the experimental result shown in

No.of.iteration 10

Min_cut 10 10 10 10 9 9 9 9 4 4

Avg_cut 14 13 13 13 14 13 12 12 10 10

Max_cut 19 18 18 18 21 22 19 19 18 18

2 6 8

20 30

3 4

5 7

40 50 60

15

14 13 11 12 10 9

70 80 90 100

16

The corresponding graph will be-

15

14

10

12

16

13

11 Fig.1: Plot for chromosome vs. Fitness in 10 Generation

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International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012 Fig.4: Plot for Chromosome vs. Fitness in 41:50 Generation

Fig.2: Plot for chromosome vs. Fitness in 11:20 Generation

Fig.5: Plot for Chromosome vs. Fitness in 51:60 Generation.

Fig.3: Plot for Chromosome vs. Fitness in 21:30 Generation

Fig 6: Plot for Chromosome vs. Fitness in 61:70 Generation.

Fig 7: Plot for Chromosome vs. fitness in 81:90 Generation. 497 | P a g e www.ijctonline.com

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International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012 As seen from the results in Fig.1 when increasing the no.of itaration 1:10 we get minimum fitness in first generetion that is 10 , maximum fitness with value 19 and avarage cut is 14. When the no. of iteration are 11 to 20 then the minimum fitness is same as previous itaration 1to10.But avarage fitness and max fitness are better then the previous iteration.Fig.2 reflex the each chromosome in each generation in iteration number 11 to 20.After a certain generation 41 to 50 these value reflex in the Fig.4. Here, we see minimum fitness is 9 better than the previous iteration, But max fitness and avarage fitness are increase than the previous iteration.In case of Fig.5,Fig.6,Fig.7 we see the minimum fitness is almost same but max fitness and avarage fitness are diferent from each other. After a certain generation between iteration no 81 to 90,we change the mutation probability(pm=0.125) then found optimum fitness that is 4 and avarage fitness and max fitness are better than the previous iteration, this is reflex(ietretion no 81 to 90) in the Fig.7.Minimum fitness,avarage fitness and max fitness are shown respectively in Fig.8, Fig.9, Fig.10 whose iteration number between 1to 100.

Fig.8: Plot for Generation vs. Min fitness in 100 Generation.

Conclusion:
We have followed survival of fittest of Charles Darwins theory. Main philosophy of genetic algorithm is followed to Holland. Circuit partition is one of the key areas in chip designing. The algorithm can partition circuit into a number of sub-circuits. Our method calculates the fitness value and discards solutions with low fitness value. The increase in number of crossover points does not necessarily the fitness, as the fitness achieved depends on crossover as well as mutation probability. The main advantage of circuit partitioning using bin packing areInitial partition is not required, there are no need to encoding chromosome with block number also chromosome will be encoded by gate or node name with BFS and Any sequence. Also the main superiority over circuit partitioning using GA is we can do easily multi way partitioning in many types of VLSI circuit, there is no need to do initial partitioning. Specially, in this paper find minimum cut size but not reduce the time. Fig.10: Plot for Generation vs. Max fitness in 100 Generation. 498 | P a g e www.ijctonline.com

Fig.9: Plot for Generation vs. Avg.fitness in 100 Generation.

Council for Innovative Research www.cirworld.com References:

International Journal of Computers & Technology Volume 3 No. 3, Nov-Dec, 2012

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