IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO.

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Electromechanical Diode Cell for Cross-Point Nonvolatile Memory Arrays

Wookhyun Kwon, Student Member, IEEE, Jaeseok Jeon, Louis Hutin, Member, IEEE, and Tsu-Jae King Liu, Fellow, IEEE

AbstractAn electromechanical diode nonvolatile memory cell design is proposed for implementation of compact (4F2 ) crosspoint memory arrays. The rst prototype cells are demonstrated to operate with relatively low set/reset voltages and excellent retention characteristics and are multi-time programmable (with endurance exceeding 104 set/reset cycles). Index TermsCross-bar memory, cross-point memory, electromechanical device, nonvolatile memory.

I. I NTRODUCTION LASH memory is the fastest growing memory market segment due to burgeoning demand for portable electronic devices. To date, memory cell size reduction with technology advancement has been the key to increasing storage capacity while lowering cost per bit. Fundamental scaling limitations for Flash memory cell operating voltages and the physical thickness of the tunneling dielectric layer pose a signicant challenge for continued scaling in the sub-20-nm regime, however [1]. Therefore, alternative materials and structures have been proposed to overcome the scaling limit of a conventional Flash memory cell. Various cross-point memory technologies are being pursued as potential successors to Flash memory technology because they not only allow for the most compact storage (4F2 cell layout area, where F is the minimum half pitch) but also can be fabricated using a relatively simple process that is more amenable to 3-D integration. Programmable resistance devices such as phase-change memory [2] and resistive RAM [3] have been explored for cross-point memory applications but generally require a selector device within each memory cell to reduce unwanted leakage current through unselected cells during a read operation; otherwise, the size (number of rows/columns) of the array will be severely limited, resulting in poor memory-array area efciency [4]. The selector devices require additional process steps and can signicantly reduce the cell current, resulting in slower read operation.

Fig. 1. Conceptual cross-sectional illustrations of the proposed new electromechanical diode memory cell design. (a) Reset state. (b) Set state (adhesion force + built-in electrostatic force > spring restoring force).

An electromechanical nonvolatile memory cell design that eliminates the need for a selector device, by leveraging the hysteretic behavior of a mechanical gap-closing actuator, was recently proposed and demonstrated [5]. Although this design is well suited for a cross-point array architecture, it requires separate read and write WLs, as well as an initial forming step (charging of a dielectric layer) to achieve nonvolatile operation. To overcome these disadvantages, a simpler electromechanical memory cell design is proposed and demonstrated in this work. II. M EMORY C ELL S TRUCTURE Fig. 1 illustrates the electromechanical diode memory cell concept. In the Reset state [Fig. 1(a)], the word line (WL) is physically separated from the bit line (BL) so that no current can ow between these lines through the cell. In the Set state [Fig. 1(b)], the WL is in physical contact with the BL so that a p-n diode is formed to provide a rectifying current-versusvoltage characteristic; the attractive electrostatic force exerted by the diode built-in electric eld, as well as surface adhesion force, counteracts the spring restoring force of the WL beam to keep the memory cell in the Set state. Fig. 2 shows scanning electron microscopy (SEM) images of prototype electromechanical diode memory cells fabricated using conventional planar processing techniques. The WL (100-nm-thick p-type poly-Si0.4 Ge0.6 ) is supported by siliconnitride spacers formed along the sidewalls of the BL (100-nmthick n-type poly-Si). The air gap (13 nm thick) between the WL and BL is formed by selectively removing a sacricial layer of low-temperature-deposited SiO2 (LTO) using HF vapor. As fabricated, all cells are in the Reset state.

Manuscript received September 28, 2011; revised October 20, 2011; accepted October 22, 2011. Date of publication December 8, 2011; date of current version January 27, 2012. The review of this letter was arranged by Editor M. stling. The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail: whkwon10@eecs.berkeley.edu). Color versions of one or more of the gures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/LED.2011.2174191

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Fig. 2. SEM images of fabricated prototype electromechanical diode memory cells. (a) Birds-eye view of the fabricated memory array. (b) Cross-sectional view of a cell before the sacricial oxide is removed in vapor HF to release the poly-Si0.4 Ge0.6 beam (WL). TABLE 1 EXEMPLARY MEMORY CELL OPERATING VOLTAGES

III. M EMORY C ELL O PERATION Exemplary operating voltage conditions for Set, Reset, and Read operations are listed in Table I. To cause a memory cell to be programmed into the Set state, a voltage pulse (Vset ) is applied between its WL and its BL to induce an attractive electrostatic force that is sufciently large to actuate the WL into contact with the BL. Fig. 3(a) shows how the BL current changes during a Set operation. A sudden increase in current at the pull-in voltage (Vpullin ) is seen when the WL is pulled in to the BL. Since it is an applied voltage (not current) that is required to actuate the WL, the Set current can be lowered by inserting a current-limiting resistance in series with the BL driver to reduce the energy consumed by the Set operation. From transient measurements, the set time (tset ) for a prototype cell is 2 s for a Set voltage of 14 V. In order for the Set state to be retained during a Hold operation (i.e., when there is no applied voltage), the built-in electrostatic force (Felec ), together with the surface adhesion force (Fadhesion ) in the Set state, must be larger than the spring restoring force (Fspring ) in the Set state. From nite-element method simulations [6], the values of Felec and Fspring are 70.5 and 4.22 N, respectively, for the prototype devices. The state of a cell is determined by sensing the BL current when a Read voltage is applied between its WL and its BL. If the cell is in the Reset state, no current ows through it; only leakage current (through parasitic paths) ows. If the cell is in the Set state, a much larger forward diode current ows through it. Fig. 3(b) shows measured I V curves for cells in the Set state and Reset state; very high Set/Reset current ratio (> 106 ) is seen. A key requirement for implementation of a cross-point memory array is the suppression of large sneak leakage currents through unselected cells in the array [7]. The sneak leakage currents comprise the reverse-bias p-n diode currents of programmed cells which share the same BL as the

Fig. 3. Measured operating characteristics of prototype electromechanical diode memory cells. (a) Hysteretic I V curves for Set operation (VWL = 0 V; VBL = 0 V 8 V 0 V). (b) I V curves for Read operation. (Current is plotted on a logarithmic scale in the left plot and on a linear scale in the right plot.) (c) I V curve for Reset operation of a programmed cell (VWL = 0 V; VBL = 0 8 V).

cell being read. The level of the reverse bias is one-half of the WL bias voltage (VWL ) during a Read operation, for an optimally designed sense amplier for a parallel read scheme [7].

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adhesion force. When the sum of Felec and Fadhesion becomes smaller than Fspring , the spring restoring force of the WL beam pulls it out of contact with the BL. Fig. 3(c) shows how the BL current changes during a Reset operation. A sudden decrease in current at the release voltage (Vrelease ) is seen when the WL comes out of contact with the BL. From transient measurements, the reset time (treset ) for a prototype cell is 100 ms for a Reset voltage of 15 V. The longer reset time can be explained by the contact opening model presented in [10]. The measured reliability characteristics in Fig. 4 demonstrate that electromechanical diode memory cells not only have excellent retention behavior but also have good endurance. IV. C ONCLUSION A new electromechanical diode memory cell design that is well suited to a cross-point array architecture is proposed. The rst prototype cells operate with relatively low Set/Reset voltages, have excellent retention behavior, and are multi-time programmable, so this design shows promise for compact (4F2 ) nonvolatile storage applications in the future. R EFERENCES
[1] Y. Koh, NAND Flash scaling beyond 20 nm, in Proc. Int. Memory Workshop, 2009, pp. 13. [2] H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, Phase change memory, Proc. IEEE, vol. 98, no. 12, pp. 22012227, Dec. 2010. [3] H. Akinaga and H. Shima, Resistive random access memory (ReRAM) based on metal oxides, Proc. IEEE, vol. 98, no. 12, pp. 22372251, Dec. 2010. [4] G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, Overview of candidate device technologies for storageclass memory, IBM J. Res. Develop., vol. 52, no. 4.5, pp. 449464, Jul. 2008. [5] W. Y. Choi, H. Kam, D. Lee, J. Lai, and T.-J. K. Liu, Compact nanoelectro-mechanical non-volatile memory (NEMory) for 3D integration, in IEDM Tech. Dig., 2007, pp. 603606. [6] CoventorWare Ver. 2008 (Coventor, Inc.) and Sentaurus Ver. A-2008.09 (Synopsys, Inc.). [7] A. Flocke and T. G. Noll, Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/CMOS-memory, in Proc. Solid State Circuits Conf., 2007, pp. 328331. [8] M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park, and I.-K. Yoo, 2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications, in IEDM Tech. Dig., 2007, pp. 771774. [9] D. Lee, H. Tran, B. Ho, and T.-J. K. Liu, Electrical characterization of etch rate for micro- and nano-scale gap formation, J. Microelectromech. Syst., vol. 19, no. 5, pp. 12601263, Oct. 2010. [10] B. D. Jensen, K. Huang, L. L.-W. Chow, and K. Kurabayashi, Adhesion effects on contact opening dynamics in micromachined switches, J. Appl. Phys., vol. 97, no. 10, pp. 103 535-1103 535-9, May 2005.

Fig. 4. Measured reliability characteristics of prototype electromechanical diode memory cells. (a) High-temperature (200 C) retention behavior of two cells, one in the Set state and the other in the Reset state. (b) Endurance characteristics in room atmosphere and at 25 C.

For VWL = 1.2 V, the ratio of selected Set cell current to sneak path leakage current is 300 for the prototype device, which compares well against that for a 1-D-1R cross-point memory cell [8]. With process modications to improve the quality of the poly-Si lm, it should be possible to improve this rectication ratio and to increase the forward-bias diode current. For example, the electromechanical diode reported in [9] shows far superior rectication behavior. To cause a memory cell to be erased into the Reset state, a voltage pulse is applied between its WL and its BL to counteract the built-in electrostatic force of the p-n diode and the surface