February 2009, 16(1): 8690

www.sciencedirect.com/science/journal/10058885 www.buptjournal.cn/xben
The Journal of China
Universities of Posts and
Telecommunications
A new structure of substage
in pipelined analog-to-digital converters
JIA Hua-yu (), CHEN Gui-can, ZHANG Hong
Institute of Microelectronics, Xian Jiaotong University, Xian 710049, China
Abstract
The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog
signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output
residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined
ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced
by offset of comparators decision levels. The ADC implemented in Semiconductor Manufactory International Corporation
(SMIC) 0.18 m CMOS process consumes 210 mW and occupies a chip area of 3.23.7 mm
2
.
Keywords digital correction, pipelined ADC, residue voltage, operational amplifier

1 Introduction


Many applications in digital communications and digitized
imaging require high-speed and low-power ADCs. Among
various ADC architectures, the pipelined converter is proved
to be efficient for achieving a combination of high resolution
and high speed.
In the substage of pipelined ADC, if the decision levels of
the comparators have offsets, the converting error will occur
in the next stage and the effective resolution of the converter
is reduced. The error can be eliminated by the digital
correction technique. The technique can correct the error by
reducing the residue gain, using the 1.5-bit structure and
overlapping the output codes of stages when they are added
[13].
At the same time, many digital calibration techniques are
developed to calibrate the errors of amplifier by multiplying
digital-to-analog converter (DAC) and other analog circuits of
pipelined ADC [45]. However, when these techniques are
used to calibrate the errors, there is no redundancy in the
substage of ADC. For instance, when the nonlinearity of
residue amplifier is calibrated by the signal statistics-based
digital calibration technique, the output codes of sub-ADC of
the first substage are modulated by a random sequence

Received date: 20-03-2008
Corresponding author: JIA Hua-yu, E-mail: jiahuayu@mail.xjtu.edu.cn
DOI: 10.1016/S1005-8885(08)60184-3
number [69]. Therefore, redundancy will disappear in the
stage and any error may cause its residue to exceed the
REF
V
range (
REF
V is full-scale input). If the second stage still uses
the 1.5-bit, in the next stage, the converting errors will occur
and the output residue will exceed
REF
V range.
The article presents a new structure of substage for
pipelined ADC: (1+1)-bit/stage. When the input signal of the
(1+1) bit/stage is in
REF
1.5V range, the stage can still
convert the input voltage correctly, and the output residue
voltage will be in
REF
V range. The stage produces a 3 bit
output code and can be used in combination with 1.5 bit in
pipelined ADC. The offsets of the comparators decision level
are corrected at the same time. In the article, the (1+1) bit/stage
structure is used in the second stage of a 12 bit 40 MS/s
pipelined ADC to test the functions of the structure.
2 Structure design
2.1 Structure
The residue transfer function of 2 bit substage is improved
to get new characteristics. The residue curve of 2 bit substage
whose residue gain is 2 is shown in Fig. 1(a). The vertical
jumps occur at the comparator decision levels
REF
0.5V , 0,
and
REF
0.5V + . When the input signal exceeds
REF
V range,
the output residue also exceeds
REF
V range. The ADC

Issue 1 JIA Hua-yu, et al. / A new structure of substage in pipelined analog-to-digital converters 87
output is shown above the curve for four regions of the input
(00 in the first region, 01 in the second region, etc). Within
each region, the residue crosses zero once. These zero
crossings occur at
REF
0.75V and
REF
0.25V .
A positive offset is added to the 2-bit substage. As shown in
Fig. 1(b), the decision levels of the comparators are increased
by
REF
0.25V , respectively. To reduce the range of the output
residue and obtain a symmetric curve, a
REF
0.75V decision
level is added. The changed curve is shown in Fig.1(b). The
new curve shows that when the input signal is in
REF
1.5V
range, the output residue remains within
REF
V range.
Therefore, the residue does not exceed the input range of the
next stage. The residue transfer function shows that the
structure has 3 bit output and 5 codes 000, 001, 010, 011, and
100. The resolution of the stage is (log
2
5)2.3. To distinguish
with 1.5 bit and 2.5 bit, the structure is named (1+1) bit/stage.

(a) Residue curve of 2 bit sub-ADC

(b) Residue curve of (1+1) bit/stage
Fig. 1 Residue curve
The circuit of the structure can be designed according to
the residue curve. The structure is shown in Fig. 2. The
sub-ADC with 4 comparators is used to quantize the analog
input into 3 bit digital output. The multiplying DAC (MDAC)
contains a DAC, a subtractor, and a sample-and-hold (S/H)
amplifier. The output signal of the MDAC is
REF IN 1
2( ) V V V = (1)
where 2 is the gain of the MDAC, V
IN
is the analog input
signal, and V
1
is the output signal of the DAC.

Fig. 2 Structure of (1+1) bit/stage
2.2 Output codes of ADC with (1+1) bit/stage
The (1+1) bit/stage is used after the stage whose output
residue may exceed the ADC converting range. According to
Ref. [3], the total output code of the pipelined ADC with
(1+1) bit/stage can be calculated by the equation:
1
OUT OUT
1
( )
m m
m
k
i k i i
N
D D i G
N

= =
(
=
(

[
(2)
where D
OUT
is the output code of the whole ADC, D
OUT
(i) is
the output code of the ith stage, N
i
and N
m
are the total codes
number of the ith stage and the mth stage respectively, and G
k

is the residue gain of the kth stage.
Assume that there is a three-stage converter with the stage
resolutions 4, 3, and 3, and that the second stage is the
(1+1) bit/stage structure. The residue gains of the first stage
and the second stage are reduced by two times to introduce
digital correction. This means N
1
= 16, G
1
= 8, N
2
= 4, G
2
= 2,
N
3
= 8, and G
3
= 4. (According to Ref. [3], N
2
is the number of
code before the comparator is added). By using Eq. (2), the
output code can be calculated as
OUT OUT OUT OUT
8 (1) 4 (2) (3) D D D D = + + (3)
The total output code in this case can be produced by
shifting D
OUT
(1) 3 steps and D
OUT
(2) 2 steps, without shifting
D
OUT
(3) or adding all three together. The process of
overlap-adding is illustrated in Fig. 3.

Fig. 3 Calculation of the output code of the ADC
3 Circuit design
3.1 Sub-ADC
The structure of sub-ADC is shown in Fig. 4. The sub-ADC
has 4 comparators. The positive inputs of the comparators are
connected to the analog input signal V
IN
. The negative inputs
of the comparators are connected to decision levels 0.75V
REF
,

Fig. 4 Structure of the Sub-ADC

88 The Journal of China Universities of Posts and Telecommunications 2009
0.25V
REF
,
REF
0.25V , and
REF
0.75 , V respectively. The
outputs of the comparators form the thermal codes a
0
, a
1
, a
2
,
and a
3
. The thermal codes are encoded by logic block to
produce the 3 bit binary output f
0
, f
1
, f
2
. The relationship of
input signal, thermal codes, and output of the logic block is
shown in Table 1.
Table 1 Output of the Sub-ADC
Input signal
Thermal codes
(a
3
, a
2
, a
1
, a
0
)
Output of logic block
(f
2
, f
1
, f
0
)
IN REF
0.75 V V < 0000 000
REF IN REF
0.75 < 0.25 V V V 0001 001
REF IN REF
0.25 0.25 V V V < 0011 010
REF IN REF
0.25 0.75 V V V < 0111 011
IN REF
0.75 V V 1111 100
3.2 MDAC
The gain-of-two amplification and the analog subtracts of
MADC are constructed by switched-capacitor circuits. Fig. 5
shows a simplified single-ended version of the circuits,
although the final silicon uses a more precise, fully
differential design. P
1
and P
2
are two-phased nonoverlapping
clocks. During P
1
, the bottom plates of capacitor C
1
is tied to
V
IN
to implement the bottom-plate sampling scheme, and both
of the plates of C
2
are tied to ground. During P
2
, the bottom
plate of C
2
is connected to the output of the operational
amplifier, whereas the bottom plate of C
1
is connected to
V
REF
or 0 or 0.5V
REF
according to the control signal S
1
S
5
.

Fig. 5 Schematic of the MDAC
The signals S
1
S
5
control the switch according to the
following equations:
1 3 2 1 0
S a a a a = (4)
2 3 2 1 0
S a a a a = (5)
3 3 2 1 0
S a a a a = (6)
4 3 2 1 0
S a a a a = (7)
5 3 2 1 0
S a a a a = (8)
Assume that the operational amplifier of the MDAC has a
finite linear gain of A, and the transfer function of the MDAC
during P
2
is as follows:
When
IN REF
< 0.75 V V , the bottom plate of C
1
is tied to
REF
V ,
1
RES IN REF
2 1
( )
1 1
1
C
V V V
C C
A A
= +
| |
+ +
|
\ .
(9)
When
REF IN REF
0.75 0.25 V V V < , the bottom plate of C
1

is tied to
REF
0.5V ,
1
RES IN REF
2 1
( 0.5 )
1 1
1
C
V V V
C C
A A
= +
| |
+ +
|
\ .
(10)
When
REF IN REF
0.25 0.25 V V V < , the bottom plate of C
1
is
tied to 0,
1
RES IN
2 1
1 1
1
C
V V
C C
A A
=
| |
+ +
|
\ .
(11)
When
REF IN REF
0.25 0.75 V V V < , the bottom plate of C
1
is
tied to +0.5V
REF
,
1
RES IN REF
2 1
( 0.5 )
1 1
1
C
V V V
C C
A A
=
| |
+ +
|
\ .
(12)
When
IN REF
0.75 V V , the bottom plate of C
1
is tied to
+V
REF
,
1
RES IN REF
2 1
( )
1 1
1
C
V V V
C C
A A
=
| |
+ +
|
\ .
(13)
If A and C
1
= 2C
2
, the residue transfer function
Eqs. (9)(13) can be written as
RES IN REF
2 2 V V V = or
RES IN REF
2 V V V = or
RES IN
2 V V = (14)
3.3 Operational amplifier
To achieve precise transfer performance of the (1+1) bit/stage,
the switching-capacitor circuits of MDAC need to work
precisely to follow Eq. (14). Therefore, it is important for
operational amplifier to obtain as high gain as reasonably
possible. In the article, a two-stage amplifier is presented to
achieve high gain and reasonable output voltage swing.
Fig. 6 shows the schematic of the fully differential
amplifier that includes two stages. The first stage is
folded-cascode amplifier with cascode PMOS loads to get
high gain. The second stage is common source circuit with
PMOS input device to get excellent output swing. The phase
margin is improved by two capacitors C
A1
and C
A2
between
the two stages. The common feedback circuit is not shown in
the figure.
The open-loop gain of the amplifier is 72 dB and the
unity-gain bandwidth is about 313 MHz with 1.5 pF load.

Issue 1 JIA Hua-yu, et al. / A new structure of substage in pipelined analog-to-digital converters 89

Fig. 6 Circuit of amplifier
4 Experimental results
A 12-bit 40 MS/s pipelined ADC is presented to test the
function of the new structure. In the ADC, the signal
statistics-based technique is used to calibrate nonlinearity.
Thus, the residue of the first stage may exceed the input range
of next stage. The topology of our ADC is shown in Fig. 7.
The primary parts of analog circuit blocks include the
sample-and-hold circuit, a 4-bit flash ADC, a (1+1)-bit/stage,
seven 1.5-bit/stage ADCs and a 3-bit flash ADC.

Fig. 7 Topology of the ADC
In the simulated model, a 0.4% noise is added in the first
stage of the ADC. The differential nonlinearity (DNL)
performance is shown in Fig. 8. According to Fig. 8(a), DNL
is within +0.7 0.5 LSB range when the second stage is
1.5 bit/stage. As shown in Fig. 8(b), the DNL is improved
within 0.5 LSB range when the second stage is
(1+1) bit/stage.

(a) DNL with 1.5-bit/stage

(b) DNL with (1+1) bit/stage
Fig. 8 DNL performance
Although (1+1) bit/stage has more complicated circuits
than 1.5 bit, the conversion speed is not reduced compared
with that of 1.5 bit/stage. The simulational results show that
the setting time of MDACs amplifier of (1+1) bit/stage is
6.03 ns, which entirely meets the requirements of resolution
and conversion speed. The power dissipation and die size are
15.7 mW and 0.053 mm
2
, respectively. Both of them are
approximately twice larger than those of 1.5 bit. Whereas, the
(1+1) bit/stage has more binary outputs and codes than
1.5 bit.
The ADC is fabricated in SMIC 0.18 m CMOS process.
The die size is 3.23.7 mm
2
, as shown by the die photo in Fig. 9.
The total power dissipation is 210 mW. The DNL and integral
nonlinearity (INL) of the ADC are 0.30.2 LSB and
0.40.3 LSB, respectively. And the spurious free dynamic
range (SFDR) and signal to noise and distortion ratio (SINAD)
are 70.54 dB and 64.57 dB, respectively. The testing results
show that the (1+1) bit/stage has right function and can
correct the offset of comparators decision level.

Fig. 9 Die photo
Table 2 shows a performance comparison between two
similar products and the ADC presented in this article. As can
be seen from the table, the DNL and INL of this ADC are
much higher than those of AD9235 and MAX1421. The
SINAD is higher than MAX1421 but lower than AD9235.
Therefore, the static performance of this work has advantages
and the dynamic performance should be improved in future
work.

90 The Journal of China Universities of Posts and Telecommunications 2009
Table 2 Comparison with previous work
This ADC AD9235 MAX1421
Resolution/bit 12 12 12
Conversion rate/MHz 40 65 40
Power/mW 210 300 188
SINAD/dB 64.54 70.2 63.5
DNL(max)/LSB 0.3 0.4 0.5
INL(max)/LSB 0.4 Not available 2
5 Conclusions
The article presents a new sub-ADC structure of pipelined
ADC: (1+1) bit/stage. The structure can correct the input
signal when the signal exceeds the ADCs converting range,
and the output residue is within the converting range of the
next stage. The testing results of the 12 bit 40MS/s pipelined
ADC show that the (1+1) bit/stage can convert input signal in
1.5V
REF
range correctly and produce the residue voltage in
V
REF
range.
Acknowledgements
This work was supported by the Project of Applied Materials
(XA-AM-200506).
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(Editor: ZHANG Ying)