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1V Rail-to-Rail 12-bit Pipelined ADC

Ramya Nallavelli 200501135 Naveen Yenugula - 200501152 Prof. Chetan D Parikh Evaluation Committee no: 4
Abstract The goal is to design a 1V rail-to-rail 12-bit pipelined ADC with a speed of 80Msamples/sec. The pipelined ADC consists of 5 stages; the first 4 stages resolving 2 bits each and the last stage resolving 4 bits with a provision for digital error correction. The design is done with the objective of achieving maximum Differential and Integral Non-linearity of LSB. Index Terms Pipelined ADC, Comparator, MDAC. INTRODUCTION Designing analog circuits that can operate on low supply voltages is gaining more and more importance. Many systems today utilize digital signal processing to resolve transmitted information. Therefore between the analog signal and the DSP system an analog-to-digital interface is necessary. The increasing integration level for integrated circuits has forced data converter circuits to reside on the same silicon chip with large digital circuits, by sharing the supply voltage between the Analog-to-Digital converter and digital circuit. Therefore Analog-to-Digital converter operates at the same voltage as the digital circuit. In order to achieve high transfer rates for many applications, the speed of Analog-to-Digital converter has to keep increasing. There are many ways of implementing an Analog-to-Digital convertor. The most straightforward way is to compare the sampled analog signal with different reference voltages (Flash Architecture). Because of direct comparison, for an N bit flash ADC, there will be a requirement for 2^n resistors and 2^n -1 comparators. It provides high speed operation but more components and offset for comparators are the drawbacks of the flash ADC. Next is a 2-step flash ADC. It provides decreased number of comparators, although offset tolerance is not resolved. Different architectures of ADCs are suited for different requirements. The main goal of this project is to design an offset compensated comparator with a very low propagation delay and an efficient MDAC which doesnt use a buffer. PIPELINED ADC Pipelined ADC is used for applications with high resolution at high speed. Fig.1 shows the block diagram of a pipelined ADC. It consists of 5 stages, the first four resolving 2 bits and the last stage resolving 4 bits. For each stage, the input signal is the output of previous stage except the first stage, for which the input is VIN. Every stage in a pipelined ADC contains a sub ADC, DAC, Sample and Hold, Adder and a Multiplier as shown in the Fig.1. The advantage of this architecture is its reduced complexity. With a given per stage resolution, an ADC of a given resolution can be obtained by cascading an appropriate number of identical stages. The major disadvantage of this architecture is the latency in the convertor.

Fig.1 Block Diagram of pipeline ADC The principle in pipelined ADC is to find a set of reference voltages whose sum equals the signal being converted. This is done by sequentially subtracting different reference voltages from the sample until the residue becomes zero. In pipelined ADC the residue is amplified between the stages to increase the accuracy. Therefore the output of the stage, resolving n bits per stage, is given by Vout = 2^n(Vin-Vdac) (1)

The design of pipelined ADC is divided into three parts. Opamp design Comparator design MDAC design The design of opamp is done by an Mtech student as a part of his thesis. Comparator design is done by Ramya. MDAC design is done by Naveen.

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SUB ADC The sub ADC is a flash ADC. As we are resolving 2 bits per stage, there should be 4 resistors and 3 comparators in the sub ADC. But the presence of offset in the comparator can create mismatch in the digital output. To reduce the effect of offset we have used a 2.5 bit flash ADC, which resolves 2 bits plus one redundant bit, which overlaps with the bits of next stage. It contains 6 reference levels as shown in the Fig.2.

The transfer characteristic of a comparator is similar to that of an opamp. So every design of an opamp can be used as a design for the comparator. The difference between them comes in the region of operation. Opamp is a differential amplifier. For an amplifier the output should be linear. To make an opamp act as an amplifier, it is always connected in a feedback path. Comparator is not an amplifier. So, comparator doesnt need a feedback. Whenever feedback is connected, to make the system stable the magnitude should fall below 0db when the phase is 180' [6]. So, to make the system stable, generally we will introduce a pole in the system like in a 2-stage CMOS opamp [6] as shown in the fig.5, by introducing a compensation capacitor. So in the design of comparator we can remove the compensation capacitor. So the design in fig.5 can be used as the design for comparator after removing Cc. But this circuit has a very large propagation delay.

Fig.2 2.5 Bit Flash ADC COMPARATOR Comparator is a three terminal device with two inputs (Vp, Vn) and one output (Vout). It compares the two analog inputs. The output of the comparator is high (VDD), when the difference between the inputs is positive and low (VSS), when the difference is negative. Fig.3 [5] shows the transfer characteristics of an ideal comparator. Fig.5 2-stage CMOS Opamp Compared to opamp, comparator has large BW and relatively low gain. So we have to design a comparator with large gain, low propagation delay and should be able to compensate the offset. We should also be able to build a circuit which can overcome the noise given at the input. Large gain can be achieved, but the issues come when it comes to low propagation delay and compensation of offset. Low propagation delay can be achieved by introducing latch in the design. Even the noise at the output can be removed by providing hysteresis in the latch. LATCH: Latch is the heart of the comparator when propagation delay is a major issue. High speed comparators typically have a stage of preamplification followed by a latch. The preamplifier is used to obtain higher resolution. Although the output of preamplifier is larger than the comparator input, it is still much smaller than the voltage level used to drive the digital circuitry. The latch stage amplifies the signal further and then regenerates the signal into a full scale digital signal.

Fig.3 Ideal transfer characteristics of a comparator So an ideal comparator requires a gain of infinite, which is impossible to achieve. So we have to build a comparator with a gain as large as possible. Due to device mismatches there will be some offset voltage appearing in the comparator, which will shift the transfer characteristic as show in the fig.4.[5]. Slope of the linear region gives the gain of the comparator.

Fig.4 Transfer curve of a comparator with offset voltage.

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Latches use positive feedback to accomplish the comparison of two signals as shown in the fig.6 [1]. Generally, latch has two modes of operation, track and latch. The first mode amplifies the signal and the next phase amplifies further, when positive feedback is enabled. Depending on the relative voltages of the inputs, the positive feedback enables the output to go high or low.

pipelined ADCs. The following is one of the implementation of MDAC using switched capacitors [3]. MDAC works in two phases sample and hold phase. In the sample phase, both the sampling capacitor (Cs) and the feed back capacitor (Cf) are charged by the input analog voltage as shown in the fig.8.

Fig.8 MDAC in Sample phase Fig. 6 Latch used in Comparator OFFSET COMPENSATION: Input offset voltage is the major problem in the comparator design. In applications, like high resolution ADC, large input offset cannot be tolerated. There are techniques to remove large portion of input offset. This is the main area we are concentrating. MDAC The Sample and Hold operation, the Digital to Analog conversion, the subtraction, and the amplification are all performed by a single circuit block, called a Multiplying Digital to Analog convertor. In a pipelined ADC the output of a stage depends on input voltage and output of the sub DAC. For a pipelined ADC which resolves 2 bits per stage, the output is given by Vout = 4 (Vin - Vdac) (2) Giving Cs = 3*Cf, we get As we have used a 2.5 bit flash ADC, there will be six reference levels. The output of the stage for different values of input is show in the fig.7. Vout = 4 * Vin 3 V. (4) Fig.9 MDAC in Hold phase In the hold phase Cf goes in the feedback path and Cs is charged with voltage V, depending on the ADC output. So the resulting output of the stage is obtained as Vout = Vin * ((Cs+Cf)/Cf) V * (Cs/Cf) (3)

Comparing the above equation with the fig.7, we will get the values of V, for different ADC outputs. So, different values of V are shown in the table I.
Vin 0 < Vin < 0.1875 0.1875 < Vin <0.3125 0.3125 < Vin < 0.4375 0.4375 < Vin < 0.5625 0.5625 < Vin < 0.6875 0.6875 < Vin < 0.8125 0.8125 < Vin < 1 TABLE I VALUES OF V ADC output 000 001 010 011 100 101 110 V 0 0.167 0.34 0.5 0.67 0.834 1

Fig.7 Output of a stage in a pipelined ADC So depending on the digital output produced by flash ADC we have to build a circuit which does the above operation. An MDAC contains and opamp and a set of switched capacitors. The switched capacitor technique has become standard in

Charging sampling capacitor (Cs) with the voltage corresponding to ADC output will give the desired output of a stage.

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To get these voltages (reference levels) corresponding to the ADC outputs we have to use a set of capacitors and a buffer. The use of buffer will make this model complex. So we have to come up with a model which doesnt use buffer. The above model wont be complex for a 1.5 bit flash ADC. Generally in a higher resolution pipelined stages, the sampling capacitor Cs is split into several pieces, and is independently connected to the references. Thus in a pipelined ADC which resolves n bits per stage, a generic MDAC consists of a feedback capacitor Cf, equal to C and sampling capacitor Cs constructed with 2^ n - 1 pieces, each equal to C. The following table shows the digital output and the output of each stage for a Vin of 0.35V
Stage Stage-1 Stage-2 Stage-3 Stage-4 Flash ADC TABLE II VIN = 0.36V ADC Input Digital Output 0.35 010 0.4 010 0.6 100 0.4 010 0.6 1001 MDAC Output (0.35*4) - 1 = 0.4 (0.4*4) - 1 = 0.6 (0.6*4) - 2 = 0.4 (0.4*4) 1 = 0.6

Fig.11 Digital error correction for Vin of 0.35 So the digital output for Vin of 0.35 is 010110011001. WORK TO BE DONE Design an offset compensated comparator with low propagation delay and high gain. Design an efficient MDAC without a buffer. After the design of comparator, opamp and MDAC, we will combine the three parts and design a stage and then complete pipelined ADC. ACKNOWLEDGMENT We sincerely thank Prof. Chetan D. Parikh for proposing the problem, and assisting us in clearing our doubts. REFERENCES
[1] R Jacob Baker, Li, and Boyce, CMOS: Circuit Design, Layout, and Simulation, 2nd ed., Wiley-IEEE, November 2004. [2] Cho, T. Low-Power Low-Voltage Analog-to-Digital Conversion Techniques using Pipelined Architectures , Ph.D. dissertation, Univ. California Berkeley, 1995. [3] Mikko E. Waltari and Kari A.I. Halonen, Circuit Techniques for lowvoltage and high speed A/D Convertors, Vol. 1, Nov 2002 [4] David A. Johns, Ken Martin, Analog Integrated Circuit Design, Vol 1, Wiley-IEEE, 1997. [5] Philip E. Allen, Doughlas R. Holberg, CMOS Analog Circuit Design, 2nd ed, 2006 [6] Razavi B., Introduction to Switched capacitor circuits, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001 [7] Charlie G Myers, Design of high performance Pipeline Analog-to-Digital Convertors in Low voltage Processes , Ph.D. Oregon state University, Feb 2004 [8] Giuseppe Palmisano, Gaetano Palumbo, High performance CMOS comparator Design, Vol.43, No.12, IEEE, Dec 1996 [9] Kathuria, A 12-bit pipelined A-to-D converter, B.Tech. project report, DA-IICT, May, 2007. [10] Razavi B., Design Techniques for High speed, High resolution comparators, Vol.27, No.12, IEEE, Dec 1992 [11] Mikko E. Waltari, Lauri sumanen, Tuomas Korhonen, Kari A.L Halonen, A self-calibrated Pipelined ADC with 200 MHz IF-sampling frontend, Vol. 37, 201-213, Feb 2003

DIGITAL ERROR CORRECTION Digital error correction is a block which contains a set of shift registers and adders. Most of the pipelined ADCs use digital error correction technique to reduce the accuracy requirement of flash ADC (and thus individual comparator). Each stage takes one clock to produce the digital output. So, for a pipelined ADC of n stages there will be a latency of n 1 clocks. So to get the digital output at the same time there should be n -1 shift registers at the first stage, n -2 shift registers at the second stage and so on which shifts the output at every clock. We have used a flash ADC that gives 2 bits plus one redundant bit which overlaps with the bits of other stage. So we have to add the redundant bit with the first bit of the next stage. The following figure explains the digital error correction.

Fig.10 Digital error correction Appling this to Vin of 0.35 we get

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