CMOS Design of 4-bit Carry Look Ahead Adder

Carry Look Ahead Adder CMOS design

VLSI Design Course Lab 16.502 University of Massachusetts Lowell ECE Department

Table of contents
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CMOS Design of 4-bit Carry Look Ahead Adder

1. Introduction 2. Problem Formulation 3. CMOS Design 3.1 Module -1 3.1.1 Schematic 3.1.2 Layout 3.1.3 Waveform Area 4. Delay Optimization 5. Conclusion 6. References

1. Introduction
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CMOS Design of 4-bit Carry Look Ahead Adder

Adders are of fundamental importance in a wide variety of digital systems. Many fast adders exist, but adding fast using low area and power is still challenging. The importance of a fast, low-cost binary adder in a digital system is difficult to overestimate. Not only are adders used in every arithmetic operation, they are also needed for computing the physical address in virtually every memory fetch operation in most modern CPUs. Adders are also used in many other digital systems including telecommunications systems in places where a full-fledged CPU would be superfluous. Many styles of adders exist. Ripple adders are the smallest but also the slowest. More recently, carry-skip adders, Carry-look-ahead and carry-select adders are very fast but far larger and consume much more power than ripple or carry-skip adders. The images below summarize the design and implementation of the Carry Look Ahead Adder CLA, which could be used to sum the partial products of the booth multiplier in the future. All simulations performed with Cadence IBM 90. Testing done to verify the functionality. Techniques used to improve speed performance from the gate level implementation include use of a transmission gate full adder and a CMOS implementation of the CLA logic. The worst case delay time of the test cases was reduced using these techniques. The following sections summarize the hierarchy of the Carry Look Ahead Adder.

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CMOS Design of 4-bit Carry Look Ahead Adder

2. Problem Formulation
Carry Look Ahead Adder: The figure below shows the block diagram of the CLA in two modules. A. Describes the Partial Full Adder. B. Describes the Carry Look Ahead Logic.

Partial Full Adder:

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CMOS Design of 4-bit Carry Look Ahead Adder

The rst block required for a multi-bit adder is the partial full adder. This circuit is identical to the half adder except that it has an additional input, Cin, so that a carry from a previous addition may be passed along. Furthermore, instead of a carry out, Cout, propagate (P) and generate (G) signals are produced. The logic for this schematic is as follows:
S = A B Cin P =AB G=AB

These two signals can be used to generate the carry out bit simultaneously for faster addition (see 4-bit Carry Look ahead Adder). Figure shows a gate level implementation of the full adder schematic. Note that ~G is also generated. This bit can be used instead of G to simplify some of carry look ahead logic. Figure 20 shows a symbol view of the full adder. The simulation output can be seen in Figure. All possible inputs were swept, and all outputs were correct. There is a average of propagation delay from input to sum.

Figure Partial Full Adder schematic

Figure PFA LVS

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CMOS Design of 4-bit Carry Look Ahead Adder

Figure Simulation

Carry Look Ahead Adder Logic:

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CMOS Design of 4-bit Carry Look Ahead Adder

In order to improve the speed of the adder, carry look ahead logic was employed to compute the carry bits while simultaneously computing the sum bits. This method becomes less effective as the number of bits surpasses four; therefore, a 4-bit CLA was implemented. This block can be cascaded to produce higher bit adders. This circuit consists of four full adders, which each pass propagate and generate signals to the CLA logic, which computes the carry bits and feeds them into the carry-in input of the appropriate full adders. The carry bits are generated by the CLA based on the following logic: Si = Ai Bi Ci = Pi Ci (2.4) Ci+1 = Gi + CiPi (2.1) Expanding Eq 2.1 for each carry bit of the four bit adder yields Eq 2.2-2.5, which contains only the first carry in bit and propagate and generate bits. Thus, the carry bits can be computed in parallel with the sum bits, which increases the speed of the adder compared to a ripple style adder. C1 = G0 + C0P0 (2.2) C2 = G1 + G0P1 + C0P0P1 (2.3) C3 = G2 + G1P2 + G0P1P2 + C0P0P1P2 (2.4) C4 = G3 + G2P3 + G1P2P3 + G0P1P2P3 + C0P0P1P2P3 (2.5) Observing these equations reveals that two more primitive gates are required to implement this logic: four and ve input NAND gates. These gates were constructed using the CMOS design. The schematics for the four and five input NAND gates are shown in Figure and Figure respectively. The CLA logic circuit that implements Eq 2.2-2.5 is shown in Figure 26 . All test cases were successful.

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CMOS Design of 4-bit Carry Look Ahead Adder

Figure 4 input Nand Schematic

Figure 4Input Nand Layout

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CMOS Design of 4-bit Carry Look Ahead Adder

Fig Carry C1 Schematic

Fig carry C1 LVS

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CMOS Design of 4-bit Carry Look Ahead Adder

Fig Carry C2 schematic

Fig Carry C2 LVS

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CMOS Design of 4-bit Carry Look Ahead Adder

Fig Carry C3 Schematic

Fig Carry C3 LVS

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CMOS Design of 4-bit Carry Look Ahead Adder

Fig Propagate and Generate Schematic

Fig Propagate and Generate LVS

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CMOS Design of 4-bit Carry Look Ahead Adder

Fig 4-bit Carry Look Ahead Adder schematic

Fig 4-bit Carry Look Ahead adder LVS

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CMOS Design of 4-bit Carry Look Ahead Adder

Fig 4-bit Carry Look Ahead Adder Area:

Fig 4-bit Carry Look Ahead Adder Output Waveform

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CMOS Design of 4-bit Carry Look Ahead Adder

3. CMOS Design

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CMOS Design of 4-bit Carry Look Ahead Adder

4. Delay Optimization
The delay calculation of the 4-bit Carry Look Ahead Adder Propagation Delay Rising : Tpdr = 1.2100nS - 1.0004nS = 0.2096nS=>209.6pS. Propagation Delay Falling: Tpdf = 11.18585nS - 11.0015nS = 0.18435nS => 184.35pS Average Total propagation Delay Tpd = (Tpdr + Tpdf)/2 = 196.975pS. Delay of the circuit can be minimized by using whole CMOS design for the CLA.
Fig 4-bit CLA Propagation delay:

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CMOS Design of 4-bit Carry Look Ahead Adder

5. Conclusion
A 4-bit Carry Look Ahead adder was successfully designed and simulated in an Area of 208*152um2 and power consumption of 57uW. Layout was completed for all blocks. The blocks were successfully passed DRC and LVS and post layout simulations. The speed improvements are particularly notable when there is a high degree of carry bit propagation through the circuit due to the CLA logic. The CMOS logic for the CLA reduces the area significantly compared to a gate level design and in some cases the propagation delay is reduced. This lab demonstrates the successful gate level implementation of an 4-bit Carry Look Ahead Adder.

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CMOS Design of 4-bit Carry Look Ahead Adder

6. References
[1] http://www.cadence.com/us/pages/default.aspx [2]http://ebookee.org/CMOS-VLSI-Design-A-Circuits-and-Systems-Perspective-4th-Edition_1408249.html

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