SINGLE PHASE ACTIVE FILTER USING A DSP WITH DIGITAL PWM

B Bolsens, J Van den Keybus, J Driesen, R J M Belmans

Katholieke Universiteit Leuven, Belgium.
INTRODUCTION
Several methods exist to reduce the harmonic content
of non-linear loads in the low-voltage grid to
regulatory levels [1] [2]. Active filters [3] have
received significant attention over the past years and
quite sophisticated control strategies have been
proposed in the literature, even including neural
networks [4]. However, to demonstrate the operation of
an active filter, these designs are usually overly
complex. In this paper, a small yet fully functional
single-phase active filter is proposed for educational
purposes. The compensating current is calculated in the
frequency domain using fast Fourier transform (FFT).
The complete design cycle is covered. Simplicity is
aimed at throughout the design and particular attention
is paid to the problems encountered during the practical
implementation such as synchronization and dead-time
compensation. Such problems are typical of the all-
digital approach.
CHOICE OF CIRCUIT TOPOLOGY
Basically, active power filters are of the shunt type or
series type. A series type filter cannot directly control
the grid current, but allows large voltage harmonics to
be present at its non-linear, series-connected load.
Since the filter determines the load voltage, it also
controls the resulting grid current to some extent,
depending on the non-linearity of the load.
A shunt type filter is connected across the load. The
resulting current is either sinusoidal (suppression of all
current harmonics) or entirely proportional to the grid
voltage (purely resistive behaviour, minimizing the
reactive power drawn from the grid).
The grid impedance has to be low enough for the shunt
filter to work properly. Otherwise, the active filter
current injection will significantly influence the grid
voltage. This voltage again determines the injected
current and this creates an unwanted feedback loop.
Shunt filters have several advantages:
- They can be installed without interrupting the
load.
- Their rating is usually lower than the loads.
- They can serve multiple loads.
- They can easily suppress only selected harmonics,
allowing them to coexist with fixed frequency LC
filter banks.
- The configuration is more reliable. A failed shunt
filter does not immediately affect the loads.
In general, active filters have a lower efficiency than
their passive counterparts, due to the switching losses in
the active circuit elements.
This paper is directed towards single-phase active shunt
filters. Where appropriate, extensions to three phase
filters are briefly discussed.
Figure 1: Using 2 switches and 2 capacitors
Two different topologies for a single-phase active filter
are considered. The first topology (Figure 1) has the
advantage of using only 2 switches. It is actually one
phase of a full three-phase bridge with connected neutral
conductor. The second topology (Figure 2), uses more
switches, but it has several advantages over the first
topology:
- It has three voltage output levels. This lowers
switching frequency harmonic content in the output
and reduces output filter requirements.
- The effective output switching frequency is twice
that of a single switch. This also lowers constraints
on the output filter.
- The DC link voltage is lower.
- The switch voltage is reduced.
- Only one capacitor is required.
Load
Figure 2: Using 4 switches and 1 capacitor
It is possible to use a transformer and match the output
voltage level of the active filter to the grid voltage [5].
This approach was used in some experiments and
allowed testing of the active filter with real-world
non-linear loads while still running from a reduced DC
bus voltage. The transformer is operated at frequencies
above 50 Hz and must therefore be de-rated.
OUTPUT FILTER AND DESIGN OF THE MAIN
INDUCTANCE
This section covers the design of the components of
the topology. First, the main inductance is studied.
This inductance has to be high enough, making the
ripple of the current due to the PWM voltage output
sufficiently small. Too small an inductance would
result in excessive current ripple, which, besides
aggravating current measurement difficulties, is also
not allowed to flow in the grid.
On the other hand, the high current bandwidth of the
active filter also requires the inductance to be low
enough. An inductance that is too high prevents the
filter from tracking the reference current unless an
excessive DC bus voltage is used. This DC link
voltage is equally important; it is actually the
combination of the link voltage and the main
inductance that determines the aforementioned
properties of bandwidth and current ripple.
The switching frequency determines the current ripple
to a large extent: the higher this frequency, the lower
the ripple.
The design starts with some known parameters, such
as the DC link design voltage, and the effective
switching frequency. The DC link voltage has to be
higher than the peak line voltage. Figure 2 explains
why: every switch has a freewheeling diode, and these
diodes form a full wave rectifier for the grid, thus
charging the DC link to a voltage that is nearly equal
to the peak line voltage.
To be able to calculate the highest harmonic that can be
tracked with a given DC link voltage, the worst case is
considered. When the line voltage reaches its peak value,
only a small voltage remains between this peak value
and the voltage available on the DC link. When this
voltage is entirely used to track an n-th harmonic (i.e.
bus voltage is applied permanently), the current I
n
is
given by:
h
DC
n
L n
E
U
I

=
2
(1)
I
n
is the rms value of the harmonic current of order n. E
is the rms line voltage, U
DC
is the available DC link
voltage and L
h
is the main inductance. The combined
influence of the inductance and the DC link voltage on
the current output is apparent.
When more than one harmonic current is to be injected,
the available voltage has also to be divided among all
harmonics. Note that phase differences must be
considered during a full calculation.
Until now, the switching frequency has not been
considered. The following formula gives the current
ripple I as a function of the DC link voltage U
DC
, the
instantaneous grid voltage e, the effective switching
frequency f
PWM
and the main inductance L
h
:
h
DC
DC PWM
L
e U
U
e
f
I

=
1
(2)
This formula is valid when the desired output current to
the grid is zero, i.e. the PWM output has to track the line
voltage.
When keeping U
DC
constant, it can be shown that this
equation reaches a maximum for e = U
DC
/ 2. In
practice, U
DC
is always smaller than twice the peak line
voltage, so as a worst case, we take e = U
DC
/ 2. The
following formula is derived:
h PWM
DC
L f
U
I

=
4
(3)
In the chosen topology, f
PWM
is 12.8 kHz, resulting in an
effective output switching frequency of 25.6 kHz. A
given inductance of 2 mH and a given maximum rms
current of 17.7A for the third harmonic result in a DC
voltage U
DC
(1) of 372 V. Together with f
PWM
, this gives
a ripple I of about 1.81 A
pp
for the worst case.
Since this ripple is still considerable, the active filter is
equipped with a LC filter between the output of the
converter and the grid. Figure 3 shows the filter circuit:
Load

L
h

R
C
f

Active
Filter
Grid
Figure 3: PWM Output LCR Filter
Apart from the original main inductance L
h
, there is a
damped second order system R-L
f
-C
f
. The purpose is
to provide a good suppression of the unwanted
harmonics of the PWM frequency (beginning at
25.6 kHz). The overall transfer function from e (grid
voltage) and u (active filter voltage) to the line current
i is given by:
( ) [ ]
( ) ( )
1
]
1

+ + +

\
|
+ +
=
f h f
h f
h f
f
f h
C L L s
R
L L
s L L s
R
L
s C L s e u
i
//
//
1
1 1
2
2
(4)
In the practical setup, L
h
is 2 mH, and 4 kHz is
selected as the natural frequency
n
of the filter. This
allows the active filter to compensate currents up to
the 50
th
harmonic, while providing a good attenuation
of the PWM frequency. To obtain the value of the
resistance, critical damping was taken. This gives:
L
f
= 0.2 mH
C
f
= 9 F
R = 2.3
Figure 4 illustrates the effect of the PWM output filter.
The upper curve (2) represents the current through
the main inductance L
h
, at a switching frequency of
10 kHz. The effective switching frequency is therefore
20 kHz. The lower curve (1) shows the grid current.
The switching frequency harmonics are well
suppressed without visibly affecting the bandwidth.
Figure 4: Effect of the PWM output filter
(100 s/div, 0.5 A/div)
CONTROL STRATEGY
The control problem of an active power filter is twofold:
one must have some way of determining the current
required to compensate the distorted load current and
one must regulate the DC link voltage.
The reference current is calculated using the measured
load current and voltage. Several approaches exist:
- Unity Power Factor. The instantaneous power is
calculated, and averaged over time. This way an
equivalent resistance can be calculated:

=
dt i e
dt e
R
LOAD
eq
2
(5)
Dividing the measured voltage by this resistance
and subtracting the instantaneous load current gives
the reference current i:
LOAD
eq
i
R
e
i = (6)
- The previous strategy is straightforward. However,
there is an even simpler approach [6]. A
decreasing DC link voltage indicates the active
current drawn from the grid is too low. In other
words, the value of R
eq
is too high. Instead of
calculating the power consumed by the load, one
can take the output of the DC link voltage controller
as the value of R
eq
. Both strategies considered so far
produce the behaviour of a resistor: if the grid
voltage is distorted, so will the current.
- If the filter also has to compensate reactive currents,
the above strategies fall short. The necessary 90
phase shift can be obtained by calculating the
fundamental frequency components of the voltage
using two Fourier integrals. These values are used
to calculate active and reactive reference currents.
- The use of Fourier integrals can be extended to a
complete Discrete Fourier Transform of the load
current. The fundamental frequency components of
the voltage are also calculated. The reference
current is then calculated as follows:
The DC component (I
0
) is discarded.
The 50 Hz current phasor I
1
is projected on the
50 Hz voltage phasor U
1
to yield the
instantaneous reactive current to be
compensated at fundamental frequency. The
active current component at fundamental
frequency is given by the output of the DC
voltage link controller, covering the losses in
the active filter.
All harmonic content (I
2
I
50
) gets an opposite
sign.
L
f
By performing the inverse Fast Fourier
Transform, the necessary reference current is
obtained. It compensates all reactive power,
all harmonics, and also includes the necessary
active current to keep the DC link voltage at
level. This is the strategy used in this work
(Figure x).
In three phase systems, it is possible to make use of
the rotating nature of the line voltages. We mention
the approach of the instantaneous reactive power
theory (IRPT) [7] and the method of the Synchronous
Reference Frame (SRF) [8]. The latter has the
advantage that all direct 50 Hz components are
transformed to a system where these values become dc
values. This is especially useful when PI current
controllers are used.
The primary current controller injects the reference
current in the grid. It compares the measured real
current to the reference. The difference is fed to a PI
type controller. Since all calculations take place on a
Digital Signal Processor (DSP), the controllers can be
efficiently implemented in the discrete time domain.
The secondary current controller regulates the DC
link voltage by varying the active current component
that is injected into the grid by the primary controller.
This component effectively covers the switching
losses. Practical considerations complicate the
implementation of this controller:
- When testing the secondary controller, the risk of
instability due to programming errors must be
considered because there is essentially no
maximum limit on the DC bus voltage. Unless the
DC bus is clamped by a diode and a source
capable of sinking dc power, catastrophic
breakdown may occur in such cases.
- The DC link bus must be charged to E 2 prior to
starting of the filter to avoid transient over
currents through the IGBT freewheeling diodes.
This can be accomplished using series resistors
with a bypass relay.
EXPERIMENTAL RESULTS USING DIF-
FERENT CURRENT CONTROLLERS
Description of the hardware
The hardware consists of a dSPACE DSP board
incorporating a Texas Instruments C31 master DSP
running at 60 MHz and a P14 slave DSP. It was
decided to develop a new A/D data acquisition system
to care for the required galvanic isolation. This
acquisition system is based on 12-bit serial A/D
converter chips and is connected to the C31 SPI port
that is accessible from the dSPACE board. Interface
routines are written in C and corresponding Simulink
blocks were built. There is no DSP overhead due to the
use of interrupts and Direct Memory Access (DMA).
The 2 power switch modules each contain two 27 A,
1200 V IGBTs. Control signals originate from the P14
slave processor, which is, however, not synchronized to
the C31. Experiments later showed this to be a major
problem in obtaining satisfactory performance. The
modules also include a current A/D converter that is
compatible with the acquisition system. The PWM
output filter is connected between the outputs of the
switch modules and the grid.
The load current, the converter current, the DC link
voltage and the line voltage are measured. These four
values are the inputs of the DSP system.
First approach
At first, there is no synchronisation between the C31
and the P14. The PWM frequency is set to 10 kHz. The
FFT strategy was used with a simple PI type primary
current controller.
Every program cycle, the value of i is sampled, and the
new value for u is sent to the PWM generator. This all-
digital approach can be studied using the transfer
function in the Z-domain [9] taking into account the
delays in the DSP cycle and the Zero-Order-Hold
character of the PWM output.

) 1 (
2
1

+
z
z T K
K
S

( ) 1
1
+

h
S
L
T R
h
S
z
L
T

1
z
Figure 5: First primary current controller
system transfer model
This system does not perform as expected. The problems
can be traced to the lack of synchronization between the
C31 and the P14. To investigate this, the control loop
is broken and in open-loop mode, a square wave current
of 1 A is generated. The grid connections are shorted
(E = 0 V). Errors are clearly visible in Figure 6 and can
be attributed to a corrupted current sample when the
slave DSP (P14) is putting out the sample containing
the increased voltage to change the current (flux)
through the inductor.
Due to the lack of synchronisation, a current sample is
sometimes taken right on a switching instant of the
switch module. The high dv/dt (> 10 kV/s) makes
disturbances unavoidable [10]. It is important to note
+
_
i
*
i
Controller
Ideal inverter
+ inductance
Sampling delay
u
that the lack of synchronisation is no real issue for
motor drive applications. The inductances are higher
and a single corrupted sample usually has little impact
on the current. However, in active power filters the
increased bandwidth of the current controller
combined with the relatively limited sampling rate
causes each corrupted sample to have a large effect on
the current. Feedback provides a solution but it is
useless to try and compensate a system that already
contains a large non-linearity when the feedback gain
is limited.
Figure 6: Open loop response for a square wave
showing synchronisation problems
(0.5 A/div, 2 ms/div)
Synchronisation
Synchronisation can be achieved by creating an
interrupt from the P14 Slave DSP every time it begins
a new PWM cycle. This interrupt is caught by the
main DSP system, and it allows a synchronisation of
the data acquisition and the PWM generator. The
frequency of the PWM generator has to be a multiple
of the data rate. This data rate itself has to be a
multiple of 50 Hz, because 128 samples per period of
the grid are necessary for the Fourier transform. The
result is a data rate of 6400 Hz. The PWM frequency
is 12.8 kHz.
Figure 7: Open loop response for a sine wave showing
the effect of converter dead time
(0.5 A/div, 2 ms/div)
This approach resulted in improved performance with
the same PI controller. Some problems remained
however, rendering a closed loop system still
impossible. When an open loop sinusoidal voltage was
applied, the current waveform of Figure 7 was
obtained:
The effect of synchronisation is clearly visible when
comparing Figure 6 and Figure 7. The repeating peaks
on the square wave no longer exist in the synchronised
system. But still, a noticeable distortion is visible.
This poor performance is only due to the presence of
converter dead time. During dead time, freewheeling
takes place, and this always results in a current decrease.
This is clearly visible in the figure: The current tends
faster to zero, and has difficulties getting away from
zero. To exclude the possible effect of the iron core, the
same test was run using an air coil of the same
inductance yielding the same results.
Hand-coded C-routine controller for faster loop
Finally, the whole controller was implemented in a C-
coded routine. The frequency of the DSP cycle still
remained 6400 Hz, but the current control loop was
executed twice per DSP cycle. Instead of a simple PI
controller, a second order controller was implemented:

2
) 1 (
) )( (

z
b z a z
G
( ) 1
1
+

h
S
L
T R
h
S
z
L
T

1
z
Figure 8: Second system transfer model
Converter Dead Time compensation
The effect of dead time is the loss of a certain voltage
compared to the desired PWM output voltage. This
voltage depends on converter dead time, PWM
frequency and the DC link voltage. It is given by:
PWM deadtime DC
f t U V = 4 (7)
Dead time compensation is accomplished by inserting a
fixed voltage in the output voltage, but with a sign
according to the actual direction of the current. Using
dead time compensation, together with the second order
current controller provided the desired open loop
response. The performance of the closed loop system is
shown in Figure 8.
+
_
i
*
i
Controller
Ideal inverter
+ inductance
Sampling delay
Figure 9: Total line current, active filter current and
load current response to a load transient and grid
voltage. Scale is 5A/div and 100V/div for voltage. DC
link voltage is 200V.
Also visible on this figure is the typical response time
of this strategy (Fourier Transform): during the first
grid period, samples are acquired. Then, in the second
grid period, these samples can be transformed using
Fast Fourier Transform (FFT), and the calculated
result can be Inverse Fourier Transformed using IFFT.
At the start of the third grid period, the correct
compensating current is available for the current
controllers. This process results in a typical response
time of 40 ms, visible on the figure. The initial Total
Harmonic Distortion (THD) is about 60 %. The active
filter reduces this value to 8 %.
CONCLUSION AND FUTURE RESEARCH
A simple single-phase active filter is designed and
constructed. The calculation of the compensating
current is performed using FFT and very simple
current controllers are used. A few problems were
easily solved in software and involved mainly the
synchronisation between the DSP and the PWM
generator. This synchronisation has never been a
problem before when implementing drive systems on
the same platform.
The final single-phase design supports a grid voltage
up to 230 V rms and output current up to 17.7 A rms
(for a single harmonic). The resulting THD when
compensating a square wave load current is below
8 %.
Future research will focus on the improvement of the
current controller, possibly leading to an
implementation using hysteresis band current
regulators such as the one described in [11].
ACKNOWLEDGEMENT
The authors are grateful to the Belgian Fonds voor
Wetenschappelijk Onderzoek Vlaanderen and the
Belgian Instituut voor de aanmoediging van Innovatie
door Wetenschap en Technologie in Vlaanderen (IWT)
for their financial support of this work. B. Bolsens is a
research assistant of the F.W.O.-V. and J. Van den
Keybus holds a research scholarship of the IWT.
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