High Resolution PID Controller Using Tapped Delay Line

ABSTRACT
Monitoring and controlling of temperature in multi core and many core SOC is an important criteria in present technology. Thus need for thermal management has tremendously increased over time. Proportional-Integral-Derivative (PID) controllers is one such controller for temperature control. It is widely used in automation control systems. A PID is the most commonly used feedback controller and offers a good solution to many practical control problems in small as well as large distributed systems. A 16 bit PID controller using tapped delay line is developed. The controller parameters are designed using MATLAB/SIMULINK. The circuit under test is a PID
Controller circuit implemented on a low-cost FPGA from XILINX.A multiplierless digital PID controller is design and implementation on FPGA device. It is more compact, power efficient and provides high speed capabilities and hardware compatibility for implementing on FPGA. The proposed method is based on Distributed Arithmetic (DA) architecture which utilizes less resources.
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CONTENTS
Page No DECLARATION ACKNOWLEDGEMENT ABSTRACT LIST OF FIGURES LIST OF TABLES LIST OF ABBREVATIONS CHAPTER 1: INTRODUCTION 1.1 1.2 1.3 1.4 1.5 Problem statement Objective of The Project Applications Software and hardware used Organization of The Report i ii iii vi vi vii 1 2 2 2 3 3
CHAPTER 2: LITERATURE SURVEY 2.1 2.2 2.3 Background Types of PID Controller Tunning of PID Controller 4 4 7 8 9 10 13 15 16 16 17
CHAPTER 3: PROPOSED PID CONTROLLER 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Control Terms Mathematical Analysis Distributed Arithmetic Distributed Arithmetic in LUTs Tapped Delay Line Pulse Width Modulation Peltier Cooler
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CHAPTER 4: TOOLS USED 4.1 Xilinx ISE 9.2i 4.2 Introduction to VHDL 4.3 Matlab R2010 a 19 20 21
CHAPTER 5: SYNTHESIS OF PID CONTROLLER USING XILINX ISE9.2 5.1 Design Flow 23 24
5.2 Synthesis Report CHAPTER 6: RTL SCHEMATICS 6.1 6. 2 RTL Schematic of Top Module RTL Schematic of PID Controller
36 37 37 38 39 40 41
6. 3 RTL Schematic of PWM Module 6. 4 RTL schematic of proposed PID control with PWM CHAPTER 7: SIMULATIONS AND RESULTS 7.1 Hardware Setup and Xilinx XC3S400 Board 7.2 Waveforms
CHAPTER 8: CONCLUSION AND SCOPE FOR FUTURE WORK REFERENCES APPENDIX A APPENDIX B APPENDIX C
43 44 46 53 58
LIST OF FIGURES
Fig No Fig.1.1 Fig.2.1 Fig.2.2 Fig.3.1 Fig.3.2 Fig.3.3 Fig.3.4 Fig.3.5 Fig.3.6 Fig.5.1 Fig.6.1 Fig.6.2 Fig 6.3 Fig 6.4 Fig.7.1 Fig.7.2 Fig.7.3 Fig.7.4 Fig 7.5 Titles Block diagram of sensor and controller Control Loop Employing a PID Control Function Block diagram of PID Controller Architecture of the Proposed PID Controller Distributed Arithmetic with Four Constant Multiplicands Four-Bit Multiplication with Constant Coefficient Tapped Delay Line Input analog signal and a sawtooth waveform Peltier cooler module synthesis design flow Top Module PID Controller Module PWM Module Proposed PID control with PWM module Hardware setup and Spartan board Simulation result of PID controller Simulation results of PWM wave Temperature vs Duty cycle curve Device summary report of PID controller Page No 1 5 6 8 13 15 16 17 18 23 36 37 37 38 40 41 41 42 42
LIST OF TABLES
Table No. 3.1 3.2 3.3 Titles Effects of increasing a given term in a closed-loop system ROM Table Module Parameters and Types of Peltier Cooler Page No. 10 12 18
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LIST OF ABBREVATIONS
DA Distributed arithmetic DTDL Digital Tapped Delay Line FPGA LUT NOC PID PWM ROM SOC TEC Field Programmable Gate Array Look Up Table Network On Chip Proportional Integral Derivative Pulse Width Modulation Read Only Memory System On Chip Thermoelectric Cooler
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High Resolution PID Controller Using Tapped Delay Line
CHAPTER 1
INTRODUCTION
More densely packed transistors within the chips are generating more heat per unit area. Monitoring and controlling the temperature of the chip using digital sensors has the advantages of having less chip area ,less power consumption and cost effective over analog sensors . The basic principle block diagram of Digital temperature sensor and control is as shown in figure 1.1.
Figure 1.1: Block diagram of sensor and controller The principle of temperature sensor is based on the relationship between temperature and propagation delay of the transistor. Propagation delay of the transistor varies with temperature of the chip, which is captured by master counter and LUT. Proportional(P), Integral(I) and Derivative(D) controller is used to maintain the temperature of the die to a setpoint by varying width of the Pulse Width Modulator signal. The PWM signal changes the direction of current in Peltier cooler to control the temperature.
M.Tech ( Dept of E&C)
1.1 Problem Statement

Requirement is to design and implement a high Resolution PID Controller using Tapped delay line for temperature control with less hardware utilization.
1.2 Objective of the Project

In multi core and many core embedded system-on-chip (SoC) millions of transistors are integrated on a single chip to add more features to the system. In the same way Network on Chip (NoC) configuration has more number of Intellectual property (IP) cores, which are integrated and are controlled by a router. In NoC the load is not equally distributed at each part or to each IP core hence thermal management is more concern in such systems because the heat increases rapidly where work load is more and it is less at where work load is less. The testing of such systems through software Built-In-Self-Test (BIST) becomes inconvenient due to its speed restrictions and more power consumption. Hence the proposed Distributed Temperature Sensor and Control can be used as hardware Built-In-Self-Test (BIST).The main Objective of this project is to design and implement a Temperature sensor and control on FPGA. The whole project is divided into two parts, temperature sensing and temperature controlling. In this report temperature controlling is discussed using PID Controller. Proportional-Integral-Derivative
(PID) controllers are widely used in automation control systems. A PID is the most commonly used feedback controller and offers a good solution to many practical control problems in small as well as large distributed systems. The PID controller compares the measured process value with a reference setpoint value. The difference or error is then processed to calculate a new process input, which will try to adjust the measured process value back to the desired setpoint. In this project we have designed PID controller based on Distributed Arithmetic (DA) architecture and output of the PID controller is then applied to the Pulse Width Modulator (PWM).PWM drives the peltier cooler which controls the temperature of the FPGA.
1.3 Applications
Monitoring and controlling the temperature of the chip without using on board temperature sensor finds its uses in many industrial applications. The demand for small sized, high accuracy chips has grown over time, and with that, the demand for low consumption smart temperature M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line sensors has also grown. The distributed temperature sensor serve as the core circuit for highly sophisticated temperature sensitive systems like CPU, CCD Cameras. PID is an important tool for the embedded real-time digital controls designer. The PID is used extensively in fields such as servo/motor control, robotics, temperature control, and power electronics. More recently, the PID has been adopted into variant forms that incorporate adaptive and non-linear controllers. The major requirement for current applications is low cost, high resolution, and wide measurement.
1.4 Software and Hardware Used

Xilinx 9.2 is used as VHDL design entry tool, schematic, and also for simulation, synthesis and implementation. Spartan 3 XC3s400-4pq208 FPGA kit is used as target device for implementation. Matlab/Simulink is used for tuning of the PID parameters. Peltier cooler to control the temperature
1.5 Organization of the Report

This dissertation consists of 8 chapters including the present introductory one. Chapter 2 consists of background of PID controller explanation. Chapter 3 explains block diagram and the architecture of PID controller. Chapter 4 deals with the introductory part of tools used. Chapter 5 explains the program flow, modern developments and the detailed hardware report i.e. Synthesis Report. Chapter 6 covers the RTL schematics obtained by the Xilinx Synthesis tool. Chapter 7 shows the Simulations Results and the waveforms obtained using different tool. Chapter 8 concludes the dissertation with suggestions for further work.
CHAPTER 2
LITERATURE SURVEY
2.1 Background
The PID controller enjoys the honor of being the most commonly used dynamic control technique. Over 85% of all dynamic (low-level) controllers are of the PID variety. The basic idea is that the controller reads the system state by a sensor. Then it subtracts the measurement from a desired reference to generate the error value e(t). The error will be managed in three ways, to handle the present, through the proportional term, recover from the past, using the integral term, and to anticipate the future, through the derivate term. Early feedback control devices implicitly or explicitly used the ideas of proportional, integral and derivative action in their structures. However, it was probably not until Minorskys work on ship steering published in 1922, that rigorous theoretical consideration was given to PID control [5]. This was the first mathematical treatment of the type of controller that is now used to control almost all industrial processes. Initially, digital PID controller was designed by using microprocessors or
microcontrollers. This method has a disadvantage in speed of operations because the operations depend on software which has a sequence of instructions and commands which needs many machine cycles to execute. [6]
2.2 Types of PID Controller

There are different types of Controllers like On-Off Controller, Proportional controller , PID Controller etc, each having its own advantages. An on-off controller is the simplest form of speed control device. The output from the device is either on or off, with no middle state. An onoff controller will switch the output only when the speed crosses the setpoint. Proportional controls are designed to eliminate the cycling associated with on-off control. A proportional controller decreases the average power supplied to the motor as the speed approaches setpoint. This proportioning action can be accomplished by turning the output on and off for short time intervals. PID controller combines proportional control with two additional adjustments, which helps the unit automatically compensate for changes in the system. The proportional, integral and M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line derivative terms must be individually adjusted or tuned to a particular system using trial and error[14]. It provides the most accurate and stable control of the three controller types, and is best used in systems which have a relatively small mass, those which react quickly to changes in the energy added to the process. Systems that are subject to wide temperature cycling need proportional control. Depending on the precision required, some processes may require full "PID" control. It provides the most accurate and stable control of the three controller types, and is best used in systems which have a relatively small mass, those which react quickly to changes in energy added to the process. It is recommended in systems where the load changes often, and the controller is expected to compensate automatically due to frequent changes in setpoint, the amount of energy available, or the mass to be controlled. FPGA-based digital PID controller has the advantage over PID designed using microprocessor or microcontroller[3]. The operations on FPGA are hardware compatible. FPGA has no problem in timing sequence, thereby allowing many processes to go at the same time with the system delay reduced as minimum as possible. However, this method still needs multipliers for computation. These multipliers lead to decrease in the speed of processing time because of delay produced by the stages and it occupies more silicon area [7].
Figure 2.1: Control Loop Employing a PID Control Function
High Resolution PID Controller Using Tapped Delay Line For the temperature control application, the desired temperature is called the setpoint (SP). The input to the process is called the manipulated variable (MV). The difference between the temperature measurement and the setpoint is the error (e) PID control is useful in systems where the load is continually varying and the controller is expected to respond automatically to frequent changes in setpointor deviations of the regulated variable. The FPGA-based controllers offer advantages such as high-speed computation, complex functionality, real-time processing capabilities and low power. An FPGA chip consists of a lot of memory blocks, referred to as Look-Up Tables (LUT) [13], which can be utilized to improve performance of certain operations such as multiplication while the trade-off for speed can be tolerated. In this project, we study the design of an efficient PID controller using the distributed arithmetic (DA) scheme. Based on the LUT scheme, the proposed PID controller reduces the cost of the FPGA design by enabling the chip to accommodate more logic and arithmetic functions while requiring less power consumption[4][16].
Figure 2.2 : Block diagram of PID Controller Also, due to the flexibility of using look-up tables in FPGAs. This is due to the fact that custom-made logic can generally outperform the general purpose microcontrollers [8]. This has been designed using distributed arithmetic (DA). M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line DA hides the explicit multiplications by ROM look-ups hence it reduces the area by 50% in the hardware design. The excess of temperature on the FPGA is modulated by pulse width modulation (PWM) whose duty cycle depends on the output of the PID controller. The PWM signal drives the Peltier cooler which is mounted on the FPGA. Peltier cooler is also known as thermoelectric cooler (TEC), works on the principle of Peltier effect i.e. whenever current flows through the peltier cooler (conductor) depending on the change in polarity of the current flow, the junction of two conductors will either release or absorb heat.
2.3 Tuning a PID (Three-Mode) Controller

Tuning a temperature controller involves setting the proportional, integral, and derivative values to get the best possible control for a particular process. If the controller does not include an auto-tune algorithm or the auto-tune algorithm does not provide adequate control for the particular application, the unit must then be tuned using a trial and error method. Implementations using a single architecture, shared to perform different PID controllers, have also been considered [9]. Since with FPGAs we are not constrained to a specific number of bits to represent data such is the case when using e.g. microcontrollers, the implementation of PID controllers using FPGAs may permit to use in embedded systems more efficient, robust and stable controllers and auto-tuning schemes[10].
Chapter 3
PROPOSED PID CONTROLLER

The PID algorithm, now widely used in industrial process control, has been recognized and employed for many pneumatic controllers. Fig3.1 shows the architecture of the proposed PID controller using Tapped delay line.
Figure 3.1: Architecture of the Proposed PID Controller This has been designed using distributed arithmetic (DA). DA hides the explicit multiplications by ROM look-ups hence it reduces the area by 50% in the hardware design.
3.1 Control Terms

Proportional Control Proportional control applies a corrective term proportional to the error. The proportionality constant ( ) is known as the proportional gain of the controller. As the gain is
increased, the system responds faster to changes in setpoint, and the final (steady-state) error is smaller, but the system becomes less stable, because it is increasingly under-damped. Further increases in gain will result in overshoots, ringing, and ultimately, undamped oscillation. Integral Control Although proportional control can reduce error substantially, it cannot by itself reduce the error to zero. The error can, however, be reduced to zero by adding an integral term to the control function. An integrator in a closed loop must seek to hold its average input at zero (otherwise, its output would increase indefinitely, ending up in saturation or worse). The higher the integral gain constant, , the sooner the error heads for zero (and beyond) in response to a
change; so to set KI too high is to invite oscillation and instability. Derivative Control
Adding a derivative term proportional to the time derivative, or rate-of-change, of the error signal can improve the stability, reduce the overshoot that arises when proportional and/or integral terms are used at high gain, and improve response speed by anticipating changes in the error. Its gain, or the damping constant, , can usually be adjusted to achieve a critically damped response to changes in
the setpoint or the regulated variable. Too little damping, and the overshoot from proportional control may remain; too much damping may cause an unnecessarily slow response. The designer should also note that differentiators amplify high frequency noise appearing in the error signal
A proportional controller (P) will reduce the rise time and will reduce, but never eliminate, the steady state error. A proportional-integral (PI) controller will eliminate the steady state error, but it may make the transient response worse. A proportional-integral-derivative controller (PID) will increase the system stability, reduce the overshoot, and improve the transient response. Effects of increasing a given term in a closed-loop system are summarized in Table 3.1.
High Resolution PID Controller Using Tapped Delay Line Table 3.1 : Effects of increasing a given term in a closed-loop system Gain Constant Kp Ki Kd Rise Time Decreases Decreases Little Change Increases Increases Decreases Overshoot Settling Time Little Change Increases Decreases Steady Error Decreases Eliminate Little Change State
3.2 Mathematical Analysis

The analytical equation of PID controller is given by U(t) = Where, Kp = proportional gain Kd = derivative gain e = error in % of full scale range Ki = integral gain PI(0) = value of integral term at t=0 + edt + (de/dt) + PI(0) (3.1)
U(t) is the control signal and e is the control error .The reference value is also called the setpoint. The control signal is thus a sum of three terms: the P-term (which is proportional to the error), the I-term (which is proportional to the integral of the error), and the D term (which is proportional to the derivative of the error). The controller parameters are proportional gain integral gain and derivative gain . The controller can also be parameterized as
=
where
+
is called integral time and
(3.2) derivative time. The proportional part acts on the
present value of the error, the integral represent and average of past errors and the derivative can be interpreted as a prediction of future errors based on linear extrapolation.
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High Resolution PID Controller Using Tapped Delay Line Laplace transform of equation (3.1) will result in,
(3.3)
Also the transfer function of PID controller is
(3.4)
Where, D(S) is transfer of PID controller. Transforming equation (3.4) into digital domain gives the transfer function of digital PID controller.
! " !
(3.5)
Equation (3.5) can be realized to,
# !'
! % $ & $ !' $ &
(3.6)
And the coefficients () , (* and (+ can be given as
(3.7)
(3.8)
=
and
(3.9) are proportional, integral and derivative parameters respectively
Where
of digital PID controller and T is sampling period. Taking Inverse z- transform of equation (3.7) and deriving it into difference equation it will give:
-' = - '
' +
'
'
(3.10)
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High Resolution PID Controller Using Tapped Delay Line Rom table is prepared using equation(3.10) for different values of controller parameters. The value for these parameters is selected by proper tuning of the controller co-efficients. Assume the values which are given below = 0101 = 5 = 0010 = 2 = 0001 = 1 T = 0001 = 1 Let us find (. , () and (* values From Eq (3.7) Constant values
The values
(. = 0111, () = 1000 and (* = 0001

Table 3.2: Rom Table
Using these, values in ROM are given in the following table
Address
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Values in ROM
0 1 (* (* +1 () () +1 () + (* () + (* +1 (. (. +1 ( . +( * (. +(* +1 (. +() (. +() +1 (. +() +(* (. +() +(* +1
After Substituting (. () (* 0000 0001 0001 0002 FFF8 FFF9 FFF9 FFFA 0007 0008 0008 0009 FFFF 0000 0000 0001
The size of ROM is very important for high speed implementation as well as area efficiency. ROM size grows exponentially with each added input address line.
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3.3 Distributed Arithmetic

Distributed arithmetic is a method of performing multiplication by distributing the operation over many LUTs. Figure 3.2 shows a four product MAC function that uses sequential shift and add to multiply four pairs, and then sums their partial product to obtain a final result. Each multiplier forms partial products by multiplying the multiplicand by one bit of the input data (multiplier) at a time, using an AND gate.
Figure 3.2: Distributed Arithmetic with Four Constant Multiplicands The multiplierless distributed arithmetic (DA)-based technique has gained substantial popularity, due to its high-throughput processing capability and increased regularity, results in cost-effective and area-time efficient computing structures. The main operations required for DA-based computation of inner product are a sequence of lookup table (LUT) accesses followed by shift accumulation operations of the LUT output. DA-based computation is well suited for FPGA realization, because the LUT as well as the shift-add operations, can be efficiently mapped to the LUT-based FPGA logic structures. At the end of the process, each partial product result of each input bit is summed prior to the final scaling accumulator stage, which performs a shift-accumulate. The distributedM.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line arithmetic circuit simultaneously performs four multiplications and sums the results when all of the products are completed. The scaling accumulator shifts the sums of partial products according to the appropriate number of bits and accumulates the result to provide the final multiplier output. Consider the following Eq (3.11) inner product of two M dimensional vectors K and 0, where K is a constant vector, 0 is the input sample vector, and 1 is the result.
4"
1= 2
35
3 03
%.
Using B-bit 2's complement binary representation scaled such that |03 | < 1 produces
8"
03 = 73 + 2 73'
'5
"'
%.
Where 73' are the bits (0 or 1) of 03 , 73 is the most significant bit, and 73 (8 ) is the least significant bit. Thus
4" 8" 3
1= 2
35
973 + 2 73'
'5
"'
%. %
by rearranging summation terms

4" 8" 3 73 ;" 3 73' : "'
1= 2
35
+ 2 92
'5 35
%. <
The computation in distributed arithmetic is represented by Eq (3.14) shown above. The values of 73' are either 0 or 1, resulting in bracketed term having only
'
possible values. Since
K is a constant vector, the bracketed term can be Pre computed and stored in memory using either lookup table (LUT) or ROM. The lookup table is then addressed using the individual bits of input samples, 0 with the final result y computed after B cycles, regardless of lengths of
vectors K and 0. This leads to a multiplier less realization of vector multiplication.
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3.4 Distributed Arithmetic in LUTs

Figure 3.3 shows how to implement distributed arithmetic using LUTs. The combined product and adder tree are reduced for the LUT implementation. LUT contains the sums of constant coefficients for all possible input combinations to the LUT. The sums of the bits from the LUTs are added together in the scaling accumulator and shifted by the appropriate weights.
Figure 3.3: Four-Bit Multiplication with Constant Coefficients Steps to be followed for the computation of inner product using Distributed Arithmetic: 1. Depending on the length of inner product, store all pre-computed partial products in LUT (ex: if M=3, 2+ =8 partial products should be stored). 2. Use LSB of all inputs as address, to get partial product from LUT. 3. All inputs are right shifted to get the new address and corresponding partial product from LUT. 4. The partial product obtained in step 1 is right shifted and added with partial product obtained in step 2 and store the result in register. 5. Repeat the step 2 to get new partial product which is added with right shifted value of register and store the result in same register. Repeat step 4 until MSB of inputs reaches LSB position. 6. Use LSB of all inputs as address to get partial product from LUT which is subtracted with right shifted value of register and store the result in same register which gives inner product.
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3.5 Tapped Delay Line

New digital tapped delay line (DTDL) systems have been designed and demonstrated which leverage low cost FPGA and data converter technology. A tap refers to the extraction of the signal at a certain position within the delay-line. Fig 3.4 shows a tapped delay line for a delay of M1 samples. The tap may be interpolating or non-interpolating, and also may be scaled and implements a shorter delay line within a larger one. Digital methods mainly use tapped delay line configurations such as Vernier delay line. Vernier Delay Line is one of the digital method to achieve nanosecond resolution by using a Vernier method. Two delay element chains are used in Vernier Delay Line. The delay time Tds of delay element in lower delay chain is greater than that Tdf in upper delay chain
Figure 3.4: A delay line tapped after a delay of M1 samples.
3.6 Pulse Width Modulator (PWM)

Pulse-width modulation (PWM), or pulse-duration modulation (PDM), is a commonly used technique for controlling power to inertial electrical devices, made practical by modern electronic power switches. The PWM signal is a signal that is either high or low with no intermediate values. The average value of voltage (and current) fed to the load is controlled by turning the switch between supply and load on and off at a fast pace. The longer the switch is on compared to the off periods, the higher the power supplied to the load is. The PWM switching frequency has to be much faster than what would affect the load, which is to say the device that uses the power. The term duty cycle describes the proportion of 'on' time to the regular interval or 'period' of time. A low duty cycle corresponds to low power, because the power is off for most of the time. Duty cycle is expressed in percent, 100% being fully on. The main advantage of PWM is M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line that power loss in the switching devices is very low. Pulse-width modulation uses a square wave whose pulse width is modulated resulting in the variation of the average value of the waveform. If we consider a square waveform f(t) with a low value ymin, a high value ymax and a duty cycle D the average value of the waveform is given by:
>= 1
(3.15 )
Figure3.5: Input analog signal and a sawtooth waveform are driven in a comparator
The simplest way to generate a PWM signal is the interceptive method, which requires only a saw tooth or a triangle waveform (easily generated using a simple oscillator) and a comparator. When the value of the reference signal (sine wave in figure) is more than the modulation waveform, the PWM signal (magenta) is in the high state, otherwise it is in the low state.
3.7 Peltier Cooler

Peltier cooler is also known as thermoelectric cooler (TEC), works on the principle of Peltier effect i.e whenever current flows through the peltier cooler (conductor) depending on the change in polarity of current flow, the junction of the two conductors will either release or absorb heat. Temperature compensation is carried out using peltier cooler which is mounted on FPGA. Figure 3.6 shows the model of peltier cooler and table 3 gives module parameters and types peltier cooler. M.Tech ( Dept of E&C)
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Figure 3.6 : Peltier Cooler
Table 3.3 : Module Parameters and Types of Peltier Cooler
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Chapter 4
TOOLS USED
The tools used for the project are Xilinx ISE 9.2i for writing and synthesizing the VHDL code, ISE simulator for simulating the code and MATLAB R2010a to test the tuning functionality of proposed architecture.
4.1 Xilinx ISE 9.2i

Xilinx integrated tool environment is a software tool which enables to write HDL code and synthesize and optimize to various required user constraints and simulate and implement on different FPGA and CPLD devices. ISE simulator key features include multi-threaded compilation, post processing capacity, TCL scriptable GUI and batch mode simulation run and Standalone waveform viewing capability. It also include debug capabilities like waveform tracing, waveform viewing, HDL source debugging, power analysis and optimization and memory editor for viewing and debugging memory elements. There are in-built Xilinx simulation libraries, so additional mapping or compilation not required. ISE 9.2i includes new key ease-of-use features to speed engineers through the design flow faster with easily visible implementation results each step of the way. ISE 9.2i design tools radically improve utilization of computing resources, providing with greater design flexibility, enabling to design with higher density FPGAs with widely available 32-bit version of Windows XP. Improvements in ISE 9.2i design tools permit greater flexibility for designs which leverage embedded processors. Tighter integration with Xilinx integrated development environment for embedded design, the Platform Studio, allows embedded users improved access to the design closure tools residing within the ISE design environment. All versions of ISE design tools software packages support Windows XP, Windows XP x64, Windows Vista Business, and Linux Red Hat Enterprise WS. The standard design flow for Xilinx consists of the following three major steps. The entire design implementation flow is run simply by selecting the desired result in the Xilinx graphical User Interface (GUI). The tools automatically determine which programs and files are needed to bring the appropriate output up to date. M.Tech ( Dept of E&C)
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Design Entry and Synthesis

In this step of the design flow, to create the design using a Xilinx-supported schematic Editor, a Hardware Description Language (HDL) for text based entry or both. Use an HDL for text-based entry; it must synthesize the HDL file into an industry standard Electronic Data Interchange Format (EDIF) file. To use the Xilinx Synthesis Technology (XST) tool, a Xilinx specific NGC net list file is created, which can be converted to an EDIF file.
Design Implementation
Implementing stage converts the logical design file format, such as EDIF, that is created in the design entry or synthesis stage into a physical file format. The physical information is contained in the Native Circuit Description (NCD) file. Then to create a bit stream file from these files and optionally program a PROM for subsequent programming of the device. Design Implementation begins with the translating and then mapping of a logical design file to a specific generation device. It is complete when the physical design is successfully routed and a bit stream is generated.
Design Verification
Using a gate level simulator, to ensure that the design meets your timing requirements and functions properly. Verification can be done by simulation which involves testing the design using software models. It is most effective when testing the functionality of the design and its performance under worst-case conditions. In circuit verification can be performed by downloading the design to the device using Xilinx iMPACT Programming software. Design verification can begin immediately after design entry and can be repeated after various steps of design implementation.
4.2 Introduction To VHDL

HDL- Hardware Description Language is a computer aided design (CAD) tool for the modern design and synthesis of digital systems. The recent steady advances in semiconductor technology continued to increase the power and complexity of digital systems due to their
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High Resolution PID Controller Using Tapped Delay Line complexity, systems cannot be realized using discrete integrated circuits (ICs) they are usually realized using high density programmable gate arrays (FPGAs) and require sophisticated CAD tool. HDL is an integral part of such tools HDL offers the designer a very efficient tool for implementing and synthesizing designs on chip The designer uses HDL to describe the system in a computer language that is similar to several commonly used software languages, such as C. Debugging the design is easy, since HDL packages implement simulators and test benches. The two widely used hardware description languages are VHDL and Verilog. Since each language is equally implemented in both academia and industry [11]. VHDL is acronym for Very-high-speed-integrated-circuit Hardware Description Language. VHDL was introduced as a means to provide a detailed design specification of a digital circuit, with little thought given to how a circuit might be implemented based on that specification (the assumption was the requirements in the source file would be captured as a schematic by a skilled engineer). At the time, the creation of a design specification, although involved, was almost trivial in comparison to the amount of work required to translate the specification to a schematic-based structural description needed to fabricate a device. Over several years, it became clear that a computer program could be written to automatically translate a VHDL behavioral specification to a structural circuit, and a new class of computer programs called synthesizers began appearing. A synthesizer produces a low-level, structural description of a circuit based on its HDL description.
4.3 MATLAB R2010a

MATLAB, which stands for matrix laboratory, is a state-of-the-art mathematical software package, which is used extensively in both academia and industry. It is an interactive program for numerical computation and data visualization, which along with its programming capabilities provides a very useful tool for almost all areas of science and engineering. Unlike other mathematical packages, such as MAPLE or MATHEMATICA, MATLAB cannot perform symbolic manipulations without the use of additional toolboxes. It remains however one of the leading software packages for numerical computation. MATLAB can be used in a wide range of M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line applications, including signal and image processing, communications, control design, test and measurement, financial modelling and analysis, and computational biology. Simulink is software for modelling, simulating, and analyzing dynamic systems. Simulink enables you to pose a question about a system, model it, and see what happens. With Simulink, you can easily build models from scratch, or modify existing models to meet your needs. Simulink supports linear and nonlinear systems, modelled in continuous time, sampled time, or a hybrid of the two. Systems can also be multirate having different parts that are sampled or updated at different rates. Thousands of scientists and engineers around the world use Simulink to model and solve real problems in a variety of industries. Simulink can use MATLAB to: Define model inputs. Store model outputs for analysis and visualization. Perform functions within a model, through integrated calls to MATLAB operators and functions.
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Chapter 5
Synthesis Of PID Controller Design Using XILINX ISE 9.2i

5.1 Design Flow
Figure 5.1: Design Flow
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High Resolution PID Controller Using Tapped Delay Line SYNTHESIS: After validating the RTL model, logic synthesis is performed to map the RTL code to logic gates in the targeted foundry library. Logic synthesis is the process of automatically converting a given RTL Hardware Descriptive Language of a design to technology gates; based on some design constraints. The result of the synthesis process is a net list composed of registers, combinational logic, interconnects and macro cell instantiations. The tool used in this step is XILINX ISE 9.2i synthesized net list should be simulated using the same test vectors used to validate the RTL. In addition, after creating the source files verifies the designs behavior with simulation and add constraints. The design is ready to be synthesized and implemented. XILINX ISE 9.2i Project Navigator) is used for post-simulation purpose. RTL Schematic and Technology Schematic can be generated and viewed in the synthesizer. Moreover, post-synthesis simulation will give layout of the design. The design is then Synthesis with XST (default) followed by translate and mapping. The logic gates of the controller are placed and routed on the CLBs of the FPGA. Following PAR, additional verification can be done on the design before creating a configuration files for downloading to the FPGA. RTL code is synthesized, implementation and generated bit file using XILINX ISE 9.2i. Then this bit file is loaded into the FPGA.
5.2 Synthesis Report

Release 9.2i - xst J.30 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s --> Reading design: pid_control.prj
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High Resolution PID Controller Using Tapped Delay Line TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ===================================================================== * Synthesis Options Summary *
===================================================================== ---- Source Parameters Input File Name Input Format Ignore Synthesis Constraint File ---- Target Parameters M.Tech ( Dept of E&C)
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: "pid_control.prj" : mixed : NO
High Resolution PID Controller Using Tapped Delay Line Output File Name Output Format Target Device ---- Source Options Top Module Name Automatic FSM Extraction FSM Encoding Algorithm Safe Implementation FSM Style RAM Extraction RAM Style ROM Extraction Mux Style Decoder Extraction Priority Encoder Extraction Shift Register Extraction Logical Shifter Extraction XOR Collapsing ROM Style Mux Extraction Resource Sharing Asynchronous To Synchronous Multiplier Style M.Tech ( Dept of E&C) : pid_control : YES : Auto : No : lut : Yes : Auto : Yes : Auto : YES : YES : YES : YES : YES : Auto : YES : YES : NO : auto
26
: " pid_control " : NGC : xc3s400-4-pq208
High Resolution PID Controller Using Tapped Delay Line Automatic Register Balancing ---- Target Options Add IO Buffers Global Maximum Fan out Add Generic Clock Buffer(BUFG) Register Duplication Slice Packing Optimize Instantiated Primitives Use Clock Enable Use Synchronous Set Use Synchronous Reset Pack IO Registers into IOBs Equivalent register Removal ---- General Options Optimization Goal Optimization Effor Library Search Order Keep Hierarchy RTL Output Global Optimization Read Cores Write Timing Constraints Cross Clock Analysis M.Tech ( Dept of E&C) : Speed :1 : pid_control.lso : NO : Yes : All Clock Nets : YES : NO : NO
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: No
: YES : 500 :8 : YES : YES : NO : Yes : Yes : Yes : auto : YES
High Resolution PID Controller Using Tapped Delay Line Hierarchy Separator Bus Delimiter Case Specifier Slice Utilization Ratio BRAM Utilization Ratio Verilog 2000 Auto BRAM Packing Slice Utilization Ratio Delta :/ : <> : maintain : 100 : 100 : YES : NO :5
===================================================================== HDL Synthesis Report Macro Statistics # ROMs 16x16-bit ROM # Adders/Subtractor 15-bit adder 15-bit subtractor 16-bit adder 16-bit subtractor # Counters 16-bit up counter # Registers 1-bit register 16-bit register M.Tech ( Dept of E&C) :1 :1 :5 :1 :2 :1 :1 :1 :1 : 53 : 49 :4
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High Resolution PID Controller Using Tapped Delay Line # Comparators 15-bit comparator greater 15-bit comparator less 16-bit comparator greater :3 :1 :1 :1
===================================================================== * Advanced HDL Synthesis *
===================================================================== Loading device for application Rf_Device from file '3s400.nph' in environment C:\Xilinx92i. INFO:Xst:2506 - Unit <rom> : In order to maximize performance and save block RAM resources, the small ROM <Mrom_d_mux0000> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
===================================================================== Advanced HDL Synthesis Report Macro Statistics # ROMs 16x16-bit ROM # Adders/Subtractors 15-bit adder 15-bit subtractor 16-bit adder 16-bit subtractor # Counters 1 6-bit up counter M.Tech ( Dept of E&C) :1 :1 :5 :1 :2 :1 :1 :1 :1
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High Resolution PID Controller Using Tapped Delay Line # Registers Flip-Flops # Comparators 15-bit comparator greater 15-bit comparator less 16-bit comparator greater : 115 : 115 :3 :1 :1 :1
===================================================================== Final Register Report Macro Statistics # Registers Flip-Flops : 120 : 120
===================================================================== * Final Report *
===================================================================== Final Results RTL Top Level Output File Name Top Level Output File Name Output Format Optimization Goal Keep Hierarchy Design Statistics # IOs : 36 : pid_control.ngr : pid_control : NGC : Speed : NO
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High Resolution PID Controller Using Tapped Delay Line Cell Usage : # BELS # # # # # # # # # # # GND INV LUT1 LUT2 LUT3 LUT4 LUT4_D LUT4_L MUXCY VCC XORCY : 443 :1 : 46 : 41 : 72 : 33 : 22 :2 :2 : 133 :1 : 90 : 120 : 36 : 17 : 51 : 16 :1 :1 : 35 : 34 :1
# FlipFlops/Latches # # # # FD FDE FDR FDS
# Clock Buffers # BUFGP
# IO Buffers # # IBUF OBUF
===================================================================== M.Tech ( Dept of E&C)

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Device utilization summary: --------------------------Selected Device : 3s400pq208-4 Number of Slices: Number of Slice Flip Flops: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: Number of GCLKs: --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. ===================================================================== TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | 143 out of 3584 120 out of 7168 218 out of 7168 36 36 out of 1 out of 141 8 25% 12% 3% 1% 3%
-----------------------------------+------------------------+-------+ Clk M.Tech ( Dept of E&C) | BUFGP | 120 |

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High Resolution PID Controller Using Tapped Delay Line -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design Timing Summary: Speed Grade: -4 Minimum period: 10.459ns (Maximum Frequency: 95.611MHz) Minimum input arrival time before clock: 5.947ns Maximum output required time after clock: 7.165ns Maximum combinational path delay: No path found Timing Detail: All values displayed in nanoseconds (ns) ===================================================================== Timing constraint: Default period analysis for Clock 'clk' Clock period: 10.459ns (frequency: 95.611MHz) Total number of paths / destination ports: 5186 / 137 ------------------------------------------------------------------------Delay: Source: Destination: Source Clock: Destination Clock: Data Path: M.Tech ( Dept of E&C) 10.459ns (Levels of Logic = 19) XLXI_34/up_limit_1 (FF) XLXI_34/pwmn (FF) clk rising clk rising XLXI_34/up_limit_1 to XLXI_34/pwmn
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High Resolution PID Controller Using Tapped Delay Line Gate Cell:in->out Net
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------Total 10.459ns (6.374ns logic, 4.085ns route) (60.9% logic, 39.1% route) ===================================================================== Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Total number of paths / destination ports: 492 / 116 ------------------------------------------------------------------------Offset: Source: Destination: Destination Clock: Data Path: Gate Cell:in->out 5.947ns (Levels of Logic = 2) rst (PAD) XLXI_34/up_limit_15 (FF) clk rising rst to XLXI_34/up_limit_15 Net
---------------------------------------- -----------IBUF:I->O 53 0.821 2.312 rst_IBUF (rst_IBUF) 16 0.551 1.237 XLXI_34/up_limit_or000094
LUT4:I0->O (XLXI_34/up_limit_or0000) FDR:R 1.026
XLXI_34/up_limit_0
---------------------------------------Total 5.947ns (2.398ns logic, 3.549ns route) (40.3% logic, 59.7% route) M.Tech ( Dept of E&C)
34
High Resolution PID Controller Using Tapped Delay Line ===================================================================== Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Total number of paths / destination ports: 1 / 1 ------------------------------------------------------------------------Offset: Source: Destination: Source Clock: Data Path: Gate Cell:in->out 7.165ns (Levels of Logic = 1) XLXI_34/pwmn (FF) pwm_out (PAD) clk rising XLXI_34/pwmn to pwm_out Net
---------------------------------------- -----------FDR:C->Q OBUF:I->O 1 0.720 0.801 XLXI_34/pwmn (XLXI_34/pwmn) 5.644 pwm_out_OBUF (pwm_out)
---------------------------------------Total 7.165ns (6.364ns logic, 0.801ns route) (88.8% logic, 11.2% route) ===================================================================== CPU : 4.93 / 5.04 s | Elapsed : 5.00 / 5.00 s Total memory usage is 180452 kilobytes Number of errors : Number of warnings : Number of infos : 0 ( 0 filtered) 0 ( 0 filtered) 1 ( 0 filtered)
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CHAPTER 6
RTL SCHEMATICS
The RTL Schematics are shown below. Fig 6.1 shows the RTL Schematic of the TOP Module, Fig 6.2 Shows the RTL Schematic of the PID Controller module, Fig 6.3 Shows the RTL Schematic of the PWM module, Fig 6.4 Shows the RTL Schematic of Proposed PID Controller for Temperature Control Module,
6.1 RTL Schematic of Top Module
Figure 6.1 : Top Module
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6.2 RTL Synthesis result of PID controller
Figure 6.2 : PID Controller Module
6.3 RTL Synthesis result of PWM Module
Figure 6.3: PWM Module
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6.4 RTL schematic of proposed PID control with PWM
Figure 6.4: Proposed PID control with PWM module
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Chapter 7
RESULTS AND SIMULATIONS

The figure below shows the hardware setup and the waveforms of the proposed PID controller for temperature control. The fig 7.1 shows the hardware setup of the project, which shows the Spartan3 Board. The Project is implemented on the Spartan3 board and the results are displayed on the Seven Segment display. A separate VHDL code is written for the Seven Segment display. The fig 7.3 shows the simulation result of PID controller and fig 7.4 shows the simulation result of pwm wave. Fig 7.5 shows the duty cycle of the pwm wave with Temperature curve. From this curve it is concluded that as the temperature increases the load driving the FPGA or die must increase the On period to bring back the temperature to normal. The fig 7.6 shows the design device summary of the proposed PID controller.
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7.1 Hardware Setup and Xilinx XC3S400 Board
Figure 7.1 : Hardware setup of the Project
Figure 7.2 : Spartan 3 XC3S400 Board used for Implementation M.Tech ( Dept of E&C)
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7.2
Waveforms
Figure 7.3: Simulation result of PID controller
Figure 7.4: Simulation results of PWM wave
41
Figure 7.5 : Temperature vs Duty Cycle curve
Figure 7.6 : Device summary report of PID controller
42
Chapter 8
CONCLUSION AND SCOPE FOR FUTURE WORK

PID is implemented using Distributed Arithmetic which reduces the silicon area used by 50%. Also implementing PID controller on FPGA features high processing speed, accuracy, power, compactness, and cost improvement over other digital implementation techniques and hardware compatibility for implementing on FPGA. FPGA has another advantage of less design cycle time for the controller rather than using other methods. Proposed design is described using VHDL language, simulated using ISE simulator, synthesized in Xilinx ISE 9.2 tool and implemented on Spartan 3 FPGA kit.
FUTURE SCOPE
Due to the use of Distributed Arithmetic algorithm, the number of PID controllers on single FPGA chip can be increased immensely.
Co-design Implementation of Controllers

Important and evolving aspect of FPGA based control is the concept of hardware software co-design using FPGA. in which a microprocessor/ microcontroller is embedded in an FPGA. Control algorithms that require a large number of computationally involved operations like matrix manipulations cannot be effectively implemented on a single microprocessor based set up, as the microprocessor gets bogged down while performing these operations. It is in this regard that the parallel architecture of the FPGA can be exploited to develop a matrix coprocessor for performing these computations, while the general purpose microprocessor that was embedded in the chip can be used to perform other operations.
43
REFERENCES
[1] Joao Lima, Ricardo Menotti, Joao M. P. Cardoso, and Eduardo Marques A Methodology to Design FPGAbased PID Controllers . 8th Oct IEEE International Conference 2006. [2] Anthony Cataldo, Low-priced FPGA options set to expand Electronic Engineering Times Journal,N 1361, PP 38-45, USA 2005. [3] Franklin, G.F., J.D. Powell and M.L., Workman1990.Digital Control of Dynamic Systems :Addison-Wesley Publishing Company. [4] Sorawat Chivapreech, Surapan Yimman, Chusit Pradabpet and Kobchai Dejhan, FPGABased Multiplier Less Digital PID Controller Using Distributed Arithmetic, ACIAR05 International Conference , Bangkok , Thailand. [5] Minorsky (1922) Directional stability of automatically steered bodies, Naval Eng., 34, p.284. [6] EamonNeary Mixed-Signal Control Circuits Use Microcontroller for Flexibility in
Implementing PID Algorithms,Analog Dialogue 38-01, January 2004.
J. Am. Soc.
[7] Martin Hellmann (2001, March). Fuzzy LogicIntroduction.[Online] http://www.fpk.tuberlin.de/~anderl /epsilon/fuzzyintro4.pdf [2006, March 20].
[8] W. Wolf, Computers as Components: Principles of Embedded Computing System Design,San Francisco, Morgan Kaufman, 2001. [9] W. Zhao, B.H. Kim, A.C. Larson and R.M. Voyles, FPGA Imple-mentation of ClosedLoop Control System for Small-Scale Robot, in Proceedings Intl Conference on Advanced Robotics (ICAR05), v. 1, 2005
44
High Resolution PID Controller Using Tapped Delay Line [10] A peled and B. Liu. A New Hardware Realization of Digital Filters. IEEE Trans.ASSP-22, pp.456-462, Dec1974 [11] Charles H Roth, Jr. Digital System Design Using VHDL, Brooks/Cole, 1998. [12] National Instruments: http://www.ni.com. FPGA based control: Millions of transistors at you command, 2004. [13] Diligent, Inc., Diligent Spartan-3 System Board, June,2004. BOARD-brochure.pdf. [14] Vikas Gupta, K. Khare and R. P. Singh Efficient fpga implementation of 2 order digital controllers using matlab/Simulink
[15] K.J. Astrom and B. Wittenmark, Computer Controlled Systems, PrenticeHall,
nd
New Jersery,USA 1997 [16] Ian Grout Digital Systems Design with FPGAs and CPLDs, Elsevier (Newnes press) publications,2008,chapter-10 ,pp 661-700. 2009.
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APPENDIX A
DEVICE DETAILS
Spartan-3 trainer Development Board (MXS3MB-0207-003-IM) provides an easy to use development platform for realizing various designs around SPARTAN-3 FPGA.
Figure A1: Block Diagram M.Tech ( Dept of E&C)

46
FEATURES
Figure A.1 shows the SPARTAN-3, which includes the following components and features:
SPARTAN-3 FPGA: 400 k logic cell SPARTAN -3 FPGA in PQ208 Plastic Quad Flat Package (MXS3FK-PQ208-IM) Three families Spartan 3 /Spartan 3L/Spartan 3 XA. Very low cost, high-performance logic solution for high-volume, consumer oriented applications. Densities as high as 74,880 logic cells. Three power rails for core (1.2V), I/Os (1.2V to 3.3V) and Auxiliary purposes (2.5V). 326 MHz system clock rate. 90 nm process technology.
*Select IO Signaling. Up to 784 I/O pins. 622 Mb/s data transfer rate per IO. 18 single-ended signal standards.
* Logic Resources Abundant Logic cells with shift register capability. Wide Multiplexers. Fast look-ahead carry logic. Dedicated 18 x 18 Multipliers.
*SelectRAM Hierarchical Memory. Up to 1,872 Kbits of total block RAM. Up to 520 Kbits of Distributed RAM.
*Digital Clock Manager (up to 4DCMs) Clock skew elimination. Frequency synthesis High resolution phase shifting.
47
High Resolution PID Controller Using Tapped Delay Line * Eight global clock lines and abundant routing. Seven Segment Display: Six-character multiplexed seven-segment LED display. Serial Interface: One RS-232 channel using MAX3223, 9 pin two channel serial interfaces. DB9 9-pin female connector (DCE connector). RS-232 transceiver/level translator using MAX3223 in SSOP package. Uses straight-through serial cable to connect to computer or workstation serial port. LCD Interface: - 16 Character/ Digit 2 Row LCD. Traffic Light Control Interface:-16 green LEDS, 8 Red LEDS, 4 Yellow LEDS. Traffic Light Interface module will be connected using 60 pin Connector (J5).
* RTC: A Real Time Counter. * Analog Interface: 12 bit AD7891 ADC and 12 bit AD7541 DAC. Analog Input Eight channels using ADC using AD7891, (500Ksps, 12 bit). Analog Output- Two channels using Two DACs-AD7541. (12 bit, 100 ns conversion time) * DIP Switches: 16 DIP switches. * LEDs: 23 onboard LEDS 16 output LEDs (OL 0 OL 15). Done LED.(DONE) 6 Power ON LEDs (LED12VN, LED12V, LED5V, LED3.3V, LED2.5V, LED1.2V).
* Push Button Switches: 16 momentary-contact push button switches in 4x4 matrix. * User selectable configuration modes - Boundary scan, Master serial. * User selectable Interface hardware Traffic Light, RTC, ADC-DAC. * Free IOs: 34 pin FRC Connector (J7) provided for free I/Os. * Clock Oscillator: 4 MHz crystal clock oscillator. Socket for an auxiliary crystal oscillator clock source. * JTAG port: JTAG download cable (parallel III) interface. M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line * Power Supplies: 5 volts regulated power supply provided along with the board. On board 3.3V, 2.5V, 1.2V regulators. FPGA supplies viz. Vccint (1.2V) & Vcco (3.3V) are generated on board
Figure A.2 Photograph of Spartan-3 FPGA kit
SEVEN SEGMENT LED DISPLAY

SPARTAN-3 -IM has a Six multiplexed seven segment .Each individual character has a separate cathode control input. To light an individual signal, drive the individual segment control signal High along with the associated cathode control signal for the individual character. The control signal is high, enabling the control inputs for the left-most character. The segment control inputs, A through G and DP, drive the individual segments that comprise the character. A High value lights the individual segment, a Low turns off the segment.
49
FigureA.3 Seven Segment Display
Types of the seven segment displays

Common Cathode Display: In this type of display the cathode of all the LEDs are tied together and the anode terminals decides the status of the LED, either ON or OFF. To turn ON the LED i.e. segment value of driven segment should be 1 and 0 for turn OFF.
Figure A.4 Common Cathode Display Common Anode Display: In this type of display all the anode terminals of LEDs are tied together and the cathode terminals decide the status of the LED either ON or OFF. To turn ON the LED i.e. segment value of driven segment should be 0 and 1 for turn OFF.
50
Figure A.5 Common Anode Display
CONSOLIDATED UCF FOR THE COMPLETE BOARD

Clock and Reset net "CLK_4M" Loc= "p181"; net "CLK_OPT" Loc= "p180"; net "RESET" Loc= "p182"; Input Switches net "IL<0>" net net net net net net net net net net net net net net net
"IL<1>" "IL<2>" "IL<3>" "IL<4>" "IL<5>" "IL<6>" "IL<7>" "IL<8>" "IL<9>" "IL<10>" "IL<11>" "IL<12>" "IL<13>" "IL<14>" "IL<15>"
Loc= "p57"; Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc=
"p52"; "p51"; "p50"; "p48"; "p46"; "p45"; "p44"; "p43"; "p42"; "p40"; "p39"; "p37"; "p36"; "p35"; "p34";
51
High Resolution PID Controller Using Tapped Delay Line Test LEDs net "OL<0> net net net net net net net net net net net net net net net Display net net net net net net Seven Segment Interface net "SEGA" net "SEGB" net "SEGC" net "SEGD" net "SEGE" net "SEGF" net "SEGG" Loc= "p144"; Loc= "p143"; Loc= "p141"; Loc= "p140"; Loc= "p139"; Loc= "p138"; Loc= "p137";
"DIS<0>" Loc= "DIS<1>" Loc= "DIS<2>" Loc= "DIS<3>" Loc= "p97"; "p100"; "p101"; "p102"; "OL<1> "OL<2> "OL<3> "OL<4> "OL<5> "OL<6> "OL<7> "OL<8> "OL<9> "OL<10>" "OL<11>" "OL<12>" "OL<13>" "OL<14>" "OL<15>"
Loc= "p68"; Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc= Loc=
"p67"; "p65"; "p64"; "p63"; "p62"; "p61"; "p58"; "p80"; "p79"; "p78"; "p77"; "p76"; "p74"; "p72"; "p71";
"DIS<4>" Loc= "p132"; "DIS<5>" Loc= "p133";
net "SEGDP" Loc= "p135";
52
APPENDIX B
Digital Temperature Sensor And Control

Figure B.1 shows the schematic diagram of the digital temperature sensor and control. PID Controller is used to control the temperature of the device to a required setpoint. In the below schematic the PID controller is designed using DA arithmetic given in figure 3.1.
Figure B.1: Proposed PID Controller for Temperature Control
The basic digital Temperature Sensor consists of ring oscillator with delay line, counters, LUTs and display. The delay line is a temperature sensing element, which is made up of inverters. The xorcy gate is used as a inverter in delay line. There are 109 xorcy gates are used to get total delay of 250ns. A ring oscillator is a chain of an odd number of XORCY inverter whose output is connected back to the input. At normal temperature the frequency of the ring oscillator is close to the on board crystal clock frequency. As delay changes with temperature, which alters the frequency of oscillator. This change is captured by counter which works on the master clock frequency. M.Tech ( Dept of E&C)
53
ring
High Resolution PID Controller Using Tapped Delay Line Counters plays an important role in Distributed temperature sensor. There are two counters are required for the temperature measurement. 1. Master counter 2. Cycle counter A 20 bit master counter is designed to capture the propagation delay of the ring
oscillator, which works on the rising edge of the on board crystal clock of 4MHz. A 13 bit cycle counter is used to reduce the no of logic gates in the ring oscillator. The advantage of having cycle counter in the temperature sensor is, reduced area and better resolution. The temperature sensing element is made up of 109 XORCY logic gates which are distributed on FPGA by manually Placing a gate in CLB and routed to cover the entire FPGA. The seven segment display of the FPGA is used to display the count value which is proportional to the temperature or by preparing the LUT we can directly display the temperature. Refresh block reads the counter at regular time interval by enabling the read signal of the counter. The count value from the counter output is subtracted with the lower limit of the step value. The pseudo code for the subtractor is as below. Pseudo Code For Subtractor: process(clk) begin sub_res1<=step - manp; if rising_edge(clk) then temp<= temp+1; end if; if (temp="0000000000001110") then step<="0000011011100100"; sub_res1<=step - manp; en1<='1'; else en1<='0'; end if; M.Tech ( Dept of E&C)
54
High Resolution PID Controller Using Tapped Delay Line if (temp="0000000000001111") then en2<='1'; else en2<='0'; end if; if (temp="0000000000010000")then temp<="0000000000000000" end if; end process; sub_res<=sub_res1; enpwm<=en1; enpid<=en2; In this code the manipulated value is subtracted from the step value. The reset signal to the PID and PWM is generated in the same code. At every 15th cycle PWM is enabled and at 16th cycle PID is enabled. Pseudo Code For PID: delay_element_16bit XLXI_16 (.clk(clk), .input1(stepin[15:0]), .rst(rst), .output1(XLXN_37[15:0])); piso1 XLXI_17 (.c(clk), .clr(rst), .par_in(XLXN_37[15:0]), .ups(XLXN_56), .sload(load), . ser_out (pisout)); rom XLXI_21 (.a0(piso2out), .k1(dff2out), .k2(dff1out), .k3(pisout), .clk(clk), M.Tech ( Dept of E&C)
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High Resolution PID Controller Using Tapped Delay Line .d(XLXN_57[15:0])); accumulator XLXI_22 (.clk(clk), .clr(rst), .rom_out(XLXN_57[15:0]), .q(accout[15:0])); piso2 XLXI_23 (.c(clk), .par_in(accout[15:0]), .ups(XLXN_55), .load_s(load), .ser_out(piso2out)); regout XLXI_24 (.clk(clk), .input1(accout[15:0]), .rst(rst), .output1(rgout[15:0])); GND XLXI_27 (.G(XLXN_56)); GND XLXI_28 (.G(XLXN_55)); FDR XLXI_32 (.C(clk), .D(dff1out), .R(rst), .Q(dff2out)); defparam XLXI_32.INIT = 1'b0; FDR XLXI_33 (.C(clk), .D(pisout), .R(rst), .Q(dff1out)); defparam XLXI_33.INIT = 1'b0; The above code is a pseudo code of PID controller using distributed arithmetic obtained from the schematic of the proposed work as shown in figure B.1. The output from the subtractor is fed to the register of the PID controller which is of 16 bits. Followed by piso where all the bits from the register are serially outputted using piso. These output bits are delayed using tapped delay line which gives two tapped delayed outputs. The output from piso along with two tapped M.Tech ( Dept of E&C)
56
High Resolution PID Controller Using Tapped Delay Line delay forms the 3 inputs for the ROM, one more input to the ROM is provided by serially outputted value from the previous output and accordingly from the LUTs the output is generated and fed to the accumulator where the new value is added with accumulator. The output from accumulator is provided to piso which in turn one of the input to ROM. The final computed value is stored in the register. Pseudo Code For PWM: process(clk) begin if rst='1' then dutycycle<=pidin; pwm_limit<="0000000000000000"; pwm<='0'; else pwm_limit<=pwm_limit+1; if(pwm_limit<=dutycycle)then pwm<='1'; else pwm<='0'; if(pwm_limit="0000000011110000")then pwm_limit<="0000000000000000"; end if; end if; end if; end process; Output from the PID register is fed to the PWM which decides the duty cycle of pwm wave. The pseudo code for pwm is as given above. The output of pwm is driven by the peltier cooler.
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APPENDIX C
The project work is submitted as a journal paper entitled Sensor less Distributed Temperature Sensor & Control Using FPGA has been published by International Journal of Engineering and Innovative Technology (IJEIT) Florida, volume 1 issue 5, May 2012 .
58
tion delay of logic gates. The relationship follows: system design is presented in section II, section III describes the implementation of system on FPGA, the simulation results and conclusion is presented in section IV and V respectively. II System Design
between temperature and propagation delay is
"
The conceptual block diagram of distributed temperature sensor on FPGA is as shown in fig 2.The sensor is composed of two counters and a ring oscillator with 109 EX-OR (XORCY) as the inverter chain. The deviation from previous results published in [1] using inverters as a delay line, the logic gates are not evenly distributed on the FPGA which has less resolution. We attribute this by XORCY logic gates as a inverter chain which can be
FPGA CLBs Temperature Sensor LUT Display
Where is the effective load capacitance of XORCY gate, is the mobility and is the threshold voltage. The thermal characteristics of threshold voltage is given by = Where, (2)
is propagation constant. According to the above equations, mobility and threshold voltage decreases with increase in temperature. From equation(1) as mobility and threshold voltage decreases the propagation delay becomes prominent. By this change in the propagation delay, the composed block and look up table reads the rise in temperature. The frequency of the ring oscillator is #
Ring Oscillator
Counter
Fig 2:Block diagram of temperature sensor. : RTL schematic of implementation
where, N is the no of inverters in the delay line and is the propagation delay of each gate. Process of Controlling the temperature can be obtained by closed loop circuit using a PID controller. PID controller offers better flexibility for temperature controlling to a set point and it maintains very tight temperature stability.

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ABSTRACT