BASIC ELECTRICAL ENGINEERING

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1.0 CIRCUIT ANALYSIS

This topic will cover two methods of circuit analysis which are:a) Kirchoffs Current Law (KCL) b) Kirchoffs Voltage law (KVL) 1.0.1) Kirchoffs Current Law (KCL) Kirchoffs current law states that the algebraic sum of the current at a node/junction in a network at any instant of time is zero. KCL may be expressed mathematically as:-

i
j 1

Where ij represents current in the jth element and n is the number of elements connected to the node k. This means that the algebraic sum of the currents meeting at a junction is zero. If the current s entering the node are taken as positive, the currents leaving the node are negatives, or vice versa. The KCL maybe thought of to be a consequence of the conservation of electric charge- charge cannot be created nor destroyed but must be conserved.

i1
i5
i4

i2

i3

Figure 1 Application of KCL KCL equation for Fig. 1 above can be expressed as:-

i1 i2 i3 i4 i5 0
By rearranging the equation, the equation for node k can be rewritten as:-

i3 i4 i1 i2 i5
With KCL, it is obvious that elements in series carry the same current value.

i1 i 2
I1 I2 I3

i 2 i3

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1.0.2) Kirchoffs Voltage Law (KVL)

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Kirchoffs voltage law states that at any instant of time the sum of voltages in a closed circuit equals to zero. KVL may be expressed mathematically as:-

v
j 1

Where vj represents the individual voltage in the jth element around the closed circuit having n elements. If the voltage drop from the positive polarity to the negative polarity is assigned as positive sign, then the voltage rise from the negative polarity to the positive polarity is assumed as negative, or vice-versa. KVL is a consequences of the fact that no energy is lost or created in an electric circuit. It is our choice whether to apply KVL clock-wise or anti clock-wise. As we go round the loop, it is also our choice to add the voltage drops ( and subtract voltage rise) or add the voltage rise (and subtracts voltage drop). Both methods are correct. However, usually going clock-wise is chosen and voltage drop in elements is set as negative values; meaning that any voltage drop in the closed circuit is subtracted.
+V1+V2-

10 V

KVL direction 5 V

-V3+

Figure 2 Application of KVL By applying KVL onto the closed loop in Fig. 2, the equation below is obtained:-

10V V1 V2 5V V3 0
By rearranging the equation, the equation for the closed circuit can be rewritten as:-

5V V1 V2 V3
With KVL, it is obvious that elements in parallel connection have the same voltage drop across them.

BASIC ELECTRICAL ENGINEERING

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+ V1 -

+ V2 -

+ V3 -

V1 V2

V 2 V3

1.1) Series and Parallel connection:1.1.1) Series Connection For impedances that is connected in series, addition of the impedances can be calculated by adding each of the impedance.

R1

R2

R3

RTOTAL R1 R2 R3
1.1.2) Parallel Connection For impedances that is connected in parallel, addition of the impedances must be calculated by using parallel concept from right to left part of the circuit. Normal addition cannot be used.

R1

R2

1 RTOTAL
1 RTOTAL

1 1 R1 R2

RTOTAL

R1 R2 R1 R2 RR 1 2 R1 R2

BASIC ELECTRICAL ENGINEERING

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1.2) Current Divider Rule When a current has to be divided among various resistors connected in parallel, the current is divided by using the current divider rule:-

IT I1 R1 R2 I2

I T I1 I 2
I1 R2 IT R1 R2

I2

R1 IT R1 R2

1.3) Voltage Divider Rule When a voltage has to be divided among various resistors connected in series, the voltage is divided by using the voltage divider rule:-

+ V1+ V R1 R2 + V2 -

V V1 V2
V1 R1 V R1 R2

V2

R2 V R1 R2

BASIC ELECTRICAL ENGINEERING

Tutorials 1. Determine the following values

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I2
10

10

10V
a.

+ VR1 I1

10V
b.

I1

3 5 1

+ VR1 -

20

15

24

20V
c.

I1
5

I2
100

+ VR1 -

2.2k

50k

12k

10k

5V
d.

+ I1 VR1 -

I2
4.7k

1k