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Sample-and-Holds

David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu)

University of Toronto

slide 1 of 18
D.A. Johns, K. Martin, 1997

Sample-and-Hold Circuits
Also called track-and-hold circuits Often needed in A/D converters Conversion may required held signal Alsoreduces errors due to different delay times Errors in Sample-and-Holds Sampling pedestal or Hold Step errors in going from track to hold should be signal independent for no distortion Signal feedthrough should be small during hold Speed due to bandwidth and slew-rate limitations Droop rate slow change during hold mode Aperture (or sampling) jitter effective sampling time error in time; difficult in high-speed designs
University of Toronto
slide 2 of 18
D.A. Johns, K. Martin, 1997

Basic Concept
clk Q1 V Chld

Vin

Vout

Basic circuit has some practical problems Charge Injection Causes hold step Aperature Jitter Sampling time variation function of Vin
University of Toronto
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D.A. Johns, K. Martin, 1997

Charge Injection
When clk goes low, channel charge on Q 1 causes V to have negative step. If clock edge fast, 1/2 flows each way. Channel charge QC
hld

Q CH C ox WLV eff -1 = ---------- = -----------------------------2 2

(1) (2)

V eff -1 = V GS 1 V tn = V DD V tn V in resulting in Q C - hld C ox WL ( V DD V tn V in ) V = ------------------- = -----------------------------------------------------------C hld 2 C hld

(3)

University of Toronto

slide 4 of 18
D.A. Johns, K. Martin, 1997

Charge Injection
V linearly related to V in gain error V also linearly related to V tn , which is nonlinearly related to V in distortion error Often gain error can be tolerated but not distortion

Also change due to the overlap capacitances C ox WL ov ( V DD V SS ) V ---------------------------------------------------C hld Causes dc offset effect
(4)

University of Toronto

slide 5 of 18
D.A. Johns, K. Martin, 1997

Aperature Jitter
t s1-actual V in clk

s1-ideal

s2-ideal t

s2-actual

Sampling jitter

Q1 turns off when clock falls to within V tn of V in True sampling time depends on value of V in distortion

University of Toronto

slide 6 of 18
D.A. Johns, K. Martin, 1997

S/H Charge Reduction


Q1 clk Vin V
1

clk

Q2

slightly delayed clk V


1

Vout

Vin

Q1

Vout

Chld clk

Chld

CMOS transmission gate

Dummy switch

Transmission gate difficult to make p and n transistors match Dummy switch Q2 is 1/2 size of Q1 to match charge injection difficult to make clocks fast enough so exactly 1/2 charge is injected up to 5 times better than without dummy
University of Toronto
slide 7 of 18
D.A. Johns, K. Martin, 1997

High Input Impedance


clk Q 1

V in
C hld

V out

buffer

dc offset of buffer divided by loop gain Disadvantages Opamp output must have fast slew rate Samp time, charge inject input signal dependent Speed reduced due to overall feedback

University of Toronto

slide 8 of 18
D.A. Johns, K. Martin, 1997

Reduced Slew Rate Requirement


clk
Q 3

clk
2

clk
Q 1

V in C hld

V out

Samp time, charge injection - input signal dependent

University of Toronto

slide 9 of 18
D.A. Johns, K. Martin, 1997

Input Signal Independence


Opamp 1

clk
Q 1

C hld

V in clk
Q 2 Opamp 2

V out

Q1 always at virtual ground Samp time, charge injection - NOT dependent Charge injection causes ONLY dc offset Q2 used to clamp opamp1 output near ground Slower due to two opamps in feedback
University of Toronto
slide 10 of 18
D.A. Johns, K. Martin, 1997

Reduced Offset (Single Ended)


clk
Q 1

C hld

V in

clk

V out
Q 3

clk
Q 2

C hld

Charge injected by Q1 matched by Q2 into

C hld

If fully differential design, matching occurs naturally leading to lower offset.

University of Toronto

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D.A. Johns, K. Martin, 1997

Reduced Offset (Differential)


C hld clk V out V in clk

clk

clk

C hld

Gnd is common mode voltage

University of Toronto

slide 12 of 18
D.A. Johns, K. Martin, 1997

Example #1 (BiCMOS)
R C

clk R Vin clk


Q2 Q1

Vout

Needs opamp capable of driving resistive loads Good high-speed BiCMOS configuration 3 dB = 1 ( RC ) when in track mode Might add a small input capacitor
University of Toronto
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D.A. Johns, K. Martin, 1997

Example #2
clk Q1 Vin C1 Vout

Q2

C2

Charge injection of transistors cancel Clock signals are signal dependent Good speed, moderate accuracy
University of Toronto
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D.A. Johns, K. Martin, 1997

Example #3
clk Q1 C1 C2

Vout

Vin
Q2

Hold capacitor is large Miller capacitor Can use smaller capacitors and switches good speed If Q2 turned off first, injection of Q1 small due to Miller effect
University of Toronto
slide 15 of 18
D.A. Johns, K. Martin, 1997

Example #3 (contd)
Vout C1 Vin C2

Miller cap C1 C2 ( 1 + A ) ----------------- C 1 + C 2 Amp output does not swing much Higher speed amplifier possible

Sample Mode
Vout C1 Vin C2

Hold Mode

University of Toronto

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D.A. Johns, K. Martin, 1997

Example #4
1 2

Vin
1

CH

Vout

Accurate since offset cancellation performed Slow since opamp swings from 0 to Vin every cycle
University of Toronto
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D.A. Johns, K. Martin, 1997

Example #5
1 Vin
Q1 Q2

2 Vout 1
Q3

Improved accuracy High input imped 1a -> advanced Charge inj of Q4 and Q5 cancel (and is signal indep) Charge inj of Q1 and Q2 - no effect Charge inj of Q3 reduced as before

B1

B2

C1
Q4

1a

C2

Q5

1a

C3

University of Toronto

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D.A. Johns, K. Martin, 1997