What is the output of AND gate in the circuit below, when A and B are as in waveform?

Where, Tp is gate delay of respective gate.

dentify the below circuit, and its limitation ?

What is the current though the resistor !" # c$ ?

!eferring to the diagram below, briefly e%plain what will happen if the propagation delay of the cloc& signal in path B is much too high compare to path A. 'ow do we solve this problem if the propagation delay of path B can not be reduced ?

What is the function of a D flip(flop, whose inverted output is connected to its input ?

Design a circuit to divide input fre)uency by * ?

Design a divide(by(+ se)uential circuit with ,-. duty cycle.?

Design a divide(by(, se)uential circuit with ,-. duty cycle.?

What are the different types of adder implementation ?

Draw a Transmission /ate(based D(0atch ?

/ive the truth table for a 'alf Adder. /ive a gate level implementation of the same.

What is the purpose of the buffer in below circuit, is it necessary1redundant to have buffer ?

What is output of the below circuit, assuming that value of 232 is not &nown ?

4onsider a circular dis& as shown in figure below with two sensors mounted 3, 5 and blue shade painted on the dis& for a angle of 6, degree. Design a circuit with minimum number of gates to detect the direction of rotation.

Design a 7! gate from *8" 9:3.

Design a 37! gate from *8" 9:3 and a N7T gate

What is the difference between a 0AT4' and a ;0 <(;07< ?

0atch is a level sensitive device and flip(flop is edge sensitive device 0atch is sensitive to glitches on enable pin, where as flip(flop is immune to glitches. 0atches ta&e less gates #also less power$ to implement then flip(flops 0atches are faster then flip(flops

Design a D ;lip(;lop from two latches.

Design a * bit counter using D ;lip(;lop.

What are the two types of delays in any digital system ?

Design a Transparent 0atch using a *8" 9u%.

Design a 68" 9u% using *8" 9u%2s and some combo logic.

What is metastable state ? 'ow does it occur ?

What is metastability ?

Design a +8= decoder

Design a ;>9 to detect se)uence ?"-"? in input se)uence.

4onvert NAND gate into nverter, in two different ways.

Design a D and T flip flop using *8" mu%, use of other components not allowed, @ust the mu%.

Design a divide by two counter using D(0atch.

Design D 0atch from >! flip(flop.

Define 4loc& >&ew , Negative 4loc& >&ew, <ositive 4loc& >&ew ?

What is !ace 4ondition ?

Design a 6 bit /ray 4ounter ?

Design 6(bit >ynchronous counter, Asynchronous counter ?

Design a "A byte Asynchronous ; ;7?

What is the difference between a BB<!79 and ;0A>' ?

What is the difference between a NAND(based ;lash and N7!(based ;lash ?

5ou are given a "-- 9'C cloc& , Design a ++.+ 9'C cloc& with and without ,- . duty cycle?

Design a !ead on !eset >ystem ?

Which one is superior Asynchronous !eset or >ynchronous !eset, B%plain ?

Design a >tate machine for Traffic 4ontrol at a ;our point Dunction ?

What are ; ;72s, can you draw the bloc& diagram of ; ;7, could you modify it to ma&e it asynchronous ; ;7 ?

'ow can you generate random se)uence in digital circuits?