Ee101 DGTL 5

EE101: Digital circuits (Part 5)
M. B. Patil
mbpatil@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay
M. B. Patil, IIT Bombay
JK ip-op: asynchronous inputs
Sd Rd
J CLK K
Rd 1 0 1 0 0 0 0
CLK
Qn+1 0 1 invalid Qn 0 1 Qn
normal operation
0 Q 1 1 0 Q 0 0 0
X X X
X X X 0 0 1 1
X X X 0 1 0 1
Sd
Sd Rd
J CLK K
Rd 1 0 1 0 0 0 0
CLK
normal operation
0 Q 1 1 0 Q 0 0 0
X X X
X X X 0 0 1 1
X X X 0 1 0 1
Sd
* Clocked ip-ops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (also called Preset and Clear, respectively) which override all other inputs (J, K, CLK).
Sd Rd
J CLK K
Rd 1 0 1 0 0 0 0
CLK
normal operation
0 Q 1 1 0 Q 0 0 0
X X X
X X X 0 0 1 1
X X X 0 1 0 1
Sd
* Clocked ip-ops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (also called Preset and Clear, respectively) which override all other inputs (J, K, CLK). * The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd .
Sd Rd
J CLK K
Rd 1 0 1 0 0 0 0
CLK
normal operation
0 Q 1 1 0 Q 0 0 0
X X X
X X X 0 0 1 1
X X X 0 1 0 1
Sd
* Clocked ip-ops are also provided with asynchronous or direct Set and Reset inputs, Sd and Rd , (also called Preset and Clear, respectively) which override all other inputs (J, K, CLK). * The Sd and Rd inputs may be active low; in that case, they are denoted by Sd and Rd . * The asynchronous inputs are convenient for starting up a circuit in a known state.
D ip-op
CLK D CLK
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
positive edgetriggered D flipflop
t1
CLK D CLK
t2
t3
t4
t5
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
negative edgetriggered D flipflop
t1
t2
t3
t4
t5
D ip-op
CLK D CLK
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
t1
CLK D CLK
t2
t3
t4
t5
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
t1
t2
t3
t4
t5
* The D ip-op can be used to delay the Data (D) signal by one clock period.
D ip-op
CLK D CLK
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
t1
CLK D CLK
t2
t3
t4
t5
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
t1
t2
t3
t4
t5
* The D ip-op can be used to delay the Data (D) signal by one clock period. * With J = D , K = D , we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the rst case, 1 in the second case.
D ip-op
CLK D CLK
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
t1
CLK D CLK
t2
t3
t4
t5
CLK
Qn+1 0 1
D CLK
Q
D
0 Q 1
t K
Q t
t1
t2
t3
t4
t5
* The D ip-op can be used to delay the Data (D) signal by one clock period. * With J = D , K = D , we have either J = 0, K = 1 or J = 1, K = 0; the next Q is 0 in the rst case, 1 in the second case. * Instead of a JK ip-op, an RS ip-op can also be used to make a D ip-op, with S = D, R = D.
Shift register
Let Q1 = Q2 = Q3 = Q4 = 0 initially.
D D
Q1
Q2
Q3
Q4
Q
CLK
Shift register
D D
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0
Q2
0
Q3
0
Q4
0
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0 1
Q2
0 0
Q3
0 0
Q4
0 0
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0 1 1
Q2
0 0 1
Q3
0 0 0
Q4
0 0 0 t
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0 1 1
Q2
0 0 1 1
Q3
0 0 0 1
Q4
0 0 0 0 t
Q1
Q2
Q3
Q4
Q
CLK
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0 1 1
Q2
0 0 1 1 0
Q3
0 0 0 1 1
Q4
0 0 0 0 1 t
Q1
Q2
Q3
Q4
Q
CLK
0 1
CLK
Q1 Q2 Q3 Q4
0.1
0.2
0.3
0.4 0.5 time (msec)
0.6
0.7
0.8
0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0 1 1
Q2
0 0 1 1 0 1
Q3
0 0 0 1 1 0
Q4
0 0 0 0 1 1 t
Q1
Q2
Q3
Q4
Q
CLK
0 1 0
CLK
Q1 Q2 Q3 Q4
(SEQUEL file: ee101_shift_reg_1.sqproj) 0 0.1 0.2 0.3 0.4 0.5 time (msec) 0.6 0.7 0.8 0.9
Shift register
D D t D: 0 D
Q1
1 0 1 1 0 1 1
Q2
0 0 1 1 0 1
Q3
0 0 0 1 1 0
Q4
0 0 0 0 1 1 t
Q1
Q2
Q3
Q4
Q
CLK
0 1 0
CLK
Q1 Q2 Q3 Q4
(SEQUEL file: ee101_shift_reg_1.sqproj) 0 0.1 0.2 0.3 0.4 0.5 time (msec) 0.6 0.7 0.8 0.9
* The data (D) keeps shifting right after each active clock edge.
Parallel transfer between shift registers
A3
A2
A1
A0
Register A
A3
A2
A1
A0
B3
B2
B1
B0
Register B
B3
B2
B1
B0
Q
CLK
Parallel transfer between shift registers
A3
A2
A1
A0
Register A
A3
A2
A1
A0
B3
B2
B1
B0
Register B
B3
B2
B1
B0
Q
CLK
* After the active clock edge, the contents of the A register (A3 A2 A1 A0 ) are copied to the B register.
Bidirectional shift register
M DR D0
D
Q0
D1
D
Q1
D2
D
Q2
D3
D
Q3
Q DL
M
CLK
M DR D0
D
Q0
D1
D
Q1
D2
D
Q2
D3
D
Q3
Q DL
M
CLK
* When the mode input (M) is 1, we have D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .
M DR D0
D
Q0
D1
D
Q1
D2
D
Q2
D3
D
Q3
Q DL
M
CLK
* When the mode input (M) is 1, we have D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 . * When the mode input (M) is 0, we have D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL .
M DR D0
D
Q0
D1
D
Q1
D2
D
Q2
D3
D
Q3
Q DL
M
CLK
* When the mode input (M) is 1, we have D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 . * When the mode input (M) is 0, we have D0 = Q1 , D1 = Q2 , D2 = Q3 , D3 = DL . * M = 1 shift right operation. M = 0 shift left operation.
Multiplication using shift and add
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143)
Z Z 1 1
Z Z Z 1 1 1
Note that Z = 0. We use Z to denote 0s which are independent of the numbers being multiplied.
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z
Register 2 Z Z Z Z
Register 1 Z Z Z initialize
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z 1
Register 2 Z 0 Z 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z 1 1
Register 2 Z 0 0 Z 1 1 Z 1 1 Z Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z add
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z 1 1 Z
Register 2 Z 0 0 1 Z 1 1 0 Z 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z 1 1 Z 0
Register 2 Z 0 0 1 0 Z 1 1 0 0 Z 1 1 1 0 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z 1 1 Z 0 0
Register 2 Z 0 0 1 0 1 Z 1 1 0 0 0 Z 1 1 1 0 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z Z Z add
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
A3 A2 A1 A0 (decimal 11) B3 B2 B1 B0 (decimal 13) since B0 = 1 since B1 = 0 addition since B2 = 1 addition since B3 = 1 addition (decimal 143) Z 1 1 Z 0 0 Z
Register 2 Z 0 0 1 0 1 0 Z 1 1 0 0 0 1 Z 1 1 1 0 1 0 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
Register 2 Z 0 0 1 0 1 0 0 Z 1 1 0 0 0 1 1 Z 1 1 1 0 1 0 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift load 1011 since B2 = 1
Z Z 1 1
Z Z Z 1 1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
Register 2 Z 0 0 1 0 1 0 0 1 Z 1 1 0 0 0 1 1 0 Z 1 1 1 0 1 0 1 1 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift load 1011 since B2 = 1 1 Z Z add
Z Z 1 1
Z Z Z 1 1 1
1 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
Register 2 Z 0 0 1 0 1 0 0 1 1 Z 1 1 0 0 0 1 1 0 1 Z 1 1 1 0 1 0 1 1 0 1 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift load 1011 since B2 = 1 1 1 Z 1 Z Z add shift
Z Z 1 1
Z Z Z 1 1 1
1 1 Z
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
Register 2 Z 0 0 1 0 1 0 0 1 1 0 Z 1 1 0 0 0 1 1 0 1 1 Z 1 1 1 0 1 0 1 1 0 1 1 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift load 1011 since B2 = 1 1 1 Z 1 Z Z add shift load 1011 since B3 = 1
Z Z 1 1
Z Z Z 1 1 1
1 1 Z 1
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
Register 2 Z 0 0 1 0 1 0 0 1 1 0 0 Z 1 1 0 0 0 1 1 0 1 1 0 Z 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift load 1011 since B2 = 1 1 1 Z 1 Z Z add shift load 1011 since B3 = 1 1 1 Z add
Z Z 1 1
Z Z Z 1 1 1
1 1 Z 1 1 0
1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 1
0 1 0 0 0 1 1
1 0 1 0 1
1 1 1 Z 1
Register 2 Z 0 0 1 0 1 0 0 1 1 0 0 0 Z 1 1 0 0 0 1 1 0 1 1 0 0 Z 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 Z 1 Z
Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift load 0000 since B1 = 0 Z 1 Z Z Z Z add shift load 1011 since B2 = 1 1 1 Z 1 Z Z add shift load 1011 since B3 = 1 1 1 1 1 Z 1 add shift
Z Z 1 1
Z Z Z 1 1 1
1 1 Z 1 1 Z 0 1
Parallel in-serial out data movement

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Clear t Load t CLK t
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3
* All ip-ops are cleared in the beginning (with Rd = Clear = 1, Sd = 0).

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3
* All ip-ops are cleared in the beginning (with Rd = Clear = 1, Sd = 0). * When Load = 1, Sd = Ai , Rd = 0 Ai gets loaded into the i th ip-op. (We will assume that CLK has been made 0 in this initial phase.)

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3
* All ip-ops are cleared in the beginning (with Rd = Clear = 1, Sd = 0). * When Load = 1, Sd = Ai , Rd = 0 Ai gets loaded into the i th ip-op. (We will assume that CLK has been made 0 in this initial phase.) * Subsequently, with every clock pulse, the data shifts right and appears serially at the output Q0 .

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
0 Clear t Load t CLK t
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3

Load
A3
A2
A1
A0
Sd Q Q3 J
Sd Q Q2 J
Sd Q Q1 J
Sd Q Q0
1 Clear CLK
Rd Q
Rd Q
Rd Q
Rd Q
Q0 = A0
Q0 = A1
Q0 = A2
Q0 = A3
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic
State transition diagram
General configuration
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic
* A counter with k states is called a modulo-k (mod-k ) counter.
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic
* A counter with k states is called a modulo-k (mod-k ) counter. * A counter can be made with ip-ops, each ip-op serving as a memory element with two states (0 or 1).
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic
* A counter with k states is called a modulo-k (mod-k ) counter. * A counter can be made with ip-ops, each ip-op serving as a memory element with two states (0 or 1). * If there are N ip-ops in a counter, there are 2N possible states (since each ip-op can have Q = 0 or Q = 1). It is possible to exclude some of these states. N ip-ops can be used to make a mod-k counter with k 2N .
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic
* A counter with k states is called a modulo-k (mod-k ) counter. * A counter can be made with ip-ops, each ip-op serving as a memory element with two states (0 or 1). * If there are N ip-ops in a counter, there are 2N possible states (since each ip-op can have Q = 0 or Q = 1). It is possible to exclude some of these states. N ip-ops can be used to make a mod-k counter with k 2N . * Typically, a reset facility is also provided, which can be used to force a certain state to initialize the counter.
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic

1 CLK X 8T 2 3 4 5 6 7 8 1
2 3 4 5 6 7 8 1 t t
X is 1 for state 3; else, it is 0.
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic

1 CLK X 8T 2 3 4 5 6 7 8 1
2 3 4 5 6 7 8 1 t t
* The counter outputs (i.e., the ip-op outputs, Q0 , Q1 , QN 1 ) can be decoded using appropriate logic.
Counters
1 k 2 Clock Counter
Q0 Q1 Q2
QN-1
Reset
Decoding logic

1 CLK X 8T 2 3 4 5 6 7 8 1
2 3 4 5 6 7 8 1 t t
* The counter outputs (i.e., the ip-op outputs, Q0 , Q1 , QN 1 ) can be decoded using appropriate logic. * In particular, it is possible to have a decoder output (say, X ) which is 1 only for state i , and 0 otherwise. For k clock pulses, we get a single pulse at X , i.e., the clock frequency has been divided by k . For this reason, a mod-k counter is also called a divide-by-k counter.
A binay ripple counter
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
* J = K = 1 for all ip-ops. Let Q0 = Q1 = Q2 = 0 initially.
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
* J = K = 1 for all ip-ops. Let Q0 = Q1 = Q2 = 0 initially. * Since J = K = 1, each ip-op will toggle when an active (in this case, negative) clock edge arrives.
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
* J = K = 1 for all ip-ops. Let Q0 = Q1 = Q2 = 0 initially. * Since J = K = 1, each ip-op will toggle when an active (in this case, negative) clock edge arrives. * For FF1 and FF2, Q0 and Q1 , respectively, provide the clock.
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
CLK t
Q0
t
Q1
t
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 0 1 1 0 0 1 1 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 0 0 0 t 1 1 t 1 1 0 t
CLK
Q0
Q1
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 0 1 1 0 0 1 1 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 0 0 0 t 1 1 t 1 1 0 t
CLK
Q0
Q1
Q2
t
* J = K = 1 for all ip-ops. Let Q0 = Q1 = Q2 = 0 initially. * Since J = K = 1, each ip-op will toggle when an active (in this case, negative) clock edge arrives. * For FF1 and FF2, Q0 and Q1 , respectively, provide the clock. * Note that the direct inputs Sd and Rd (not shown) are assumed to be Sd = Rd = 0 for all ip-ops, allowing normal ip-ip operation.
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 0 1 1 0 0 1 1 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 0 0 0 t 1 1 t 1 1 0 t
CLK
Q0
Q1
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 0 1 1 0 0 1 1 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 0 0 0 t 1 1 t 1 1 0 t
CLK
Q0
Q1
Q2
t
* The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111. it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111).
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 0 1 1 0 0 1 1 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 0 0 0 t 1 1 t 1 1 0 t
CLK
Q0
Q1
Q2
t
* The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111. it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111). * If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8, respectively. For this counter, therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requring decoding logic.
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 0 1 1 0 0 1 1 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 0 0 0 t 1 1 t 1 1 0 t
CLK
Q0
Q1
Q2
t
* The counter has 8 states, Q2 Q1 Q0 = 000, 001, 010, 011, 100, 101, 110, 111. it is a mod-8 counter. In particular, it is a binary, mod-8, up counter (since it counts up from 000 to 111). * If the clock frequency is fc , the frequency at the Q0 , Q1 , Q2 outputs is fc /2, fc /4, fc /8, respectively. For this counter, therefore, div-by-2, div-by-4, div-by-8 outputs are already available, without requring decoding logic. * This type of counter is called a ripple counter since the clock transitions ripple through the ip-ops.
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 1 1 0 0 1 1 0 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 1 1 1 t 1 0 t 0 0 0 t
CLK
Q0
Q1
Q2
t
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2 Q2 Q1
0 1 1 0 0 1 1 0 0
Q0
0 1 0 1 0 1 0 1 0 repeats
0 1 1 1 t 1 0 t 0 0 0 t
CLK
Q0
Q1
Q2
t
* If positive edge-triggered ip-ops are used, we get a binary down counter (counting down from 1111 to 0000).
Binay ripple counters
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
1 J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
* Home work: Sketch the waveforms (CLK, Q0 , Q1 , Q2 ), and tabulate the counter states in each case.
Up-down binay ripple counters
M
J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
M=1 CLK t CLK
M=0
Q0
t
Q0
t
Q1
t
Q1
t
Q2
t
Q2
t
Up-down binay ripple counters
M
J CLK K FF0
Q0
J FF1
Q1
J FF2
Q2
M=1 CLK t CLK
M=0
Q0
t
Q0
t
Q1
t
Q1
t
Q2
t
Q2
t
* When Mode (M) = 1, the counter counts up; else, it counts down. (SEQUEL le: ee101 counter 3.sqproj)
Decade counter using direct inputs
0 1 J CLK K
Q0 Sd Q
FF0
Q1 Sd Q
FF1
Q2 Sd Q
FF2
Q3 Sd Q
FF3
Rd Q
Rd Q
Rd Q
Rd Q
Q3
0 0 0 0
Q2
0 0 0 0 1 1 1 1 0 0 0
Q1
0 0 1 1 0 0 1 1 0 0 0
Q0
0 1 0 1 0 1 0 1 0 1 0 repeats
Q0
Q1
0 0 0 0 1 1 0
Q2
Q3
0.1
0.2
0.3
0.4 time (msec)
0.5
0.6
0.7
0.8
0 1 J CLK K
Q0 Sd Q
FF0
Q1 Sd Q
FF1
Q2 Sd Q
FF2
Q3 Sd Q
FF3
Rd Q
Rd Q
Rd Q
Rd Q
Q3
0 0 0 0
Q2
0 0 0 0 1 1 1 1 0 0 0
Q1
0 0 1 1 0 0 1 1 0 0 0
Q0
0 1 0 1 0 1 0 1 0 1 0 repeats
Q0
Q1
0 0 0 0 1 1 0
Q2
Q3
0.1
0.2
0.3
0.4 time (msec)
0.5
0.6
0.7
0.8
* When the counter reaches Q3 Q2 Q1 Q0 = 1010 (i.e., decmial 10), Q3 Q1 = 1, and the ip-ops are cleared to Q3 Q2 Q1 Q0 = 0000.
0 1 J CLK K
Q0 Sd Q
FF0
Q1 Sd Q
FF1
Q2 Sd Q
FF2
Q3 Sd Q
FF3
Rd Q
Rd Q
Rd Q
Rd Q
Q3
0 0 0 0
Q2
0 0 0 0 1 1 1 1 0 0 0
Q1
0 0 1 1 0 0 1 1 0 0 0
Q0
0 1 0 1 0 1 0 1 0 1 0 repeats
Q0
Q1
0 0 0 0 1 1 0
Q2
Q3
0.1
0.2
0.3
0.4 time (msec)
0.5
0.6
0.7
0.8
* When the counter reaches Q3 Q2 Q1 Q0 = 1010 (i.e., decmial 10), Q3 Q1 = 1, and the ip-ops are cleared to Q3 Q2 Q1 Q0 = 0000. * The counter counts from 0000 (decimal 0) to 1001 (decimal 9) decade counter. (SEQUEL le: ee101 counter 5.sqproj)
A synchronous counter
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
* Since all ip-ops are driven by the same clock, the counter is called a synchronous counter.
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
* Since all ip-ops are driven by the same clock, the counter is called a synchronous counter. * J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 .
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
* Since all ip-ops are driven by the same clock, the counter is called a synchronous counter. * J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 . * FF0 toggles at every active edge. FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. Similar comments apply to FF2 and FF3.
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
1 J FF0 K CLK
Q0
J FF1
Q1
J FF2
Q2
J FF3
Q3
CLK t
Q0
t
Q1
t
Q2
t
Q3
t
* Since all ip-ops are driven by the same clock, the counter is called a synchronous counter. * J0 = K0 = 1, J1 = K1 = Q0 , J2 = K2 = Q1 Q0 , J3 = K3 = Q2 Q1 Q0 . * FF0 toggles at every active edge. FF1 toggles if Q0 = 1 (just before the active clock edge); else, it retains its previous state. Similar comments apply to FF2 and FF3. * From the waveforms, we see that it is a binary up counter.
Design of synchronous counters
CLK J CLK K
Qn+1 Qn 0 1 Qn
0 0
0 1 0 1
1 1
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn
Qn+1
0 0
0 1 0 1
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen?
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn
Qn+1
0 0
0 1 0 1
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen? * Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by making J = 0, K = 0.
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn
Qn+1
0 0
0 1 0 1
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen? * Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by making J = 0, K = 0. J = 0, K = X (i.e., K can be 0 or 1).
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn 0
Qn+1 0
0 0
0 1 0 1
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen? * Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by making J = 0, K = 0. J = 0, K = X (i.e., K can be 0 or 1).
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn 0
Qn+1 0
0 0
0 1 0 1
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen? * Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by making J = 0, K = 0. J = 0, K = X (i.e., K can be 0 or 1). * Similarly, work out the other entries in the table.
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 0
0 1 0 1
0 1 X X
X X 1 0
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen? * Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by making J = 0, K = 0. J = 0, K = X (i.e., K can be 0 or 1). * Similarly, work out the other entries in the table.
CLK J CLK K
Qn+1 Qn 0 1 Qn
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 0
0 1 0 1
0 1 X X
X X 1 0
1 1
* Consider the reverse problem: We are given Qn and the next desired state (Qn+1 ). What should J and K be in order to make that happen? * Qn = 0, Qn+1 = 0: We can either force Qn+1 = 0 with J = 0, K = 1, or let Qn+1 = Qn = 0 by making J = 0, K = 0. J = 0, K = X (i.e., K can be 0 or 1). * Similarly, work out the other entries in the table. * The table for a negative edge-triggered ip-op would be identical excpet for the active edge.
state Q2 1 2 3 4 5 1 0 0 0 0 1 0
Q1
0 0 1 1 0 0
Q0
0 1 0 1 0 0 CLK repeats
J2
Q2 J1
Q1 J0
Q0
CLK
Qn 0 0
Qn+1 0 1 0 1
0 1 X X
X X 1 0
K2
K1
K0
1 1
Design a synchronous mod-5 counter with the given state transition table.
state Q2 1 2 3 4 5 1 0 0 0 0 1 0
Q1
0 0 1 1 0 0
Q0
J2
Q2 J1
Q1 J0
Q0
CLK
Qn 0 0
Qn+1 0 1 0 1
0 1 X X
X X 1 0
K2
K1
K0
1 1
Design a synchronous mod-5 counter with the given state transition table. Outline of method:
state Q2 1 2 3 4 5 1 0 0 0 0 1 0
Q1
0 0 1 1 0 0
Q0
J2
Q2 J1
Q1 J0
Q0
CLK
Qn 0 0
Qn+1 0 1 0 1
0 1 X X
X X 1 0
K2
K1
K0
1 1
Design a synchronous mod-5 counter with the given state transition table. Outline of method: * State 1 State 2 means Q2 : 0 0, Q1 : 0 0, Q0 : 0 1.
state Q2 1 2 3 4 5 1 0 0 0 0 1 0
Q1
0 0 1 1 0 0
Q0
J2
Q2 J1
Q1 J0
Q0
CLK
Qn 0 0
Qn+1 0 1 0 1
0 1 X X
X X 1 0
K2
K1
K0
1 1
Design a synchronous mod-5 counter with the given state transition table. Outline of method: * State 1 State 2 means Q2 : 0 0, Q1 : 0 0, Q0 : 0 1. * Refer to the right table. For Q2 : 0 0, we must have J2 = 0, K2 = X , and so on.
state Q2 1 2 3 4 5 1 0 0 0 0 1 0
Q1
0 0 1 1 0 0
Q0
J2
Q2 J1
Q1 J0
Q0
CLK
Qn 0 0
Qn+1 0 1 0 1
0 1 X X
X X 1 0
K2
K1
K0
1 1
Design a synchronous mod-5 counter with the given state transition table. Outline of method: * State 1 State 2 means Q2 : 0 0, Q1 : 0 0, Q0 : 0 1. * Refer to the right table. For Q2 : 0 0, we must have J2 = 0, K2 = X , and so on. * When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q1 , Q2 , Q3 .
state Q2 1 2 3 4 5 1 0 0 0 0 1 0
Q1
0 0 1 1 0 0
Q0
J2
Q2 J1
Q1 J0
Q0
CLK
Qn 0 0
Qn+1 0 1 0 1
0 1 X X
X X 1 0
K2
K1
K0
1 1
Design a synchronous mod-5 counter with the given state transition table. Outline of method: * State 1 State 2 means Q2 : 0 0, Q1 : 0 0, Q0 : 0 1. * Refer to the right table. For Q2 : 0 0, we must have J2 = 0, K2 = X , and so on. * When we cover all transitions in the left table, we have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q1 , Q2 , Q3 . * The last step is to come up with suitable functions for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q1 , Q2 , Q3 . This can be done with K-maps. (If the number of ip-ops is more than 4, other techniques can be employed.)
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
K2
J1
K1
J0
K0
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
K2
J1
K1
J0
K0
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0
K2
X
J1
K1
J0
K0
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0
K2
X
J1
0
K1
X
J0
K0
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0
K2
X
J1
0
K1
X
J0
1
K0
X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0
K2
X
J1
0
K1
X
J0
1
K0
X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0
K2
X X
J1
0
K1
X
J0
1
K0
X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0
K2
X X
J1
0 1
K1
X X
J0
1
K0
X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0
K2
X X
J1
0 1
K1
X X
J0
1 X
K0
X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0
K2
X X
J1
0 1
K1
X X
J0
1 X
K0
X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0
K2
X X X
J1
0 1
K1
X X
J0
1 X
K0
X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0
K2
X X X
J1
0 1 X
K1
X X 0
J0
1 X
K0
X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0
K2
X X X
J1
0 1 X
K1
X X 0
J0
1 X 1
K0
X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0
K2
X X X
J1
0 1 X
K1
X X 0
J0
1 X 1
K0
X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1
K2
X X X X
J1
0 1 X
K1
X X 0
J0
1 X 1
K0
X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1
K2
X X X X
J1
0 1 X X
K1
X X 0 1
J0
1 X 1
K0
X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1
K2
X X X X
J1
0 1 X X
K1
X X 0 1
J0
1 X 1 X
K0
X 1 X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1
K2
X X X X
J1
0 1 X X
K1
X X 0 1
J0
1 X 1 X
K0
X 1 X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X
K1
X X 0 1
J0
1 X 1 X
K0
X 1 X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X
K0
X 1 X 1
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
* We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . The next step is to nd logical functions for each of them.
state 1 2 3 4 5 1
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
CLK
Qn 0 0 1 1
Qn+1 0 1 0 1
0 1 X X
X X 1 0
* We now have the truth tables for J0 , K0 , J1 , K1 , J2 , K2 in terms of Q0 , Q1 , Q2 . The next step is to nd logical functions for each of them. * Note that we have not tabulated the J and K values for those combinations of Q0 , Q1 , Q2 which do not occur in the state transition table (such as Q2 Q1 Q0 = 110). We treat these as dont care conditions (next slide).
J2
state 1 2 3 4 5 1
Q2 Q1 Q0 00 0 0 1 0
01
11
10
0 1
X X
X X
K2
Q2 Q1 Q0 00 0 X 1 X
01
11
10
X X
X X
1 X
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
J1
Q2 Q1 Q0 00 0 0 1 1
01
11
10
X X
X X
0 X
K1
Q2 Q1 Q0 00 0 X 1 X
01
11
10
0 1
X X
X X
J0
Q2 Q1 Q0 00 0 1 1 X
01
11
10
1 X
X X
0 X
K0
Q2 Q1 Q0 00 0 X 1 1
01
11
10
X 1
X X
X X
J2
state 1 2 3 4 5 1
Q2 Q1 Q0 00 0 0 1 0
01
11
10
0 1
X X
X X
K2
Q2 Q1 Q0 00 0 X 1 X
01
11
10
X X
X X
1 X
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
J1
Q2 Q1 Q0 00 0 0 1 1
01
11
10
X X
X X
0 X
K1
Q2 Q1 Q0 00 0 X 1 X
01
11
10
0 1
X X
X X
J0
Q2 Q1 Q0 00 0 1 1 X
01
11
10
1 X
X X
0 X
K0
Q2 Q1 Q0 00 0 X 1 1
01
11
10
X 1
X X
X X
* We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) dont care conditions. Since these are dierent from the dont care conditions arising from the state transition table, we mark them with a dierent colour.
J2
state 1 2 3 4 5 1
Q2 Q1 Q0 00 0 0 1 0
01
11
10
0 1
X X
X X
K2
Q2 Q1 Q0 00 0 X 1 X
01
11
10
X X
X X
1 X
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
J1
Q2 Q1 Q0 00 0 0 1 1
01
11
10
X X
X X
0 X
K1
Q2 Q1 Q0 00 0 X 1 X
01
11
10
0 1
X X
X X
J0
Q2 Q1 Q0 00 0 1 1 X
01
11
10
1 X
X X
0 X
K0
Q2 Q1 Q0 00 0 X 1 1
01
11
10
X 1
X X
X X
* We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) dont care conditions. Since these are dierent from the dont care conditions arising from the state transition table, we mark them with a dierent colour. * We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the ve allowed states (say, Q2 Q1 Q0 = 000).
J2
state 1 2 3 4 5 1
Q2 Q1 Q0 00 0 0 1 0
01
11
10
0 1
X X
X X
K2
Q2 Q1 Q0 00 0 X 1 X
01
11
10
X X
X X
1 X
Q2
0 0 0 0 1 0
Q1 Q0
0 0 1 1 0 0 0 1 0 1 0 0
J2
0 0 0 1 X
K2
X X X X 1
J1
0 1 X X 0
K1
X X 0 1 X
J0
1 X 1 X 0
K0
X 1 X 1 X
J1
Q2 Q1 Q0 00 0 0 1 1
01
11
10
X X
X X
0 X
K1
Q2 Q1 Q0 00 0 X 1 X
01
11
10
0 1
X X
X X
J0
Q2 Q1 Q0 00 0 1 1 X
01
11
10
1 X
X X
0 X
K0
Q2 Q1 Q0 00 0 X 1 1
01
11
10
X 1
X X
X X
* We treat the unused states (Q2 Q1 Q0 = 101, 110, 111) as (additional) dont care conditions. Since these are dierent from the dont care conditions arising from the state transition table, we mark them with a dierent colour. * We will assume that a suitable initialization facility is provided to ensure that the counter starts up in one of the ve allowed states (say, Q2 Q1 Q0 = 000). * From the K-maps, J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.
Design of synchronous counters: verication
J2
Q2
J1
Q1
J0
Q0
K2
CLK 1
K1
K0
CLK
Q0 Q1 Q2
0.04 0.14 0.24 time (msec) 0.34
(SEQUEL file: ee101_counter_6.sqproj)
J2
Q2
J1
Q1
J0
Q0
K2
CLK 1
K1
K0
CLK
Q0 Q1 Q2
0.04 0.14 0.24 time (msec) 0.34
* J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1.
J2
Q2
J1
Q1
J0
Q0
K2
CLK 1
K1
K0
CLK
Q0 Q1 Q2
0.04 0.14 0.24 time (msec) 0.34
* J2 = Q1 Q0 , K2 = 1, J1 = Q0 , K1 = Q0 , J0 = Q2 , K0 = 1. * Note that the design is independent of whether positive or negative edge-triggered ip-ops are used.
Combination of counters
Clock 1
Counter 1
mod-k1
Clock 2
Counter 2
mod-k2
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.)
Clock 1
Counter 1
mod-k1
Clock 2
Counter 2
mod-k2
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.) * Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with k1 k2 states if appropriate synchronisation is provided between the two clocks.
Clock 1
Counter 1
mod-k1
Clock 2
Counter 2
mod-k2
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.) * Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with k1 k2 states if appropriate synchronisation is provided between the two clocks. * There are two ways of providing synchronisation:
Clock 1
Counter 1
mod-k1
Clock 2
Counter 2
mod-k2
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.) * Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with k1 k2 states if appropriate synchronisation is provided between the two clocks. * There are two ways of providing synchronisation: - derive Clock 2 from Clock 1 (using some decoding logic, if necessary)
Clock 1
Counter 1
Clock 1
Counter 1
mod-k1
Decoding logic
Counter 2 Clock 2
mod-k2
mod-k1
Clock 2
Counter 2
mod-k2
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.) * Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with k1 k2 states if appropriate synchronisation is provided between the two clocks. * There are two ways of providing synchronisation: - derive Clock 2 from Clock 1 (using some decoding logic, if necessary)
Clock 1
Counter 1
Clock 1
Counter 1
mod-k1
Decoding logic
Counter 2 Clock 2
mod-k2
mod-k1
Clock 2
Counter 2
mod-k2
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.) * Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with k1 k2 states if appropriate synchronisation is provided between the two clocks. * There are two ways of providing synchronisation: - derive Clock 2 from Clock 1 (using some decoding logic, if necessary) - drive the two counters with the same clock
Clock 1
Counter 1
Clock 1
Counter 1
mod-k1
Decoding logic
Counter 2 Clock 2
mod-k2
mod-k1
Clock 2
Counter 2
Counter 1
Counter 2
mod-k2
mod-k1
mod-k2
common clock
* Consider two counters, Counter 1 (mod-k1 ) and Counter 2 (mod-k2 ). (Each of them can be ripple or synchronous type.) * Since Counter 1 has k1 states and Counter 2 has k2 states, we can get a new counter with k1 k2 states if appropriate synchronisation is provided between the two clocks. * There are two ways of providing synchronisation: - derive Clock 2 from Clock 1 (using some decoding logic, if necessary) - drive the two counters with the same clock
J0
CLK 1
Q0
J2
Q2
J1
Q1
J0
Q0
K0
Q
CLK 1
K2
K1
K0
CLK t
CLK t
Q0
t
Q0
t
Q1
t
Q2
t
mod2 counter
mod5 counter
J0
CLK 1
Q0
J2
Q2
J1
Q1
J0
Q0
K0
Q
CLK 1
K2
K1
K0
CLK t
CLK t
Q0
t
Q0
t
Q1
t
Q2
t
mod2 counter
mod5 counter
* Let us combine the mod-2 and mod-5 counters to make a mod-10 counter.
J0
CLK 1
Q0
J2
Q2
J1
Q1
J0
Q0
K0
Q
CLK 1
K2
K1
K0
CLK t
CLK t
Q0
t
Q0
t
Q1
t
Q2
t
mod2 counter
mod5 counter
* Let us combine the mod-2 and mod-5 counters to make a mod-10 counter. * We will follow two approaches (as described earlier): A: The clock for the second (mod-5) counter is derived from the rst (mod-2) counter. B: A common clock is used to drive the mod-2 and mod-5 counters.
Approach A
J0
CLK 1
QA
J2
Q2
J1
Q1
J0
Q0
K0
K2
1
K1
K0
CLK
QA
Q0
Q1
Q2
1 2 3 4 5 6 7 8 9 10 0.44 1 2 3 4 5 6 7 8 9 10 1 2 3 4
0.04
0.24
0.64 time (msec)
0.84
1.04
Approach B
J0
QA
J2
Q2
J1
Q1
J0
Q0
1 CLK
K0
K2
1
K1
K0
CLK
QA
Q0
Q1
Q2
1 2 3 4 5 6 7 8 9 10 0.44 1 2 3 4 5 6 7 8 9 10 1 2 3 4
0.04
0.24
0.64 time (msec)
0.84
1.04
* Show that, by connecting the Q output of the mod-2 counter (instead of the Q output) to the clock input of the mod-5 counter in the ripple connection (Approach A) circuit, we get a decade counter, counting up from 0000 to 1001.
* Show that, by connecting the Q output of the mod-2 counter (instead of the Q output) to the clock input of the mod-5 counter in the ripple connection (Approach A) circuit, we get a decade counter, counting up from 0000 to 1001. * Derive appropriate decoding logic for each of the ten counters states (i.e., the output should be 1 for only that particular state and 0 otherwise).
* Show that, by connecting the Q output of the mod-2 counter (instead of the Q output) to the clock input of the mod-5 counter in the ripple connection (Approach A) circuit, we get a decade counter, counting up from 0000 to 1001. * Derive appropriate decoding logic for each of the ten counters states (i.e., the output should be 1 for only that particular state and 0 otherwise). * Derive appropriate decoding logic which will give a symmetrical square wave (i.e., a duty cycle of 50 %) with a frequency of fc /10, where fc is the clock frequency.
* Show that, by connecting the Q output of the mod-2 counter (instead of the Q output) to the clock input of the mod-5 counter in the ripple connection (Approach A) circuit, we get a decade counter, counting up from 0000 to 1001. * Derive appropriate decoding logic for each of the ten counters states (i.e., the output should be 1 for only that particular state and 0 otherwise). * Derive appropriate decoding logic which will give a symmetrical square wave (i.e., a duty cycle of 50 %) with a frequency of fc /10, where fc is the clock frequency. * Verify your design by simulation.

Ee101 DGTL 5

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EE101: Digital circuits (Part 5)

M. B. Patil, IIT Bombay

JK ip-op: asynchronous inputs

M. B. Patil, IIT Bombay

JK ip-op: asynchronous inputs

M. B. Patil, IIT Bombay

JK ip-op: asynchronous inputs

M. B. Patil, IIT Bombay

JK ip-op: asynchronous inputs

M. B. Patil, IIT Bombay

positive edgetriggered D flipflop

negative edgetriggered D flipflop

M. B. Patil, IIT Bombay

positive edgetriggered D flipflop

negative edgetriggered D flipflop

M. B. Patil, IIT Bombay

positive edgetriggered D flipflop

negative edgetriggered D flipflop

M. B. Patil, IIT Bombay

positive edgetriggered D flipflop

negative edgetriggered D flipflop

M. B. Patil, IIT Bombay

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

0.4 0.5 time (msec)

Parallel transfer between shift registers

M. B. Patil, IIT Bombay

Parallel transfer between shift registers

M. B. Patil, IIT Bombay

Bidirectional shift register

M. B. Patil, IIT Bombay

Bidirectional shift register

* When the mode input (M) is 1, we have D0 = DR , D1 = Q0 , D2 = Q1 , D3 = Q2 .

M. B. Patil, IIT Bombay

Bidirectional shift register

M. B. Patil, IIT Bombay

Bidirectional shift register

M. B. Patil, IIT Bombay

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Register 1 Z Z Z initialize load 1011 since B0 = 1

Multiplication using shift and add

Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z add

Multiplication using shift and add

Register 1 Z Z Z initialize load 1011 since B0 = 1 Z Z Z Z Z Z add shift

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

Multiplication using shift and add

M. B. Patil, IIT Bombay