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Today, at the low end of the communication protocols, we find IC (for Inter-Integrated Circuit, protocol) and S I (for Serial eripheral Interface)! "oth protocols are well-suited for communications #etween integrated circuits, for slow communication with on-#oard peripherals! $t the roots of these two popular protocols we find two ma%or companies & hilips for IC and 'otorola for S I & and two different histories a#out why, when and how the protocols were created! The IC #us was de(eloped in )*+,- its original purpose was to pro(ide an easy way to connect a C . to peripherals chips in a T/ set! eripheral de(ices in em#edded systems are often connected to the microcontroller as memorymapped I01 de(ices! 1ne common way to do this is connecting the peripherals to the microcontroller parallel address and data #usses! This results in lots of wiring on the C" (printed circuit #oard) and additional glue logic to decode the address #us on which all the peripherals are connected! In order to spare microcontroller pins, additional logic and ma2e the C"s simpler & in order words, to lower the costs & hilips la#s in 3indho(en (The 4etherlands) in(ented the Inter-Integrated Circuit, IIC or IC protocol that only re5uires , wires for connecting all the peripheral to a microcontroller! The original specification defined a #us speed of )66 2#ps (2ilo #its per second)! The specification was re(iewed se(eral times, nota#ly introducing the 766 2#ps speed in )**8 and & since )**+, 9!7 '#ps for e(en faster peripherals! It seems the Serial eripheral rotocol (S I) was first introduced with the first microcontroller deri(ing from the same architecture as the popular 'otorola :+666 microprocessor, announced in )*;*! S I defined the e<ternal microcontroller #us, used to connect the microcontroller peripherals with 7 wires! .nli2e IC, it is hard to find a formal separate specification of the S I #us & for a detailed official description, one has to read the microcontrollers data sheets and associated application notes!

S I is 5uite straightforward & it defines features any digital electronic engineer would thin2 of if it were to 5uic2ly define a way to communicate #etween , digital de(ices! S I is a protocol on 7 signal lines (please refer to figure ))= - $ cloc2 signal named SC>?, sent from the #us master to all sla(es- all the S I signals are synchronous to this cloc2 signal- $ sla(e select signal for each sla(e, SSn, used to select the sla(e the master communicates with- $ data line from the master to the sla(es, named '1SI ('aster 1ut-Sla(e In)

- $ data line from the sla(es to the master, named 'IS1 ('aster In-Sla(e 1ut)!

S I is a single-master communication protocol! This means that one central de(ice initiates all the communications with the sla(es! @hen the S I master wishes to send data to a sla(e and0or re5uest information from it, it selects sla(e #y pulling the corresponding SS line low and it acti(ates the cloc2 signal at a cloc2 fre5uency usa#le #y the master and the sla(e! The master generates information onto '1SI line while it samples the 'IS1 line (refer to figure ,)!

Aour communication modes are a(aila#le ('1B3 6, ), ,, 9) & that #asically define the SC>? edge on which the '1SI line toggles, the SC>? edge on which the master samples the 'IS1 line and the SC>? signal steady le(el (that is the cloc2 le(el, high or low, when the cloc2 is not acti(e)! 3ach mode is formally defined with a pair of parameters called cloc2 polarity (C 1>) and cloc2 phase (C C$)!

$ master0sla(e pair must use the same set of parameters & SC>? fre5uency, C 1>, and C C$ for a communication to #e possi#le! If multiple sla(es are used, that are fi<ed in different configurations, the master will ha(e to reconfigure itself each time it needs to communicate with a different sla(e! This is #asically all what is defined for the S I protocol! S I does not define any ma<imum data rate, not any particular addressing scheme- it does not ha(e a ac2nowledgement mechanism to confirm receipt of data and does not offer any flow control! $ctually, the S I master has no 2nowledge of whether a sla(e e<ists, unless something additional is done outside the S I protocol! Aor e<ample a simple codec wont need more than S I, while a command-response type of control would need a higher-le(el protocol #uilt on top of the S I interface! S I does not care a#out the physical interface characteristics li2e the I01 (oltages and standard used #etween the de(ices! Initially, most S I implementation used a non-continuous cloc2 and #yte-#y-#yte scheme! "ut many (ariants of the protocol now e<ist, that use a continuous cloc2 signal and an ar#itrary transfer length!
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IC is a multi-master protocol that uses , signal lines! The two IC signals are called serial data (SB$) and serial cloc2 (SC>)! There is no need of chip select (sla(e select) or ar#itration logic! /irtually any num#er of sla(es and any num#er of masters can #e connected onto these , signal lines and communicate #etween each other using a protocol that defines= - ;-#its sla(e addresses= each de(ice connected to the #us has got such a uni5ue address- data di(ided into +-#it #ytes - a few control #its for controlling the communication start, end, direction and for an ac2nowledgment mechanism!

The data rate has to #e chosen #etween )66 2#ps, 766 2#ps and 9!7 '#ps, respecti(ely called standard mode, fast mode and high speed mode! Some IC (ariants include )6 2#ps (low speed mode) and ) '#ps (fast mode D) as (alid speeds! hysically, the IC #us consists of the , acti(e wires SB$ and SC> and a ground connection (refer to figure 7)! The acti(e wires are #oth #i-directional! The I,C protocol specification states that the IC that initiates a data transfer on the #us is considered the "us 'aster! Conse5uently, at that time, all the other ICs are regarded to #e "us Sla(es!

Airst, the master will issue a ST$ET condition! This acts as an $ttention signal to all of the connected de(ices! $ll ICs on the #us will listen to the #us for incoming data! Then the master sends the $BBE3SS of the de(ice it wants to access, along with an indication whether the access is a Eead or @rite operation (@rite in our e<ample)! Ca(ing recei(ed the address, all ICs will compare it with their own address! If it doesnt match, they simply wait until the #us is released #y the stop condition (see #elow)! If the address matches, howe(er, the chip will produce a response called the $C?41@>3BF3 signal! 1nce the master recei(es the ac2nowledge, it can start transmitting or recei(ing B$T$! In our case, the master will transmit data! @hen all is done, the master will issue the ST1 condition! This is a signal that states the #us has #een released and that the connected ICs may e<pect another transmission to start any moment! @hen a master wants to recei(e data from a sla(e, it proceeds the same way, #ut sets the EB0n@E #it at a logical one! 1nce the sla(e has ac2nowledged the address, it starts sending the re5uested data, #yte #y #yte! $fter each data #yte, it is up to the master to ac2nowledge the recei(ed data (refer to figure 8)!

ST$ET and ST1 are uni5ue conditions on the #us that are closely dependent of the IC #us physical structure! 'oreo(er, the IC specification states that data may only change on the SB$ line if the SC> cloc2 signal is at low le(el- con(ersely, the data on the SB$ line is considered as sta#le when SC> is in high state (refer to figure : hereafter)!

$t the physical layer, #oth SC> and SB$ lines are open-drain I01s with pull-up resistors (refer to figure 7)! ulling such a line to ground is decoded as a logical Gero, while releasing the line and letting it flow is a logical one! $ctually, a de(ice on a IC #us only dri(es Geros! Cere we come to where IC is truly elegant! $ssociating the physical layer and the protocol descri#ed a#o(e allow flawless communication #etween any num#er of de(ices, on %ust , physical wires! Aor e<ample, what happens if , de(ices are simultaneously trying to put information on the SB$ and 0 or SC> linesH $t electrical le(el, there is actually no conflict at all if multiple de(ices try to put any logic le(el on the IC #us lines simultaneously! If one of the dri(ers tries to write a logical Gero and the other a logical one, then the open-drain and pull-up structure ensures that there will #e no shortcut and the #us will actually see a logical Gero transiting on the #us! In other words, in any conflict, a logic Gero always wins! The #us physical implementation also allows the master de(ices to simultaneously write and listen to the #us lines! This way, any de(ice is a#le to detect collisions! In case of a conflict #etween two masters (one of them trying to write a Gero and the other one a one), the master that gains the ar#itration on the #us will e(en not #e aware there has #een a conflict= only the master that looses will 2now & since it intends to write a logic one and reads a logic Gero! $s a result, a master that looses ar#itration on a IC will stop trying to access the #us! In most cases, it will %ust delay its access and try the same access later! 'oreo(er, the IC protocol also helps at dealing with communication pro#lems! $ny de(ice present on the IC listens to it permanently! otential masters on the IC detecting a ST$ET condition will wait until a ST1 is detected to attempt a new #us access! Sla(es on the IC #us will decode the de(ice address that follows the ST$ET condition and chec2 if it matches theirs! $ll the sla(es that are not addressed will wait until a ST1 condition is issued #efore listening again to the #us! Similarly, since the IC protocol foresees acti(e-low ac2nowledge #it after each #yte, the master 0 sla(e couple is a#le to detect their counterpart presence! .ltimately, if anything else goes wrong, this would mean that the de(ice tal2ing on the #us (master or sla(e) would 2now it #y simply comparing what it sends with what is seen on the #us! If a difference is detected, a ST1 condition must #e issued, which releases the #us! $dditionally, IC has got some ad(anced features, li2e e<tended #us addressing, cloc2 stretching and the (ery specific 9!7 '#ps high speed mode!
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- 10-bits device addressing $ny IC de(ice must ha(e a #uilt-in ; #its address! In theory, this means that there would #e only ),+ different IC de(ices types in the world! ractically, there are much more different IC de(ices and it is a high pro#a#ility that , de(ices ha(e the same address on a IC #us! To o(ercome this limitation, de(ices often ha(e multiple #uilt-in addresses that the engineer can chose #y though e<ternal configuration pins on the de(ice! The IC specification also foresees a )6-#its addressing scheme in order to e<tend the range of a(aila#le de(ices address! ractically, this has got the following impact on the IC protocol (refer to figure ;)= - Two address words are used for de(ice addressing instead of one! - The first address word 'S"s are con(entionally coded as I))))6J so any de(ice on the #us is aware the master sends a )6 #its de(ice address!

$ctually, there are other reser(ed address codes for specific types of accesses (refer to ta#le ))! Aor details a#out them, please refer to the IC specification!

- Clock stretching In an IC communication the master de(ice determines the cloc2 speed! The SC> signal is an e<plicit cloc2 signal on which the communication synchroniGes! Cowe(er, there are situations where an IC sla(e is not a#le to co-operate with the cloc2 speed gi(en #y the master and needs to slow down a little! This is done #y a mechanism referred to as cloc2 stretching and is made possi#le #y the particular open-drain 0 pull-up structure of a IC #us line! $n IC sla(e is allowed to hold down the cloc2 if it needs to reduce the #us speed! The master on the other hand is re5uired to read #ac2 the cloc2 signal after releasing it to high state and wait until the line has actually gone high!

- High speed mode Aundamentally, the use of pull-ups to set a logic one limits the ma<imum speed of the #us! This may #e a limiting factor for many applications! This is why the 9!7 '#ps high speed mode was introduced! rior to using this mode, the #us master must issue a specific Cigh Speed 'aster code at a lower speed mode (for e<ample= 766 2#ps Aast 'ode) (refer to Ta#le )), which initiates a session at 9!7 '#ps! Specific I01 #uffers must also #e used to let the #us to shorten the signals rise time and increase the #us speed! The protocol is also somewhat adapted in such a way that no ar#itration is performed during the high speed transfer! Eefer to the IC specification for more information a#out the high speed mode!
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IC vs SPI: is there a winner?

>ets compare IC and S I on se(eral 2ey protocol aspects= - Bus topology / routing / resources: IC needs , lines and thats it, while S I formally defines at least 7 signals and more, if you add sla(es! Some unofficial S I (ariants only need 9 wires, that is a SC>?, SS and a #i-directional 'IS10'1SI line! Still, this implementation would re5uire one SS line per sla(e! S I re5uires additional wor2, logic and0or pins if a multi-master architecture has to #e #uilt on S I! The only pro#lem IC when #uilding a system is a limited de(ice address space on ; #its, o(ercome with the )6-#its e<tension! Arom this point of (iew, IC is a clear winner o(er S I in sparing pins, #oard routing and how easy it is to #uild an IC networ2! - Throughput / Speed: If data must #e transferred at high speed, S I is clearly the protocol of choice, o(er IC! S I is full-duple<- IC is not! S I does not define any speed limit- implementations often go o(er )6 '#ps! IC is limited to )'#ps in Aast 'odeD and to 9!7 '#ps in Cigh Speed 'ode & this last one re5uiring specific I01 #uffers, not always easily a(aila#le! - legance: It is often said that IC is much more elegant than S I, and that this last one is a (ery rough (if not dum#) protocol! $ctually, we tend to thin2 the two protocols are e5ually elegant and compara#le on ro#ustness! IC is elegant #ecause it offers (ery ad(anced features & such as automatic multi-master conflicts handling and #uiltin addressing management & on a (ery light infrastructure! It can #e (ery comple<, howe(er and somewhat lac2s performance! S I, on the other hand, is (ery easy to understand and to implement and offers a great deal of fle<i#ility for e<tensions and (ariations! Simplicity is where the elegance of S I lies! S I should #e considered as a good platform for #uilding custom protocol stac2s for communication #etween ICs! So, according to the engineers need, using S I may need more wor2 #ut offers increased data transfer performance and almost total freedom! "oth S I and I,C offer good support for communication with low-speed de(ices, #ut S I is #etter suited to applications in which de(ices transfer data streams, while IC is #etter at multi master register access application! .sed properly, the two protocols offer the same le(el of ro#ustness and ha(e #een e5ually successful among (endors! 33 E1' (3lectrically-3rasa#le rogramma#le Eead-1nly 'emory), $BC ($nalog-to-Bigital Con(erter), B$C (Bigital-to-$nalog Con(erter), ETC (Eeal-time cloc2s), microcontrollers, sensors, >CB (>i5uid Crystal Bisplay) controllers are largely a(aila#le with IC, S I or the , interfaces!

!n the "orld o# communication protocols$ !%C and S&! are o#ten considered as 'little( communication protocols compared to thernet$ )SB$ S*T*$ &C!- +press and others$ that present throughput in the +100 megabit per second range i# not gigabit per second, Though$ one must not #orget "hat each protocol is meant #or, thernet$ )SB$ S*T* are meant #or 'outside the bo+ communications( and data e+changes bet"een "hole systems, -hen there is a need to implement a communication bet"een integrated circuitsuch as a microcontroller and a set o# relatively slo" peripheral$ there is no point at using any e+cessively comple+ protocols, There$ !%C and S&! per#ectly #it the bill and have become so popular that it is very likely that any embedded system engineer "ill use them during his/her career,

What is SPI?
SPI is a simple interface that allows one chip to communicate with one or more other chips.

How does it look?

Let's start with a simple example where only two chips have to communicate together. SPI re uires ! wires to "e used in "etween the two chips.

#s you can see$ the wires are called S%&$ '(SI$ 'IS( and SS)L$ and one of the chip is called the SPI master$ while the other the SPI slave.

SPI fundamentals
*asically+ ,. -. .. !. 0. It is synchronous. It is serial. It is full/duplex. It is not plug/and/play. 1here is one 2and only one3 master$ and one 2or more3 slaves.

In more details+ ,. # clock is generated "y the master$ and one "it of data is transferred each time the clock toggles. 2. 4ata is seriali5ed "efore "eing transmitted$ so that it fits on a single wire.

3. 1here are two wires for data$ one for each direction.
!. 0. 1he master and slave know "eforehand the details of the communication 2"it order$ length of data words exchanged$ etc...3 1he master is always the one who initiates communication.

*ecause SPI is synchronous and full/duplex$ every time the clock toggles$ two "its are actually transmitted 2one in each direction3.

Simple transfer
Let's assume that the master and slave expect 6/"its data transfers$ with 'S* transmitted first. Here's how would look a single 6/"its data transfer.

1he line '(SI is the 7master output7 while 'IS( is the 7slave output7. Since SPI is full/duplex$ "oth lines toggles simultaneously$ with different data going from master/to/slave$ and slave/to/master. In more datails+

,. -. ..

1he master pulls SS)L down to indicate to the slave that communication is starting 2SS)L is active low3. 1he master toggles the clock eight times and sends eight data "its on its '(SI line. #t the same time it receives eight data "its from the slave on the 'IS( line. 1he master pulls SS)L up to indicate that the transfer is over.

If the master had more than one 6/"its data to send8receive$ it could keep sending8receiving and de/ assert SS)L only when it is done.

'ultiple slaves
#n SPI master can communicate with multiples slaves "y connecting most signals in parallel and adding SS)L lines$ or "y chaining the slaves.

9ith the multiple SS)L lines techni ue$ only one SS)L line is actived at a time$ and slaves that are not selected must not drive the 'IS( line.

How fast is it?

SPI can easily achieve a few '"ps 2mega/"its/per/seconds3. 1hat means it can "e used for uncompressed audio$ or compressed video.


1he Serial Peripheral Interface Bus from 9ikipedia

SPI - A simple implementation

ARM processor
1o get an opportunity to test our newly ac uired SPI knowledge$ we use a Saxo-L "oard. It has an #:'; processor 2LP%-,.63 and a %yclone <P=# 2)P,%.3$ connected "y a SPI "us. 1he #:' is used as a SPI master$ while the <P=# is used as a SPI slave. 1he Saxo/L #:' processor has actually two SPI interfaces$ one called SPI>$ and a more advanced one called SPI,8SSP. 1hey are "oth e ually easy to use. 9e are using SPI,8SSP on Saxo/L$ as it is pre/wired on the "oard.

SPI master / % #:' code

?sing SSP is @ust a matter of initiali5ing a few registers$ and then writing8reading data to send8receive automatically. void main(void) { // initialize SSP SSP0CPSR = 0x02; SSP0CR0 = 0x07; SSP0CR P"#S$% )*ile( ) { // send t)o b+tes SSP0,R = 0x--; 2"23 SSP0,R = 0x-4; // one ni.e t*in/ abo0t t*e SSP is t*at it *as a 81)o!ds deep // so *e!e )e )!ite t*e data to be sent )it*o0t )o!!+in/ = 0x02; = 0x2&8; // SSP max speed // SSP max speed, 8 bits // SSP maste! mode // SSP mode 'o! pins P0( 7 to P0(20

// no) )ait 0ntil bot* b+tes a!e sent )*ile(5(SSP0SR 6 0x0 )); // no) )e .an !ead t*e t)o b+tes !e.eived((( and do an+t*in/ )it* t*em int data // ((( 7 7 = SSP0,R; int data2 = SSP0,R;

SPI slave / H4L <P=# code

Aow for the SPI slave in the <P=#. Since the SPI "us is typically much slower than the <P=# operating clock speed$ we choose to over/ sample the SPI "us using the <P=# clock. 1hat makes the slave code slightly more complicated$ "ut has the advantage of having the SPI logic run in the <P=# clock domain$ which will make things easier afterwards. <irst the module declaration. module SP"8slave(.l9, SC:, ;3S", ;"S3, SS$%, %$,); input .l9;

input SC:, SS$%, ;3S"; output ;"S3; output %$,; Aote that we have 7clk7 2the <P=# clock3 and an L)4 output... a nice little de"ug tool. 7clk7 needs to "e faster than the SPI "us. Saxo/L has a default clock of -!'H5$ which works fine here.

9e sample8synchroni5e the SPI signals 2S%&$ SS)L and '(SI3 using the <P=# clock and shift registers. // s+n. SC: to t*e 2P<& .lo.9 0sin/ a =1bits s*i't !e/iste! reg >2?0@ SC:!; always A(posedge .l9) SC:! B= {SC:!> ?0@, SC:7; wire SC:8!isin/ed/e = (SC:!>2? @==2Cb0 ); // no) )e .an dete.t SC: !isin/ ed/es wire SC:8'allin/ed/e = (SC:!>2? @==2Cb 0); // and 'allin/ ed/es // same t*in/ 'o! SS$% reg >2?0@ SS$%!; always A(posedge .l9) SS$%! B= {SS$%!> ?0@, SS$%7; wire SS$%8a.tive = DSS$%!> @; // SS$% is a.tive lo) wire SS$%8sta!tmessa/e = (SS$%!>2? @==2Cb 0); // messa/e sta!ts at 'allin/ ed/e wire SS$%8endmessa/e = (SS$%!>2? @==2Cb0 ); // messa/e stops at !isin/ ed/e // and 'o! ;3S" reg > ?0@ ;3S"!; always A(posedge .l9) ;3S"! B= {;3S"!>0@, ;3S"7; wire ;3S"8data = ;3S"!> @; Aow receiving data from the SPI "us is easy. // )e *andle SP" in 81bits 'o!mat, so )e need a = bits .o0nte! to .o0nt t*e bits as t*e+ .ome in reg >2?0@ bit.nt; reg b+te8!e.eived; // *i/* )*en a b+te *as been !e.eived

reg >7?0@ b+te8data8!e.eived; always A(posedge .l9) begin if(DSS$%8a.tive) bit.nt B= =Cb000; else if(SC:8!isin/ed/e) begin bit.nt B= bit.nt E =Cb00 ; // implement a s*i't1le't !e/iste! (sin.e )e !e.eive t*e data ;SF 'i!st) b+te8data8!e.eived B= {b+te8data8!e.eived>G?0@, ;3S"8data7;

end end always A(posedge .l9) b+te8!e.eived B= SS$%8a.tive 66 SC:8!isin/ed/e 66 (bit.nt===Cb ); // )e 0se t*e %SF o' t*e data !e.eived to .ont!ol an %$, reg %$,; always A(posedge .l9) if(b+te8!e.eived) %$, B= b+te8data8!e.eived>0@; <inally the transmission part. reg >7?0@ b+te8data8sent; reg >7?0@ .nt; always A(posedge .l9) if(SS$%8sta!tmessa/e) .ntB=.ntE8C* ; always A(posedge .l9) if(SS$%8a.tive) begin if(SS$%8sta!tmessa/e) b+te8data8sent B= .nt; else if(SC:8'allin/ed/e) begin if(bit.nt===Cb000) b+te8data8sent B= 8C*00; else b+te8data8sent B= {b+te8data8sent>G?0@, end end assign ;"S3 = b+te8data8sent>7@; // send ;SF 'i!st Cb07; // a'te! t*at, )e send 0s // 'i!st b+te sent in a messa/e is t*e messa/e .o0nt // .o0nt t*e messa/es

// )e ass0me t*at t*e!e is onl+ one slave on t*e SP" b0s // so )e donCt bot*e! )it* a t!i1state b0''e! 'o! ;"S3 // ot*e!)ise )e )o0ld need to t!i1state ;"S3 )*en SS$% is ina.tive endmodule 9e have esta"lished communication "etween the #:' and the <P=#B

:unning the code

#s we step through the #:' code$ we can see the L)4 changing state$ and the data returned "y the <P=#.

Aow let's see if we can do useful things with SPI.

SPI - Application
L%4 interface
Since we already know how to drive a graphic L%4 panel$ in particular in text mode$ let's try to write text out from the LP%. <rom the <P=# point of view$ the L%4 controller uses a few "lockrams to hold the font$ characters to display$ etc... So we @ust have to make sure that SPI data gets into the "lockrams. <rom the #:' point of view$ the function that sends data to the L%4 "lockrams is called 7SSPC9rite*lock7. // '0n.tion 0sed to )!ite in t*e %C, blo.9!ams void SSP8H!iteFlo.9(.*a!I ob, int len, int add!);

void %C,8P0tSt!in/(.*a!I s, int x, int +) { // t*e blo.9!am t*at *olds t*e .*a!a.te!s sta!ts at add!ess 0, and *ave 80 .*a!a.te!s pe! line SSP8H!iteFlo.9(s, st!len(s), xE+I80); 7 void main(void) { SSP8init(); %C,8P0tSt!in/(JKello )o!ld5J, 0, 0); %C,8P0tSt!in/(J2P<&42L#(C3; 1 )*e!e 2P<&s a!e '0n(J, 4, =); %C,8P0tSt!in/(JC*a! set?J, 0, 7); int i; 'o!(i=0; iB 28; iEE) %C,8P0tC*a!(i, i, 8); %C,8C0!so!8o''(); 7 #fter configuring the <P=# with the L%4 controller$ and running the #:' code$ here's what we get+

'ore ideas of pro@ects

Interface to a SPI flash memory %reate a complete console or =?I on the L%4 %reate an em"edded scope using <lashyD<P=#D#:'DL%4


Eour turn to experimentB