Decoders

A decoder is a multiplexer whose inputs are all constant with distinct one-hot (or one-cold) coded values. Please refer to the "Multiplexers" section of this chapter for more details. This section shows two examples of 1-of-8 decoders using One-Hot and One-Cold coded values.

Log File
The XST log file reports the type and size of recognized decoders during the macro recognition step: Synthesizing Unit <dec>. Related source file is decoders_1.vhd. Found 1-of-8 decoder for signal <res>. Summary: inferred 1 Decoder(s). Unit <dec> synthesized. ============================== HDL Synthesis Report Macro Statistics # Decoders : 1 1-of-8 decoder : 1 ============================== ... The following table shows pin definitions for a 1-of-8 decoder.

IO pins Description
s[2:0] res Selector Data Output

Related Constraints
A related constraint is decoder_extract.

VHDL (One-Hot)
Following is the VHDL code for a 1-of-8 decoder.

library ieee;
use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0);

res: out std_logic_vector end dec; architecture archi of dec is begin res <= "00000001" when sel = "00000010" when sel = "00000100" when sel = "00001000" when sel = "00010000" when sel = "00100000" when sel = "01000000" when sel = "10000000"; end archi;

(7 downto 0));

"000" "001" "010" "011" "100" "101" "110"

else else else else else else else

Verilog (One-Hot)
Following is the Verilog code for a 1-of-8 decoder. module mux (sel, res); input [2:0] sel; output [7:0] res; reg [7:0] res; always @(sel or res) begin case (sel) 3'b000 : res = 8'b00000001; 3'b001 : res = 8'b00000010; 3'b010 : res = 8'b00000100; 3'b011 : res = 8'b00001000; 3'b100 : res = 8'b00010000; 3'b101 : res = 8'b00100000; 3'b110 : res = 8'b01000000; default : res = 8'b10000000; endcase end endmodule

VHDL (One-Cold)
Following is the VHDL code for a 1-of-8 decoder. library ieee; use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; architecture archi of dec is begin res <= "11111110" when sel = "000" else "11111101" when sel = "001" else "11111011" when sel = "010" else "11110111" when sel = "011" else "11101111" when sel = "100" else "11011111" when sel = "101" else "10111111" when sel = "110" else "01111111"; end archi;

Verilog (One-Cold)
Following is the Verilog code for a 1-of-8 decoder. module mux (sel, res); input [2:0] sel; output [7:0] res; reg [7:0] res; always @(sel) begin case (sel) 3'b000 : res = 8'b11111110; 3'b001 : res = 8'b11111101; 3'b010 : res = 8'b11111011; 3'b011 : res = 8'b11110111; 3'b100 : res = 8'b11101111; 3'b101 : res = 8'b11011111; 3'b110 : res = 8'b10111111; default : res = 8'b01111111; endcase end endmodule In the current version, XST does not infer decoders if one or several of the decoder outputs are not selected, except when the unused selector values are consecutive and at the end of the code space. Following is an example:

IO pins Description
s[2:0] res Selector Data Output

VHDL
Following is the VHDL code. library ieee; use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; architecture archi of dec is begin res <= "00000001" when sel = "000" else -- unused decoder output "XXXXXXXX" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else "01000000" when sel = "110" else "10000000"; end archi;

Verilog
Following is the Verilog code. module mux (sel, res); input [2:0] sel; output [7:0] res; reg [7:0] res; always @(sel) begin case (sel) 3'b000 : res = 8'b00000001; // unused decoder output 3'b001 : res = 8'bxxxxxxxx; 3'b010 : res = 8'b00000100; 3'b011 : res = 8'b00001000; 3'b100 : res = 8'b00010000; 3'b101 : res = 8'b00100000; 3'b110 : res = 8'b01000000; default : res = 8'b10000000; endcase end endmodule On the contrary, the following description leads to the inference of a 1-of-8 decoder.

IO pins Description
s[2:0] res Selector Data Output

VHDL
Following is the VHDL code. library ieee; use ieee.std_logic_1164.all; entity dec is port (sel: in std_logic_vector (2 downto 0); res: out std_logic_vector (7 downto 0)); end dec; architecture archi of dec is begin res <= "00000001" when sel = "000" else "00000010" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else

"00100000" when sel = "101" else -- 110 and 111 selector values are unused "XXXXXXXX"; end archi;

Verilog
Following is the Verilog code. module mux (sel, res); input [2:0] sel; output [7:0] res; reg [7:0] res; always @(sel or res) begin case (sel) 3'b000 : res = 8'b00000001; 3'b001 : res = 8'b00000010; 3'b010 : res = 8'b00000100; 3'b011 : res = 8'b00001000; 3'b100 : res = 8'b00010000; 3'b101 : res = 8'b00100000; // 110 and 111 selector values are unused default : res = 8'bxxxxxxxx; endcase end endmodule