CIRCUITS FREQUENTLY MET IN THE INDUSTRIAL ASSEMBLIES Bipolar technologies and MOS until now are used in the

industrial circuits. That it is for maintenance or the realization, it is important to know not only technology, but also the inventory of the circuits with their function. ach manufacturer uses codes which it prints on the cases in order to be able to identify them. Still these codes should be known. !t is the role of figures " and # which give the significance of the codes of name of logical circuits TTL and C-MOS.

The two paragraphs which follow respectively provide the functions and the stitching of logical circuits TTL $bipolar% whereas the two last pursue the same goals but in technology C.MOS. 1. 1. - INVENTORY OF THE CIRCUITS OF LOGIC : FAMILY TTL To know certai !titc"i #! or their connections of the integrated circuits, it is enough to pass your pointer on the bonds hereafter:
&'(( ) &'(" ) &'(# ) &'(/ ) &'(' ) &'(1 ) &'(0 ) &'(& ) &'(2 ) *uadruple door )OT + ,)- at # entries *uadruple door )OT + ,)- at # entries with open collector *uadruple door )OT + O. at # entries *uadruple door )OT + ,)- at # entries with open collector 0 reversers 0 reversers with open collector 0 stages of attack reverser to open collector for '( my 0 stages of attack to open collector for '( my *uadruple door ,)- at # entries

&'(3 ) &'"( ) &'"" ) &'"# ) &'"/ ) &'"' ) &'"0 ) &'"& ) &'#( ) &'## ) &'#/ ) &'#1 ) &'#0 ) &'#& ) &'#2 ) &'/( ) &'/# ) &'/& ) &'/2 ) &''( ) &''# ) &''/ ) &''' ) &''1 ) &''0 ,) &''& ,) &''2 ) &'1( ) &'1" ) &'1/ ) &'1' ) &'0( ) &'&( ) &'&# ) &'&/ ) &'&' ) &'&1 ) &'&0 ) &'2( ) &'2" )

*uadruple door ,)- at # entries with open collector Triple carries )OT + ,)- at / entries Triple carries ,)- to / entry Triple carries )OT + ,)- at / entries with open collector -ouble door )OT + ,)- at ' entries 0 reversers trigger 0 reversers of powers to open collector 0 stages of attack to open collector for '( my -ouble door )OT + ,)- at ' entries -ouble door )OT + ,)- at ' entries with open collector -ouble door )OT + O. at ' entries e4pansible and strobe -ouble door )OT + O. at ' entries and strobe *uadruple door )OT + ,)- with # entries + 5igh voltage Triple carries )OT + O. at / entries *uadruple )O. door at # entries 6arry )OT + ,)- at 2 entries *uadruple door O. at # entries *uadruple door )OT + ,)- of power at # entries *uadruple door )OT + ,)- of power at # entries and open collector -ouble door )OT + ,)- of power at ' entries -ecimal decoder B6-ecoder e4cesses of / + decimal -ecoder e4cesses of / 7ray + decimal -ecimal decoder B6- with open collector for 2( my and /( 8 or "1 8 -ecoder B6- & segments with open collector with /( 89#( my -ecoder B6- & segments with open collector with /( 89#( my -ecoder B6- & segments -ouble door ,)-9O. + )OT to # : # entries -ouble door reverser ,)-9O. + )OT to # : # entries 6arry reverser ,)-9O. + )OT to ' : # entries e4pansible 6arry reverser ,)-9O. + )OT to ' : # entries -ouble door of multiplication at ' entries ;lip+flop <= to # : / entries Main flip+flop slave with # : / entries Main flip+flop slave with entry reset -ouble ;lip+flop - synchronous *uadruple ;lip+flop - asynchronous -ouble main ;lip+flop <= slave with entries set and reset ;ull adder with " bit Memory with "0 bits writing9reading

&'2# ) &'2/ ,) &'2' ,) &'21 ) &'20 ) &'23 ) &'3( ,) &'3" ,) &'3# ) &'3/ ) &'3' ) &'31 ,) &'30 ) &'3& ) &'"(( ) &'"(& ) &'""( ) &'""" ) &'""2 ) &'"#( ) &'"#" ) &'"## ) &'"#/ ) &'"#1 ) &'"/# ) &'"'" ,) &'"'# ) &'"'1 ) &'"'2 ) &'"1( ) &'"1" ) &'"1/ ) &'"1' ) &'"11 ) &'"10 ) &'"1& ) &'"0( ) &'"0" ) &'"0# ) &'"0/ )

;ull adder with # bits ;ull adder with ' bits Memory with "0 bits writing9reading at # entries of writing and reading Binary comparator with ' bits *uadruple door O. 4clusive Memory with 0' bits writing9reading with open collector -ecimal scaler .egister with shift with 2 bits series -ivider by "# Binary counter .egister with shift ' bits at parallel entry .egister with shift ' bits entered and ' parallel ports .egister with parallel shift 1 bits -ivider of synchronous binary fre>uency programmable 0 bits Octo+;lip+failure -ouble main ;lip+flop <= slave with entry reset Main flip+flop <= slave with blocking of entry -ouble main ;lip+flop <= slave with blocking of entry Si4fold ;lip+flop .S at common entry of reset -ouble synchronization of impulses Monostable Monostable red?clenchable at entry reset -ouble monostable red?clenchable at entry reset ' doors @ S at e4its / states *uadruple Trigger de Schmitt )OT + ,)- at # entries -ecimal decoder B6- for tubes of posting -ecimal scaler and ordering of )!:! -ecimal decoder B6- with open collector for 2( my and /( 8 or "1 8 2 To / Aine Briority ncoder Selector of data "0 bits9multiple4er Selector of data 2 bits9multiple4er -ouble selector of data ' bits9multiple4er Binary decoder ' bits9demultiple4er -ouble binary decoder # bits9demultiple4er -ouble binary decoder # bits9demultiple4er *uadruple selector of information # bits9multiple4er Synchronous decimal scaler at entry of set and reset Synchronous decimal scaler at entry of set and reset Synchronous binary counter ' bits at entry of set and reset Synchronous binary counter ' bits at entry of set and reset

&'"0' ) &'"01 ) &'"00 ) &'"0& ) &'"&( ) &'"&' ) &'"&1 ) &'"2( ) &'"2" ) &'"2' ) &'"21 ,) &'"3( ) &'"3" ) &'"3# ) &'"3/ ) &'"3' ) &'"31 ) &'"30 ) &'"3& ) &'"32 ) &'"33 ) &'AS#'" &'AS#'# &'AS#'/ 2"AS31 2"AS3&

.egister with shift 2 bits at parallel port .egister shift 2 bits at parallel entry .egister with synchronous shift 2 bits at parallel entry -ivider of fre>uencies, decimal Memory with "0 bits writing9reading with words to ' bits Si4fold ;lip+flop - at entry of reset *uadruple ;lip+flop - synchronous Barity check 2 bits ,rithmetic logical unit ' bits Binary converter B6- 0 bits Binary converter B6- 0 bits .eversible decimal scaler for synchronous counting chain .eversible binary counter for synchronous counting chain Meter decimal discounting machine with set and reset Binary meter discounting machine with set and reset .egister with synchronous ' bits right+hand side9left parallel shift .egister with synchronous shift parallel ' bits with entry <= -ecimal scaler 1( M5z with entry of set and reset Binary counter 1( M5z with entry of set and reset .egister with synchronous shift 2 bits at entry and port parallel .egister with synchronous shift 2 bits parallel at entry <= -river of bus not reverser *uad drunk transceiver inverting ' transcoders not reverser / states &'&31 : Octal Buffer with Three+State Outputs $&'AS&31 is e>uivalent to 2"AS31% &'&3& : Octal Buffer with Three+State Outputs $&'AS&3& is e>uivalent to 2"AS3&%

1. $. - STITCHING OF THE CIRCUITS OF LOGIC : FAMILY TTL

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".

". /. + !)8 )TO.@ O; T5 6!.6C!TS O; AO7!6 D ;,M!A@ 6.MOS

5 ; '((( '((" '((# '((0 '((& '((2 '("" '("# '("/ '("' '("1 '("0 '("& '("2 '("3 '(#( '(#" '(## '(#/ '(#' '(#1 '(#& '(#2 '(#3 '(/( '(/" '(/1 '('( '('" '('# '('/ '('' '('0

-ouble door )OT + O. at / entries E reverser *uadruple door )OT + O. at # entries -ouble door )OT + O. at ' entries .egister with static shift "2 stages -ouble complementary pair E reverser ,dder ' bits with reserve *uadruple door )OT + ,)-ouble door )OT + ,)- at ' entries -ouble rocker .egister with shift 2 bits -ouble register with shift ' bits *uadruple bidirectional switch <ohnson meter on 1 floors -ividing meter by FnF programmable *uadruple multiple4er at # entries Binary counter on "' floors .egister with shift 2 bits <ohnson meter on ' floors, divider by 2 Triple carries )OT + ,)- at / entries Binary counter on & floors Triple carries )OT + O. at / entries -ouble rocker < + = -ecoder B6- + decimal $" among "(% Meter 9 synchronous, binary9decimal discounting machine *uadruple :6ACS!8 +O. door .egister with shift 0' bits .egister with universal shift ' bits Binary counter on "# floors *uadruple door of power with complementary e4it *uadruple rocker - with locking *uadruple rocker )OT + O. + . 9 S with locking $left / states% *uadruple rocker )OT + ,)- + . 9 S with locking $left / states% Buckle with controlled phase $BAA%

'('& '('3 '(1( '(1" '(1# '(1/ '(1' '(10 '(0( '(00 '(0& '(02 '(03 '(&( '(&" '(&# '(&/ '(&1 '(&2 '(2" '(2# '(21 '(20 '(3/ '(32 '"(' '1"( '1"" '1"' '1"1 '1"0 '1"2 '1"3 '1#( '1#2 '1/3 '111 '110 '&#( '&#" '&#' '&/0 '((3& '((32 '("(0 '("&' '("&1 '("3# '("3/ '("3' '("31

Monostable Si4fold door of power $reverser% Si4fold door of power $not + reverser% ,nalogical multiple4er9demultiple4er with 2 channels -ouble multiple4er9analogical demultiple4er with ' channels Triple analogical multiple4er9demultiple4er with # channels -river for bill+poster ' segments A6-ecoder B6- for bill+poster & segments A6, meter+divider "' stages with oscillator *uadruple bidirectional switch Multiple4er "0 + " 6arry )OT + ,)- at 2 entries Si4fold reverser *uadruple :6ACS!8 +O. door *uadruple door O. at # entries -ouble door O. at ' entries Triple carries ,)- at / entries Triple carries O. at / entries 6arry )OT + O. at 2 entries *uadruple door ,)- at # entries -ouble door ,)- at ' entries -ouble door ,)- 9 O. + )OT to # 4 # entries -oor ,)- 9 O. + )OT to ' 4 # entries *uadruple trigger of Schmitt ),)- at # entries -ouble monostable red?clenchable *uadruple translator of tension at e4it / states Meter 9 discounting machine B6-ecoder 9 driver & segments -ecoder 9 demultiple4er " among "0, with register of entry $high e4it% -ecoder 9 demultiple4er " among "0, with register of entry $low e4it% Binary meter 9 discounting machine -ouble decimal scaler *uadruple multiple4er at # entries -ouble binary counter -ouble monostable red?clenchable -ouble multiple4er at ' entries -ouble decoder 9 demultiple4er " among ' $high e4it% -ouble decoder9demultiple4er " among ' $low e4it% .ead+write memory #10 bits $#10 4 "% .ead+write memory "(#' bits $#10 4 '% ,ddressable register 2 bits with locking .ead+write memory " (#' $" (#' 4 "% Si4fold door of power, e4it / states $not reverser% Si4fold door of power, e4it / states $reverser% Si4 triggers of Schmitt reversers Si4fold rocker *uadruple rocker Meter 9 synchronous discounting machine ' bits decimal Binary meter 9 synchronous discounting machine ' bits .egister with bidirectional universal shift ' bits .egister with universal shift ' bits

1. %. - STITCHING OF THE CIRCUITS OF LOGIC : FAMILY CMOS

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MC 14511