2-Fundamentals On ADCs-Part 1

Fundamentals on ADCs: Part I J ose Silva-Martinez
FUNDAMENTALS OF ANALOG TO DIGITAL

CONVERTERS PART I 1
Jose Silva Martinez
CONVERTERS: PART I.1
Jose Silva-Martinez
Amesp02.tamu.edu/~jsilva
Many of these slides were provided by
Dr. Sebastian Hoyos
Amesp02.tamu.edu/~hoyos
January 2011
Texas A&M University 1 Spring, 2011
Outline
Fundamentals of Analog-to-Digital Converters
Introduction
Sampling and Quantization
Quantization noise and distortion
INL and DNL
S t Li it ti System Limitations
Linear Range
Stability
Clock Jitter Clock Jitter
Potential realizations
ADC architectures
SAR
Pi li (Ti i t l ) Pipeline (Time interleave)
Sigma-Delta
Folding
Flash
Conclusions
Conclusions
R. Walden, 1999
What is an Analog What is an Analog--to to- -Digital Converter (ADC)? Digital Converter (ADC)?
Analog Digital
0100101100101001010101010
1010100101001010010100101 1010100101001010010100101
0100100100100101100110010
10100100101001001010
Continuous with no apparent
discontinuities
The way we interpret our
Discrete with limited range;
based on binary numbers with
limited number of bits.
ADC
surroundings: sound, light,
temperature etc
The way we mathematically
represent and process our world
using electronic brain power
How does an ADC work? How does an ADC work?
Analog Digital
100101001
010010100
0100101100101001010101010
1010100101001010010100101 010010100
1001100101
1001010
1010100101001010010100101
0100100100100101100110010
10100100101001001010
Continuous with no apparent
discontinuities
The way we interpret our
ADC
Discrete with limited range;
based on binary numbers with
limited number of bits.
surroundings: sound, light,
temperature etc
The way we mathematically
represent and process our world
using electronic brain power
How does an ADC work? How does an ADC work?
x(t)
Analog
Digital
ADC
t
100101001
010010100
1001100101
1001010
Quantization
noise
1001010
x(n)
2
N
L l
(n)
nT
S
2
N
Levels
separated
by 1LSB,
1LSB =
V
FS
*
/ 2
N
nT
S
* V
FS
= full scale range, V
max
-V
min
ADCs: Yesterday vs. Today
Example: Digital photography (8-12b ADCs)
Yesterday: 2000 Today: 2009
DSP
(balance control, black level
compensation, image
stabilization, exposure levels,
noise reduction, lens shading
correction, encoding...etc)
AMP
CCD/
CMOS
Image
Array
ADC
0.5-0.8m CMOS with 5V supply (moderate gate density
and speed in DSPs)
2M pixel CCD sensor (low pixel scanning speed)
Some pre ADC analog conditioning
90nm-180nm CMOS with 1.2-1.8V supplies (high gate
density and speed in DSPs)
12M pixel CCD sensor (high pixel scanning speed)
Minimal pre ADC analog conditioning
ADCs are indispensable, but
now need to handle smaller
i l t hi h d ith
Some pre-ADC analog conditioning
~2.5mV / LSB
Minimal pre-ADC analog conditioning
~0.5mV / LSB
Faster DSPs capable of
performing numerous complex
f ti d l d th k
ADCs are becoming the
bottleneck for advancement, and
d i t h i d t
signals at higher speeds with
similar or higher resolutions.
functions are developed thanks
to advanced CMOS technologies.
new design techniques need to
be developed.
ADCs: Tomorrow? ADCs: Tomorrow?
ADC IEEE literature survey: 2006-2008
18
20
Pipeline ADC Applications
Today
8
10
12
14
16
o
l
u
t
i
o
n

(
b
i
t
s
)
Sigma-Delta
2
4
6
8
0 1 1 10 100 1000 10000
R
e
s
o
0 01
Sigma Delta
Pipelined
Flash
Tomorrow
Pipeline ADC is currently most published architecture
Pipeline ADC is breaking the trend set by Sigma-Delta
0.1 1 10 100 1000 10000
Signal Bandwidth (MHz)
0.01
Pipeline ADC is breaking the trend set by Sigma-Delta p g y g
and Flash ADCs
Pipeline ADC is expected to be a key ADC architecture in
future applications
The development of new design techniques for high speed, low voltage and low
15M?
20M?
From 1080P to
4K (2160P)?
4G?
HDTV?
p g y g
and Flash ADCs, and driven by consumer electronics
The development of new design techniques for high speed, low voltage and low
power Pipeline ADCs is crucial to stay on the future applications roadmap
Design Challenges of Pipeline ADCs in Design Challenges of Pipeline ADCs in
Advanced CMOS Technologies (Summary) Advanced CMOS Technologies (Summary)
High Speed Low Voltage Low Power
DSP
(balance control, black level
compensation, image
stabilization, exposure levels,
noise reduction, lens shading
correction encoding etc)
AMP
CCD/
CMOS
Image
Array
ADC
Digital Camera Example
correction, encoding...etc)
With the added speed of
newgenerations of DSPs the
Reduction of Device size
allows for denser integration
Many applications are
portable andoperatedfroma new generations of DSPs, the
ADC is becoming the
bottleneck for overall system
speed
in additionto increased
allows for denser integration,
but device reliability dictate
lower supply voltages
Reduced supplies means
reducedsignal range, which
portable and operated from a
battery
As a potentially power
hungry component, the ADC
power needs to be reduced in addition to increased
speed, the DSP ability to
perform more complex tasks
will require higher ADC
resolutions
reduced signal range, which
requires a higher ADC
accuracy for the same number
of bits
power needs to be reduced
to help prolong battery life
The Smartphone market The Smartphone market
Global Global smartphone smartphone market projected to grow market projected to grow Global Global smartphone smartphone market projected to grow market projected to grow
Anticipated global unit sales to approach 400 millions in 2013
(market research report from Forward Concepts Co)
Projected revenue in 2012: $32.2 billion
(source: In-Stat Group)
Multi Multi--standard Wireless Systems standard Wireless Systems Multi Multi standard Wireless Systems standard Wireless Systems
Multiple services
Reuse circuits as much as possible
Power
Area
Competitiveness
Smaller Cell phone,
stronger function,
longer battery duration
Use of digital (analog unfriendly)
g ( g y)
nanometric tecnologies
Multi Multi--standard Wireless Systems standard Wireless Systems
Exponential growth in mobile computing and broadband wireless
Major need for high dynamic range, wide-bandwidth, low power ADCs.
Multi Multi standard Wireless Systems standard Wireless Systems
Bandwidth requirements for higher connectivity Bandwidth requirements for higher connectivity
Higher flexibility on operational frequency and bandwidth,
higher blocker rejection higher dynamic range higher blocker rejection, higher dynamic range
Receiver Architectures:
Super-heterodyne Low-IF Direct Conversion High-IF Digital
Super-heterodyne, Low-IF, Direct Conversion, High-IF, Digital
Radio
Super-heterodyne Receiver p y
Invented by Armstrong in 1918
Hardware specific radio architecture
Extensive filtering to relax ADC specs
Suitable for narrow-band applications
Design issues for multi-standard solutions es g ssues o u t sta da d so ut o s
Limited by flicker
noise noise
Not flexible
Hardware intensive
Excessive power at the front-end (Linearity issues)
Extensive down conversions: LO and mixers increase
b h i d i both noise and power consumption
Extensive filtering: Area, Power and Noise issues
Not fully compatible for the Telecoms roadmap
Not fully compatible for the Telecoms roadmap
Current Multi Current Multi--standard designs standard designs Current Multi Current Multi standard designs standard designs
IF
Antenna
Receiver for standard 1 Minimum sharing of
BPF LNA BPF VGA
RF
(1-2 GHz)
IF
(100-200 MHz)
blocks
Area and power
LO2 LO1
Receiver for standard 2
p
consumption overhead
Not Flexible at all
RF
Switch
BPF LNA BPF VGA
RF
(1-2 GHz)
IF
(100-200 MHz)
Receiver for standard 2
Not Flexible at all
Limited number of
standards can be
LO2 LO1
standards can be
accommodated
Efficient radio transceiver: Direct Conversion
Antenna
16-Channel Multiband
Digital Receiver
Frequency
Synthesizer
RF
signal
Software
Platform
LNA & VGA RF Filter 1 ADC 1
IF Filter 1
80 MHz
4-
channel
digital
receiver
4-
channel
Mixer
DSP
or
FPGAs
digital
receiver
ADC 2
IF Filter 2
4-
channel
digital
receiver
Antenna
RF
signal
LNA & VGA RF Filter 2
Optional
Mixer
FPGAs
receiver
4-
channel
digital
receiver
Direct conversion + broadband ADC (1 receiver per service)
Lowpass filter is required (~ 50-100 mW)
13-14 bits 80 MHz Lowpass ADC (500 mW from ADI)
p ( )
Bank of receivers, filters and ADCs
Recent Approaches to Broadband Receivers Recent Approaches to Broadband Receivers pp pp
Sample rate, downsampling and filtering
R. Crochiere and L. Rabiner, Multirate Digital Signal Processing. Englewood Cliffs, NJ :
Prentice Hall, 1983. ,
Sampling with built-in anti-aliasing
Y. S. Poberezhskiy et.al. Sampling and signal reconstruction circuits performing internal
antialiasingfiltering and their influence on the design of digital receivers and antialiasing filtering and their influence on the design of digital receivers and
transmitters, TCASI, J an. 2004.
A discrete-time RF sampling receiver
R B Staszewski et al All digital TX frequency synthesizer and discrete time receiver for R. B. Staszewski, et. al. All-digital TX frequency synthesizer and discrete-time receiver for
Bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits, Dec. 2004.
SDR receiver
f f SSC Abidi, The path to software-defined radio receiver, IEEE J SSC, May 2007
Frequency-domain-sampling receivers
S. Hoyos and B. M. Sadler, Ultra-wideband analog to digital conversion via signal
y g g g
expansion, IEEE Transactions on Vehicular Technology, Sept. 2006.
UCLA SDR receiver UCLA SDR receiver
Direct conversion with tunable LO in the freq. range 800 MHz to 6 GHz.
Cascade of sinc
N
filters followed by decimation to achieve the initializing
needed.
Good for narrowband signals as a single ADC can handle the bandwidth. But g g
SDR should also be good for wideband and ultra-wideband signals. Need parallel
ADC to sample at a fraction of Nyquist rate. Parallelization of the front-end will be
needed if want to keep the ADC sampling rate down.
A. Abidi, The path to software-defined radio receiver, IEEE J SSC, May 2007
Frequency Frequency- -Domain ADC Based on Fourier Coefficients Domain ADC Based on Fourier Coefficients
( ) r t
0
R
0
R
( )
( 1)
c
c
m T
mT
dt
+
}
1
Tc
F0 F1 FN-1 F2
0
2 j F t
e
t
1 N
R
1
N
R
1
R
2
R
1 N
R

1
2
N
j F t t
1 N
( )
( 1)
c
c
m T
mT
dt
+
}
0
R
1 N
R

1
2
N
j F t
e
t

Mixers and integrators.
L f l d
No signal reconstruction. Parallel
di it l i Lower frequency sample and
hold requirements.
digital processing.
Optimal bit allocation minimizes
quantization error. Some
samples may not be quantized at all.
p y q
S. Hoyos and B. M. Sadler, Ultra-wideband analog to digital conversion via signal expansion, IEEE
Transactions on Vehicular Technology, Sept. 2006.
Roadmap for high Roadmap for high--resolution Receivers resolution Receivers p g p g
How much RF processing should be done before the ADC?
The front end must be scalable and configurable to fit multiple standards
The front-end must be scalable and configurable to fit multiple standards
The single The single--chip Transceiver Paradigm chip Transceiver Paradigm
22
gg p g p g
Modern technologies: Modern technologies:
Digital intensive System Digital intensive System on on Digital intensive System Digital intensive System--on on--
Chip (SOC) environment Chip (SOC) environment
Scaling of transistor dimensions in digital
CMOS t h l i CMOS technologies
Increased intra-die variability from device
scaling
D f t d iti i i Defect densities increase in newer
technologies
Yields decrease as SOC chip sizes increase
Yi ld i t l ifi ti l d Yield impact on analog specifications leads
to process corner-based overdesign
to allow for analog parameter variations
Increased test cost
Critical Analog components must be minimized Critical Analog components must be minimized
Increased test cost
M. Onabajo, 2011
Fast CMOS ADCs: State of the art Fast CMOS ADCs: State of the art
p
e
c
t
u
r
m
Trends:
Extensive use of parallelism
Freq (GHz)
S
5.4 2.4 2 1.9 1.0 0.05 0.8
Resolution
Time interleaved
Reduced supply voltages make
analog more challenging
16
14
Pipeline
Resolution
Headroom for amplifiers
Little room for cascoding
Poor devices if V
DS
is
Immediate Goal
12
10
8
Pipeline Interleaved
DS
further reduced
Use techniques that take
advantage of digital trends
6
4
10 MS/s 100MS/s 1GS/s 10GS/s 100GS/s
Flash
g g
Digital circuitry is cheap and fast
Tendency is Digitally Assisted
Analog Circuits
Sampling rate
g
Introduction to Analog Introduction to Analog--to to--Digital Converters Digital Converters gg gg
Analog-to-Digital Converters (ADC) are necessary to
convert real world signals (which are analog in nature) to convert real world signals (which are analog in nature) to
their digital equivalents for easy processing.
Common applications for ADCs are communication
systems, TV receivers, Digital Oscilloscopes, Audio
applications..
Analog
Software radio transceiver: Design Issues Software radio transceiver: Design Issues gg
Makes it sense to have a multi standard solution based on this Makes it sense to have a multi-standard solution based on this
architecture?
Bandwidth required?
D i i d? Dynamic range required?
DTV SNRsignal=25 dB; Blockers > 45 dB; Crest factor > 20 dB
LNA+VGA+ADC Dynamic Range over 90 dB (practical ?)
y g (p )
Can you use tracking filters? (back to the past)
Software radio transceiver: Ultimate goal Software radio transceiver: Ultimate goal gg
Concept introduced in 1991
Modulation/demodulation waveforms in software
Flexible multi-standard software architecture
Data Converters: The main issue Data Converters: The main issue
The quantized signal
presents a finite number presents a finite number
of output values that are
associated with digital
codes
codes
R. Walden, 1999
Where we were in 99? Where we are?
WiMAX
A Little bit of History A Little bit of History A Little bit of History A Little bit of History
A Little bit of History A Little bit of History A Little bit of History A Little bit of History
Jitter and noise limitations on ENOB Jitter and noise limitations on ENOB Jitter and noise limitations on ENOB Jitter and noise limitations on ENOB
Classic Classic FoM FoM to compare ADCs to compare ADCs Classic Classic FoM FoM to compare ADCs to compare ADCs
Recent Recent EA EA modulators modulators Recent Recent EA EA modulators modulators
Bandwidth (Nyquist in pipeline) vs. SNDR ( y )
1 E+10
1.E+11
ISSCC 1997-2009
VLSI 1997-2009
1.E+08
1.E+09
1.E+10
H
z
]
VLSI 1997 2009
ISSCC 2009
J itter=1psrms
J itter=100fsrms
1.E+06
1.E+07
B
W

[
H
1 E+03
1.E+04
1.E+05
1.E+03
10 20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
B. Murmann, " ADC Performance Survey 1997-2010, http://www.stanford.edu/~murmann/adcsurvey.html.
Energy per conversion at Nyquist rate gy p yq
1 E+06
1.E+07
1.E+04
1.E+05
1.E+06
[
p
J
]
1.E+02
1.E+03
P
/
f
s
[
ISSCC 2010
1.E+00
1.E+01
ISSCC 2010
ISSCC 1997-2009
VLSI 1997-2009
FOM=100fJ /conv-step
FOM=10fJ /conv-step
1.E-01
10 20 30 40 50 60 70 80 90 100 110 120
SNDR [dB]
p
B. Murmann, " ADC Performance Survey 1997-2010, http://www.stanford.edu/~murmann/adcsurvey.html.
What the problem is? p
Issues: Sampling, Holding and conversion Issues: Sampling, Holding and conversion p g, g p g, g
The quantized signal
presents a finite number presents a finite number
of output values that are
associated with digital
codes
codes
Properties of the Fourier Series Properties of the Fourier Series
Properties of the Fourier Series Properties of the Fourier Series pp
Modulation properties Modulation properties Modulation properties Modulation properties
Convolution in time Convolution in time
Relevant properties of the Fourier Series Relevant properties of the Fourier Series p p p p
Relevant properties of the Fourier Series Relevant properties of the Fourier Series p p p p
Additional properties of the Fourier Series Additional properties of the Fourier Series p p p p
Define the problem: Sampling Operation p p g p
Signal Sampling Theorem Signal Sampling Theorem g p g g p g
Time Time
domain domain
sampling sampling
Frequency Frequency
Spectrum Spectrum
Signal Sampling employing a train of Signal Sampling employing a train of g p g p y g g p g p y g
pulses pulses Time domain sampling with Time domain sampling with
pulses pulses
Spectrum Spectrum
Sampling Operation: Sampling Operation: Nyquist Nyquist Rate Rate p g p p g p yq yq
According to the sampling theorem: If no g p g
alias issues, then
Ideal sampling does not Ideal sampling does not
dd di t ti b t dd di t ti b t add distortion but add distortion but
replicas of the original replicas of the original
tt
spectrum spectrum
Alias issue if Alias issue if undersampling undersampling p g p g
Under-sampling of a broadband signal p g g
S/H and Quantization errors S/H and Quantization errors
The sampling and Held operations generate alias
frequency components and (sinc) signal distortion,
respectively
QQ
respectively
Error is an odd function (no even harmonic distortions,
why?)
Quantization generates harmonic distortion components
when sinusoidal input signals are used
( ) ( ) ( ) t Err or t S t S
q i n
+ =
Distortion due to quantization errors Distortion due to quantization errors qq
ADC ADC metrics: Quantization error metrics: Quantization error
Signal is sampled at given instants
Signal is encoded to a limited number of codes resulting in
quantization noise (random signals) and distortion (periodic signals)
What the fundamental problem is? What the fundamental problem is? What the fundamental problem is? What the fundamental problem is?
Mapping an Mapping an
infinite infinite
resolution resolution
analog signal analog signal
into a digital into a digital
but finite but finite but finite but finite
resolution resolution
representation representation
Quantization noise for Random (Ramp) input signal Quantization noise for Random (Ramp) input signal
ADC ADC metrics: SQNR metrics: SQNR
The maximum Signal-to-Quantization Noise
ratio (SQNR) for an N bit ADC:
QQ
( )
dB . N .
/ / A
P
SQNR
N
signal
ideal
76 1 02 6
2 2 2
2
2
2
+ =
A
= = =
ratio (SQNR) for an N-bit ADC:
/ P P
Q
noise noise
ideal
12
2
A
For anADC ith a meas red SNDR the effecti e For an ADC with a measured SNDR, the effective
number of bits is defined as:
02 . 6
76 . 1 ) dB ( SNDR
ENOB

=
Quantization noise density Quantization noise density
The dynamic range of a system is equal to the signal to noise ratio measured The dynamic range of a system is equal to the signal to noise ratio measured
over a bandwidth equal to half of the sampling ( over a bandwidth equal to half of the sampling (Nyquist Nyquist) frequency ) frequency
Then, Then,
2
2
12
q
= o
Is the total while the quantization noise density Is the total while the quantization noise density
(quantization noise measured in a bandwidth of 1 Hz) (quantization noise measured in a bandwidth of 1 Hz)
2 2
s
2
s
2
f 6
q
f
2
densit y Noi se = =
o
fs/2 -fs/2
Practical Limitations Practical Limitations Practical Limitations Practical Limitations
Digital to Analog Converters Digital to Analog Converters g g g g
Practical Definitions Practical Definitions
Quite critical issue! Usually not a major issue Quite critical issue! Usually not a major issue
Quite critical issue! Usually not a major issue Quite critical issue! Usually not a major issue
Practical Limitations: Offset error Practical Limitations: Offset error Practical Limitations: Offset error Practical Limitations: Offset error
Practical Limitations Practical Limitations
j i Q i i i i ! j i Q i i i i !
Usually not a major issue Quite critical issue! Usually not a major issue Quite critical issue!
Practical Limitations: Gain error Practical Limitations: Gain error Practical Limitations: Gain error Practical Limitations: Gain error
Practical Limitations: Differential Error Practical Limitations: Differential Error Practical Limitations: Differential Error Practical Limitations: Differential Error
Practical Limitations: Integral error Practical Limitations: Integral error Practical Limitations: Integral error Practical Limitations: Integral error
Practical Limitations: Absolute Accuracy Practical Limitations: Absolute Accuracy yy
Analog to Digital Converters Analog to Digital Converters g g g g
Usually the effects Usually the effects
of the systematic of the systematic of the systematic of the systematic
offsets can be offsets can be
minimized through minimized through
calibration or calibration or
accounted in accounted in
digital domain digital domain
Digital to Analog Converters Digital to Analog Converters g g g g
DNL b ll l 1 LSB DNL b ll l 1 LSB
DNL must be smaller or equal to 1 LSB DNL must be smaller or equal to 1 LSB
Offset Voltages Offset Voltages gg

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Fundamentals on ADCs: Part I J ose Silva-Martinez

FUNDAMENTALS OF ANALOG TO DIGITAL

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