SEMICONDUCTOR TECHNICAL DATA


 
L SUFFIX
CERAMIC
CASE 620

The MC14049UB hex inverter/buffer is constructed with MOS Pchannel

and Nchannel enhancement mode devices in a single monolithic structure.
This complementary MOS device finds primary use where low power
dissipation and/or high noise immunity is desired. This device provides
logiclevel conversion using only one supply voltage, VDD. The inputsignal
high level (V IH ) can exceed the V DD supply voltage for logiclevel
conversions. Two TTL/DTL Loads can be driven when the device is used as
CMOStoTTL/DTL converters (VDD = 5.0 V, VOL
0.4 V, IOL 3.2 mA).
Note that pins 13 and 16 are not connected internally on this device;
consequently connections to these terminals will not affect circuit operation.

P SUFFIX
PLASTIC
CASE 648

High Source and Sink Currents

HightoLow Level Converter
Supply Voltage Range = 3.0 V to 18 V
Meets JEDEC UB Specifications
VIN can exceed VDD
Improved ESD Protection on All Inputs

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Rating

Symbol

Value

Unit

VDD

0.5 to + 18

Input Voltage (DC or Transient)

Vin

0.5 to + 18

Output Voltage (DC or Transient)

Vout

0.5 to VDD + 0.5

Iin

10

mA

Output Current (DC or Transient), per Pin

Iout

+ 45

mA

Power Dissipation, per Package

Plastic/Ceramic
SOIC

PD

Storage Temperature

Tstg

65 to + 150

_C

TL

260

_C

DC Supply Voltage

Input Current (DC or Transient), per Pin

Lead Temperature (8Second Soldering)

mW

825
740

* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating: All Packages: See Figure 4.

CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
MC14049UB
VDD

D SUFFIX
SOIC
CASE 751B

ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD

Plastic
Ceramic
SOIC

TA = 55 to 125C for all packages.

LOGIC DIAGRAM
MC14049UB
3

10

11

12

14

15
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1

VSS
REV 3
1/94

MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA

MC14049UB
1

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Output Voltage
Vin = VDD or 0

Symbol

55_C

25_C

125_C

VDD
Vdc

Min

Max

Min

Typ

Max

Min

Max

Unit

0 Level

VOL

5.0
10
15

0.05
0.05
0.05

0
0
0

0.05
0.05
0.05

0.05
0.05
0.05

Vdc

1 Level

VOH

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

5.0
10
15

4.95
9.95
14.95

Vdc

0 Level

VIL

5.0
10
15

1.0
2.0
2.5

2.25
4.50
6.75

1.0
2.0
2.5

1.0
2.0
2.5

5.0
10
15

4.0
8.0
12.5

4.0
8.0
12.5

2.75
5.50
8.25

4.0
8.0
12.5

5.0
10
15

1.6
1.6
4.7

1.25
1.3
3.75

2.5
2.6
10

1.0
1.0
3.0

IOL

5.0
10
15

3.75
10
30

3.2
8.0
24

6.0
16
40

2.6
6.6
19

mAdc

Input Current

Iin

15

0.1

0.00001

0.1

1.0

Adc

Input Capacitance
(Vin = 0)

Cin

10

20

pF

Quiescent Current
(Per Package)

IDD

5.0
10
15

1.0
2.0
4.0

0.002
0.004
0.006

1.0
2.0
4.0

30
60
120

Adc

IT

5.0
10
15

Vin = 0 or VDD

Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)

1 Level

VIH

(VO = 0.5 Vdc)

(VO = 1.0 Vdc)
(VO = 1.5 Vdc)

Output Drive Current

(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

Vdc

Vdc

IOH

Source

Sink

Total Supply Current**

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

mAdc

IT = (1.8 A/kHz) f + IDD

IT = (3.5 A/kHz) f + IDD
IT = (5.3 A/kHz) f + IDD

Adc

#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

** The formulas given are for the typical characteristics only at 25_C.
To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL 50) Vfk

where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14049UB
2

MOTOROLA CMOS LOGIC DATA

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)

Characteristic

Symbol

Output Rise Time

tTLH = (0.8 ns/pF) CL + 60 ns
tTLH = (0.3 ns/pF) CL + 35 ns
tTLH = (0.27 ns/pF) CL + 26.5 ns

tTLH

Output Fall Time

tTHL = (0.3 ns/pF) CL + 25 ns
tTHL = (0.12 ns/pF) CL + 14 ns
tTHL = (0.1 ns/pF) CL + 10 ns

tTHL

Propagation Delay Time

tPLH = (0.38 ns/pF) CL + 61 ns
tPLH = (0.20 ns/pF) CL + 30 ns
tPLH = (0.11 ns/pF) CL + 24.5 ns

tPLH

Propagation Delay Time

tPHL = (0.38 ns/pF) CL + 11 ns
tPHL = (0.12 ns/PF) CL + 9 ns
tPHL = (0.11 ns/pF) CL + 4.5 ns

tPHL

VDD
Vdc

Min

Typ #

Max

5.0
10
15

100
50
40

160
100
60

5.0
10
15

40
20
15

60
40
30

5.0
10
15

80
40
30

120
65
50

5.0
10
15

30
15
10

60
30
20

Unit
ns

ns

ns

ns

* The formulas given are for the typical characteristics only at 25_C.
#Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

Vout , OUTPUT VOLTAGE (Vdc)

18
15

10

VDD = 15 Vdc

VDD = 10 Vdc

55C

VDD = 5 Vdc
+125C

5
10
Vin, INPUT VOLTAGE (Vdc)

15

18

Figure 1. Typical Voltage Transfer Characteristics versus Temperature

MOTOROLA CMOS LOGIC DATA

MC14049UB
3

VDD
1

VDD
1
IOH
8

IOL

VOH
8

VSS
VDS = VOH VDD

VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)

0
I OH , OUTPUT SOURCE CURRNT (mAdc)

VOL

VSS

VGS = 5.0 Vdc

10

VGS = 15 Vdc

120

20
VGS = 10 Vdc

30

40

VGS = 15 Vdc

50
10

MAXIMUM CURRENT LEVEL

8.0
6.0
4.0
2.0
VDS, DRAINTOSOURCE VOLTAGE (Vdc)

VGS = 10 Vdc

80

MAXIMUM CURRENT LEVEL

40
VGS = 5.0 Vdc
0

Figure 2. Typical Output Source Characteristics

2.0
4.0
6.0
8.0
VDS, DRAINTOSOURCE VOLTAGE (Vdc)

10

Figure 3. Typical Output Sink Characteristics

VDD

PD , MAXIMUM POWER DISSIPATION (mW)

PER PACKAGE

1
PULSE
GENERATOR

1200
1100
1000

Vout

Vin
8

900
825
800
740
700
600

20 ns

(L) CERAMIC

INPUT

(P) PDIP

CL

VSS

20 ns
VDD

90%
50%

500
400

10%

300

(D) SOIC

200
100
0
25

50

75
100
125
TA, AMBIENT TEMPERATURE (C)

260 mW (L)
175 mW (P)
120 mW (D)
150

175

Figure 4. Ambient Temperature Power Derating

This device contains circuitry to protect the inputs against damage

due to high static voltages or electric fields referenced to the VSS pin,
only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high-impedance circuit. For proper operation, the ranges VSS Vin 18 V and VSS Vout VDD
are recommended.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.

VSS

tPHL
OUTPUT

tPLH
VOH

90%
50%
10%
tTHL

tTLH

VOL

Figure 5. Switching Time Test Circuit

and Waveforms
PIN ASSIGNMENT
VDD

16

NC

OUTA

15

OUTF

INA

14

INF

OUTB

13

NC

12

OUTE

INB

OUTC

11

INE

INC

10

OUTD

VSS

IND

NC = NO CONNECTION

MC14049UB
4

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 62010
ISSUE V
A
16

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.

B
C

DIM
A
B
C
D
E
F
G
H
K
L
M
N

T
K

SEATING
PLANE

E
F

G
D

16 PL

0.25 (0.010)

16 PL

0.25 (0.010)

T A

T B

INCHES
MIN
MAX
0.750
0.785
0.240
0.295

0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040

MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49

5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01

P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

A
16

S
T

SEATING
PLANE

H
G

16 PL

0.25 (0.010)

MOTOROLA CMOS LOGIC DATA

T A

DIM
A
B
C
D
F
G
H
J
K
L
M
S

INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040

MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01

MC14049UB
5

OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
A

16

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

B
1

8 PL

0.25 (0.010)

X 45 _

C
T

SEATING
PLANE

M
D

16 PL

0.25 (0.010)

T B

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent
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MC14049UB
6

*MC14049UB/D*

MOTOROLA CMOSMC14049UB/D
LOGIC DATA