AC-PLM-1

Data Sheet

AC-PLM-1 Powerline Communication Modem

FEATURES
Robust narrowband FSK modulation Programmable transmission data rate up to 30kbps Programmable communication frequency from 50kHz to 500kHz Complete Media Access Control (MAC) logic CSMA/CD type collision detection and resolution Programmable automatic preamble generation Programmable automatic packet-priority management with four levels Error detection (CRC 16) High-efficiency Forward Error Correction (FEC) Parallel and SPI interfaces Protocol neutrality RoHS compliant

OVERVIEW
The AC-PLM-1 (PLM-1) is a digital modem implementing a half-duplex transmitter/receiver for powerline communications (PLC). Designed as an ASIC, the device is a very efficient solution for cost sensitive, medium data rate applications. The PLM-1 uses a narrowband FSK (Frequency-Shift Keying) modulation technique. The information is encoded by shifting the frequency of the carrier signal between two discrete values in a very narrow range. By adding a complete set of advanced processing functions to this simple form of modulation, PLM-1 technology offers superior performance in powerline communication. Highly selective filtering and efficient error detection/error correction algorithms make reliable communication in very noisy electrical environments possible. Programmable baud rate and carrier frequency provide flexibility to the user and allow sharing the same powerline medium with other systems and technologies. Protocol-neutral technology allows transporting multiple protocols within one powerline network and enables applications to use more than one protocol.

APPLICATIONS
Thanks to its low cost and high performance, the PLM-1 modem offers communication solutions for residential, commercial, industrial and public utilities automation applications. Building and Home Automation:

Lighting Solar Panels Thermostats/HVAC Security

Utilities and Public Services: Automatic Meter Reading (AMR) Demand Response Load Shedding Remote Diagnostic Street/Tunnel Lighting Traffic Lights

Ariane Controls 2145 Chemin Sainte-Foy, suite 22 Qubec City, Qubec G1V 1S1 Canada Tel: 1 418 874 1919 Fax: 1 418 872 4348 www.arianecontrols.com sales@arianecontrols.com

AC-PLM-1
RECOMMENDED OPERATING CONDITIONS
Symbol VDD fosc fc Ta Parameter Supply Voltage Clock Frequency Communication Center Frequency Ambient Temperature Min. 3.0 4.0 50 -40 25 Typ. 3.3 Max. 3.6 20
Figure 1

Data Sheet

Unit V MHz kHz C

500 85

ELECTRICAL CHARACTERISTICS
Symbol VIL VIH VOL VOH IDDi IDDo IO Parameter Input Low-Level Voltage (3V TTL or 5V TTL Tolerant) Input High-Level Voltage (3V TTL or 5V TTL Tolerant) Output Low-Level Voltage Output High-Level Voltage Supply Current in Idle Mode Supply Current in Receive or Transmit Mode Output current 2.4 7.3 16 8.5 16.5 3 2.0 0.4 Min. Typ. Max. 0.8 Unit V V V V mA mA mA

20.0 18.0 16.0 Max fosc (MHz) 14.0 12.0 10.0 8.0 6.0 4.0
50 100 150 200 250 300 350 400 450 500

fc (kHz) Figure 1 Maximum clock frequency is related to the communication frequency

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AC-PLM-1
PACKAGE PINOUT
SCANEN TXOUT RESET

Data Sheet

33

32

31

30

29

28

27

26

25

24

RBURST RSOP REOF REOP RBIT RBITSTR LBUSY XBIT XBITSTR XCMD TESTEN

23

TXING

CFGD

TXEN

RXIN

VDD

VDD

VSS

VSS

34 35 36 37 38 39 40 41 42 43 44 10 11 1 2 3 4 5 6 7 8 9

22 21 20 19 18 17 16 15 14 13 12

RXING CSPOL PORTSEL RSV OE CS STRB/SCLK RD/PCKPOL D4/MISO D3/MOSI D2/PBUSY

VSS

HSK

VSS

D0/PDAV

CFCLK

PINOUT DESCRIPTION
Name CFCLK MCLKO INT
2

Pin 1 2 3

Type Output Output Output / High-Z Output / High-Z

Description Reference frequency (fref) clock. Master clock output. Its frequency is fosc. This pin outputs an image of MCLKI. Interrupt. This pin can be configured to be active-low or active-high. Handshake. During a host parallel READ operation, HSK is set High to indicate that data is available on pins D0-D4. During a host WRITE operation, HSK is set High to indicate that the PLM-1 has sampled data on pins D[4:0]. HSK is in a high impedance state when CS is deactivated. 3.3V power- supply terminals. Ground terminals. Master clock input (fosc). This pin must be driven by an external electronic oscillator or microcontroller. Do not connect a crystal to this pin. Parallel port: Data I/O 0 / Data Available. During a READ operation, while STRB/SCLK is Low, this pin also indicates that data is available on the parallel port. SPI port: Data Available. PDAV is active high.

HSK

VDD VSS MCLKI D0/PDAV

1,2

5, 8, 27, 28 6, 9, 30, 31 7 10

Supply Supply Input Input / Output

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D1/LBUSY

MCLKI

VDD

MCLKO

VDD

INT

AC-PLM-1
Name D1/LBUSY
1,2

Data Sheet
Pin 11 Type Input / Output Input / Output Input / Output Input / Output / High-Z Input Description Parallel port: Data I/O 1 / Line busy. During a READ operation, while STRB/SCLK is Low, this pin also indicates that the line is busy. SPI port: Line Busy. LBUSY is active high. Parallel port: Data I/O 2 / Port Busy. During a READ operation, while STRB/SCLK is Low, this pin also indicates that the parallel port is busy. SPI port: Port Busy. PBUSY is active high. Parallel port: Data I/O 3. SPI port: MOSI - Master Output Slave Input (serial data input of PLM-1). Parallel port: Data I/O 4. SPI port: MISO - Master Input Slave Output (serial data output of PLM-1). MISO provides a high impedance state when CS is deactivated. Parallel port: Read/Write control signal. When driven High, RD indicates a read access from the PLM-1. When driven Low, RD indicates a write access to the PLM-1. SPI port: Clock Polarity. This pin configures how the PLM-1 samples and setup the data on the MOSI and MISO lines respectively, as well as specifying the default level of the clock when the SPI port is idle. Parallel port: READ or WRITE strobe signal. SPI port: Serial Clock. The maximum frequency of SCLK is fosc/4. Chip-Select for parallel and SPI ports. This pin can be configured to be active low or active high. Output Enable. This pin is asserted High when using the parallel port, the CS pin is active and the RD line is High. In normal operation, this signal is not needed and it can be left unconnected. This signal can be used to control external tristate buffers for the data lines D0-D4, e.g. when using the parallel port of a PC to directly interface to the PLM-1. Reserved (leave unconnected, do not connect to power or ground) Communication port type selection. High to select the parallel port. Low to select the SPI port. Chip-Select Polarity. When this pin is High, CS is active high. When it is Low, CS is active low. Receiving. This pin is asserted Low when the PLM-1 is receiving a packet. This pin can drive a LED directly. Transmitting. This pin is asserted Low when the PLM-1 is transmitting a packet. This pin can drive a LED directly. Receiver Input. Transmitter Output. Transmitter Output Enable. This pin is active when the PLM-1 is transmitting. It can be used to put the external power amplifier into a lowpower mode when the PLM-1 is not transmitting. Its polarity can be configured through the TXENPOL configuration parameter. Logic Reset input. Asserting this terminal Low resets the internal logic. Configuration Done. The PLM-1 asserts this pin High when it has successfully received and verified the CRC of its configuration data. This pin can drive a LED directly.

D2/PBUSY

1,2

12

D3/MOSI D4/MISO

1,2

13 14

1,2

RD/PCKPOL

1,2

15

STRB/SCLK CS OE
1,2

1,2

16 17 18

Input Input Output

RSV

2 1,2

19 20 21 22 23 24
2

Output Input Input Output Output Input Output Output

PORTSEL CSPOL
1,2

RXING TXING
RXIN
2

TXOUT TXEN
2

25 26

RESET
CFGD

29 32

Input Output

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AC-PLM-1
Name SCANEN RBURST RSOP REOF REOP RBIT
4 4 4 4 4 3

Data Sheet
Pin 33 34 35 36 37 38 39 40 41 Type Input Output Output Output Output Output Output Output Output Output Output Input Description Test Control input (for Ariane Controls internal use only). In normal operation, this pin must be tied to ground. Positive pulse when a preamble burst is detected. Goes high when a Start of Packet symbol is received. Goes high when a End of Field symbol is received. Goes high when a End of Packet symbol is received. Received bit. Received bit strobe. Pulse indicating moments when RBIT is sampled. High when the communication channel is busy. Bit transmitted. Only valid when TXEN is active. Indicates the moment when the transmitted bit changes. High when the modem is transmitting and the preamble is over. Enables pins 34 to 43. Active high.

RBITSTR LBUSY XBIT

4 4

XBITSTR XCMD
4

42 43

TESTEN

44

Notes: 1. 2. 3. 4. Pin with internal 50k pull-up resistor. 5V tolerant pin. Pin with internal 50k pull-down resistor. Pin only active if TESTEN is high.

PLM-1-BASED POWERLINE TRANSCEIVER

Figure 2 Block diagram of PLM-1-based powerline transceiver

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Line Driver

Host Interface

Conv

AC-PLM-1
FUNCTIONAL DESCRIPTION
The PLM-1 modem can be used to transport data over any AC, DC or unpowered line. The external circuitry can be adapted to meet the characteristics and requirements of various applications, e.g. line conditions, applicable regulations, node size and cost. Figure 2 presents the block diagram of a typical PLM-1based transceiver. The main external components required to complete the modem functionality are: Host: CPU that implements the upper layers of the communication protocol and application specific functions. Typically it is a microcontroller (MCU). Oscillator (Osc): provides the operating clock signal. Analog Front-End: performs signal conditioning and coupling with the communication lines. Power supply: provides suitable DC power to all components.

Data Sheet
Configuration
PLM-1 offers great flexibility when it comes to communication frequencies, data rate, MAC and hardware interfacing. The key to this flexibility lies in the 38-nibble configuration string that the Host must send to the PLM-1 after power-up. The Ariane Controls Configuration Tool software provides an easy way to compute the configuration parameters based on the required communication frequency and data rate.

Packet Format
The PLM-1 can use any protocol to transmit information. However, PLM-1 packets must comply with a standard header that can be added to the protocol frame, and must end by an End of Packet nibble. Also, the maximum packet size is limited to 63 bytes.

Analog Front-End
The Analog Front-End (AFE) is the interface between the PLM-1 modem and the communication channel. It is composed of three main sections: receiving circuit (Rx), transmitting circuit (Tx) and coupling circuit. In reception, the communication signal is processed by the Rx filter that eliminates the out-of-band frequencies. Then, the sinusoidal signal is converted to a 3.3V square wave that is applied to the modem RXIN pin. In transmission, the Tx filter converts the PLM-1 square-wave output (TXOUT) into a sinusoidal signal; a narrowband band-pass response is used to select the communication frequency and attenuate additional components and related harmonics. The line driver provides voltage and current signal amplification. It is activated during transmission by the PLM-1 enable signal (TXEN). The coupling circuit connects the AFE to the communication channel. It acts as a filter that passes the communication signals, while attenuating out-ofband frequencies.

Internal Operation
Implementing the PHY and MAC layers of the OSI model, the PLM-1 modem is based on a patented technique for modulating the binary information on a frequency shift keying (FSK) carrier in a very narrow band. The digital data is encoded in a binary signal whose frequency is shifted between two discrete values: F0 for logic 0 and F1 for logic 1. The average value of the two frequencies is defined as the center frequency Fc. The internal structure of the PLM-1 modem consists of four main blocks, as shown in Figure 2. The Clock Generator is used internally to set timings for communication frequencies. An external clock signal (MCLKI) that ranges from 4MHz to 20MHz is required to provide the operating frequency Fosc. The Demodulator, or Receiver, samples the input signal on the RXIN pin, decodes it and feeds it to the Host Interface. The Modulator, or Transmitter, receives data from the Host Interface and modulates them on the output signal pin (TXOUT). The signal TXEN is used to enable the external amplifier during transmission.

DEVELOPMENT TOOLS
To help users of PLM-1 modem to easily integrate the chip into their project, Ariane Controls offers a full range of development tools: Evaluation boards and easy-to-use software allow for evaluating and developing PLM-1-based applications. PLM-1 User Manual provides complete design and application information. Firmware libraries and sample codes are accessible for easy start-up. PCB footprint libraries for various design software. Technical support and design review.

Interfacing with a CPU

PLM-1 provides two types of communication with the external Host: serial (SPI) and parallel. Which one to use depends on the circuit design, as well as the capabilities of the CPU. In both cases, a master-slave design is used, in which the PLM-1 acts as a slave. The PORTSEL pin enables the selection of the interface. The PLM-1 offers the following interfacing features: Serial and parallel mode Programmable clock polarity for serial mode Programmable Chip Select (CS) polarity Port and line status monitoring

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AC-PLM-1
MECHANICAL PACKAGE DATA

Data Sheet

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AC-PLM-1 ORDERING INFORMATION

Product number: AC-PLM-1 Sales: sales@arianecontrols.com Technical support: support@arianecontrols.com Tel: +1 418-874-1919 Fax: +1 418-872-4348 Headquarters: 2145 Chemin Sainte-Foy, suite 22 Quebec City, Quebec G1V 1S1 CANADA

Data Sheet

For further information on Ariane Controls technology and products, please visit our web site: www.arianecontrols.com

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