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Logic Design Project

By:
Terry Owen Instructor, Electronics and Engineering Portland Community College Portland, OR

Abstract:
This project is used in the first term of the logic design course for electrical and computer engineering students. It is taken in the middle of their nd year. !ariations of the project ha"e #een done for a#out $% years at PCC. The student must complete the project and it must work correctly to pass the course. & PC is used to confirm correct operation. & program has #een written to output the '( codes and to check the circuit)s response. It is written in *%*' assem#ler and uses the parallel printer port. The character codes are changed each year.

Equipment:
PC +, ,+, (+, and *+input nand gates ea. -(., counters

/ogic &naly0er such as &gilent $'*,& or &gilent $'.,& 1pecial Test Program for PC

Problem Description:
In digital computers, letters of the alpha#et and the ten decimal numerals can #e coded in the form of uni2ue com#inations of fi"e or si3 #its. One of these codes is the '+#it 4le3owriter code, which is used for some punched paper tape. This code is gi"en #elow in terms of 5E6 e2ui"alents.

7our jo# is to design a circuit which detects whether a code on si3 data lines represents a num#er, a letter, or an illegal code. The circuit produces three output signals, &, 8, and E, as shown #elow.

Outputs:
The A output is high when an alpha#etic character is sensed, low when a numeric character is sensed, and either high or low for any other character. The N output is low for an alpha#etic character, high for a numeric character, and high or low for any other character. The E output is low for #oth alpha#etic and numeric characters, and high for any other characters.

Examples:
9hen a code :e3ample; input pattern for the letter < is $C 5E6= assigned to an alpha#etic character is sensed, the & output is high, the 8 output is low, and the E output is low. 9hen the input pattern is neither alpha#etic or numeric : % 5E6=, the E output is high, and & and 8 outputs can #e either high or low.

Design Constraints:
The circuits which implement the three outputs can use only , ,, (, and *+input 8&8> gates and in"erters. & ma3imum of ' IC packages. & #onus of ? points will #e gi"en if you use ? packages and $? points if you use ( packages.

Design Log:
&1 7O@ 9ORA you are to keep a log which discusses the steps you take and the results of each. & part of the grade will depend on how thoroughly and clearly you document your work. This log B@1T #e done as you do your design and not #e recreated after the design is completed. It is to show all your work, #oth correct and incorrect. >O 8OT @1E 1CR&TC5 P&PER &T &87 TIBE. The /OC is to use one or more of the </@E E3amination <ooks :*.,-? #y '.-? inches= a"aila#le in the PCC #ookstore. 8o other type of log#ook is accepta#le. Bore than one may #e needed. If you need to include a computer output, then fold and fasten it to the log #ook. 7ou are to time and date each entry into the #ook. The final report must #e supported #y the entries in the log#ook. The first page of the /OC is to contain a ta#le used to track your progress. It is to ha"e the following columns;

9ork categories; >+design, C+construction, ><+de#ugDtest &t the end, make a summary of the time spent in each phase and the total time.

Procedure:
$. Bake a truth ta#le for the design. . Bake three '+"aria#le Aarnaugh maps and get the minimal 1OP e3pression for each output. ,. 1tudy the symmetry of the outputs and decide how to #est implement the circuits within the design constraints stated pre"iously. This will pro#a#ly not #e the 1OP form you found from the maps #ut a "ariant of that form.

(. >raw a schematic diagram for the design. 7ou may either hand draw using a logic template or use a schematic capture program such as P1PICE. ?. <uild the circuit and test its operation. @se two -(., counters to gi"e the input signals and the logic analy0er to make the measurements. '. &fter you are sure the circuit works correctly, and it is your #est design using the minimal num#er of IC packages, ha"e the instructor test the circuit at the PC #ased test station. It is e3pected that e"ery circuit will pass the computer #ased test on the first attempt. 4i"e points will #e su#tracted for each incorrect try.

eport:
$. 7our log#ook:s= which show all your design steps and thinking process. &gain these are to #e done as you proceed with the project, not at the end of the project. . & fully la#eled and correctly drawn schematic diagram of your circuit as it was tested. The instructor will sign+off the schematic when the circuit passes the computer #ased testing. ,. & one to two page report done on a word processor. The report is to summari0e the pro#lem #eing sol"ed, the major design decisions you made in sol"ing the pro#lem, and the pro#lems you encountered and how they were resol"ed in completing the design. It is e3pected that the report will #e of a professional 2uality. (. The signed intellectual property statement; I do here#y affirm that I did the work on this circuit #y myself. 1igned EEEEEEEEEEEEEEEEEEEEE >atedEEEEEEEEEEEEEEEEEEEE

Computer !est "nter#ace:


& PC will #e connected to your circuit for the final test. The computer will supply the input signals to your circuit and will read the three outputs. The outputs will #e compared to a look+up ta#le to determine your circuit functions correctly. To make the test work correctly you are to remo"e the two -(., counters from your #oard so their outputs do not interfere with the computer test. The wiring for the counters should #e left in place in case you need to retest your circuit using the logic analy0er. & place on your circuit #oard needs to #e wired with wires which will supply your circuit with the test signals, and make your circuit outputs a"aila#le to the computer. & plug which looks like a $' pin IC will connect your #oard to the computer. The wiring of the interface socket on your #oard is shown #elow. It is essential this diagram #e followed e3actly. @+F are the input signals. 8ote; F is the /1< :Ga of the first counter= $+$' are the pin num#ers of the interface socke

$rading:
/og#ook ,%H 4ormal report and schematic ,%H >esign I operation (%H

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