Vinti vv2236 Homework 1.

a Pseudo-code for Go-Back-N when messages and acknowledgements are numbered on field of real numbers: W is the window size Transmitter: Begin Expected_ID = 0 ID = 0 Frame = First packet to send While (true){ //Infinite loop Switch(event){ case frame_ready: //next message ready to be transmitted Msg = ID,Frame if (ID<Expected_ID+W) Xmit Msg Msg= Msg+1 if (timeout==set) frame_ready=true // send next frame else set Timeout case Ack_Received: if (Rcvd_ID>Expected_ID) Expected_ID= Rcvd_ID Set Timeout if(Expected_ID=ID) Reset Timeout case Timeout: // this means that acknowledgement was not received so reset packets ID = ID_expected frame_ready = true } Receiver: Begin Expected_ID=0 Repeat Wait(event) // wait till an error message is received If (Rcvd_ID<= Expected_ID) If (Rcvd_ID== Expected_ID) Expected_ID=Expected_ID+1; Send Expected_ID ack to network end Until doomsday end

1.b Pseudo-code for Go-Back-N when messages and acknowledgements are numbered on N+1 W is the window size N is the frame size Transmitter: Begin Expected_ID = 0 ID = 0 Frame = First packet to send While (true){ //Infinite loop Switch(event){ case frame_ready: //next message ready to be transmitted Msg = ID,Frame if (ID<Expected_ID+W) Xmit Msg Msg= (Msg+1)modN if (timeout==set) frame_ready=true // send next frame else set Timeout case Ack_Received: if (Rcvd_ID>Expected_ID) Expected_ID= Rcvd_ID Set Timeout if(Expected_ID=ID) Reset Timeout case Timeout: // this means that acknowledgement was not received so reset packets ID = ID_expected frame_ready = true

Receiver: Begin Expected_ID=0 Repeat Wait(event) // wait till an error message is received If (Rcvd_ID<= Expected_ID) If (Rcvd_ID== Expected_ID) Expected_ID=(Expected_ID+1)modN; Send Expected_ID ack to network end Until doomsday end

2. Pseudo-code for Selective-Repeat protocol W is the window size = Transmitter: Begin Expected_ID = 0 ID = 0 Start_ID=0 Frame = First packet to send While (true){ //Infinite loop Switch(event){ case frame_ready: //next message ready to be transmitted if (ID-Start_ID<W) Msg = ID,Frame Xmit Msg ID= ID+1 Start Timer(ID) case Nak Reveived(t): // this means that Nak for msg t received Reset Timer(t) Xmit Msg(t) // retransmit msg with ID = t case Ack_Received: if (Start_ID<Rcvd_ID <ID) while (Start_ID< Rcvd_ID){ Stop Timer(Start_ID) Start_ID=Start_ID+1 } case Timeout(t): // this means that acknowledgement for msg t was not received Reset Timer(t) Xmit Msg(t) // retransmit msg with ID = t

Receiver: Begin Expected_ID=0 Start_ID=0 Repeat Wait(event) // wait till an error message is received If (Start_ID= Rcvd_ID) Xmit Ack(Start_ID) Start_ID= Start_ID+1 If (Start_ID<= Rcvd_ID <= Start_ID+W){ Xmit Ack(Rcvd_ID) // transmit ack for the received ID For (ID=Start_ID; ID<Rcvd_ID) Xmit Nak(ID) // transmit NAK for packets not received before Rcvd_ID } end Until doomsday End

Summary: Testing Communication Protocol Advancement in the telecommunication industry has resulted in the need of better and more advanced protocol testing methodologies. This chapter focuses on these aspects. It discusses different protocol models and specification, fundamental techniques of testing simple systems and how to implement them in testing communication protocol, the OSI-RM structure and then different formal tools used for protocol specification and verification. After introduction, the author introduces conformance testing in which a system is considered as a black box i.e. no information is available about its internal components, and it is tested based on the expected behavior of the system. This concept has been explained through the example of a calculator. Hence for conformance testing, test cases are required. In the next section, the research papers that have been reviewed to write this chapter have been listed like the OSI reference model introduces the OSI protocol and the Finite Descriptions of Communications Protocols, which explains use of FSM to model communication protocol. The concepts have further been explained with the help of flow diagrams and block diagrams. The 4th section then talks about Finite State Machines exclusively. An elaborate methodology of how to make finite state machines has been given. FSMs are basically automaton having finite number of different states that a system can exist in at a given time and can transition from one state to another depending upon the value of inputs. A change in input causes a state transition and generation of an output based on this transition. A formal definition of FSMs has been given in this chapter through mathematical representation. The sub sections explain how are state transition tables made to represent an FSM. Different Formal Description techniques like SDL, LOTOS and Estelle have also been described with examples. At the end of the chapter, the author sums up all the sections and topics that have been covered. The author also points out the use of FSMs and EFSMs for formal specification and verification of communication protocols is a topic that is an active research area right now and a lot of literature is available. Also, the challenges in using FDTs have been pointed out. One of the major challenges is to prove that the system model developed using an FDT satisfies safety and liveliness properties and is error and deadlock free. This is called specification verification. Problems like state explosion and use of spontaneous transitions make protocols very difficult to test. This chapter is a good and concise read for getting a preliminary idea of formal methods in communication systems. Further, interested readers can use the reference to learn more about the subsections.

Summary: Section 4. Modeling communication protocols The 4th section then talks about Finite State Machines exclusively. An elaborate methodology of how to make finite state machines has been given. FSMs are basically automaton having finite number of different states that a system can exist in at a given time and can transition from one state to another depending upon the value of inputs. A change in input causes a state transition and generation of an output based on this transition. A formal definition of FSMs has been given in this section through mathematical representation. The state transitions depend on a certain set of permissible inputs I which generate outputs from a set of permissible outputs O. Null in not a permitted input. Inputs are generally generated by external sources or stimuli. A fully specified FSM has an output for every possible input combination. Partially specified FSMs are those in which some inputs are not allowed in some states. Deterministic FSMs have outputs and next state as a function of the input and current state. The author next defines an FSM in tuple form <SIOT>. S is the finite set of states. I and O are permissible inputs and outputs sets and T is a set of functions of the transition from current to next state. For the Extended FSM the tuples are <SIOVPBT> where V is a set of variables, P is a set of parameters and B is a set of Boolean expression. Hence, EFMS are dependent on variables, parameters and Boolean expressions as well, along with inputs and current states. All these tuples have been formally defined in this section. The next section talks about representing FSMs. State transition tables are used to represent an FSM. The columns contain current state, input and next state fields and the rows contain the set of finite states possible. In case of partially specified FSMs, some of the table entries are vacant. The first row starts with the initial state or the power on state. Another tool used to represent FSMs is a directed graph G=(V,E). V is the vertices of the graph that correspond to the states and E is the edge that represents transition from one vertex/state to other. Inputs and outputs are marked on these edges. These representations have been explained with the help of an example of a PhoneDTE. The state transition table as well as the directed graph for this has been given. An important feature of directed graphs is that their cant be two edges from a given vertex for the same input sets. If such a case exists, the FSM will be non-deterministic. Directed graphs have been discussed in detail in this subsection. Deadlocks happen when system waits in a state forever for an input which will never be sent. The author next discusses the paper Finite State Description of Communication Protocols and its highlights. The paper presents the concept of layered communication design in OSI-RM and protocol verification. The next sub section then covers different Formal Description techniques available. The first FDT given is Specification and Description Language (SDL) based on EFSMs. SDL is a high-level general-purpose description language and its main area of application is telecommunication systems and protocols. SDL is based on Extended Finite State Machines and uses a graphical syntax. It has a modular approach and a clear distinction between structural and behavioral aspects of a system, which facilitates modeling of layered architectures in communication protocols in this technique. Estelle is another FDT, which is based on Extended FSM theory and uses Pascal for data manipulation. LOTOS (Language of Temporal Ordering Specifications) is based on process algebra, which is used to model distributed systems and concurrent processes. Its syntax has temporal and stochastic features.

While using these FDTs, protocol designers have to make various tradeoff between precisely specified and over specified protocols. A precise specification is easier to test but it limits the features that the designer can add to the protocol. The PhoneDTE example has been implemented all the three FDTs discussed. This section gives a good overview of what are FSMs and EFSMs and how they can be used to model communication protocols with examples. Therefore it provides a good understanding of this topic.