Digital Electronics - Written Exam

July 12th 2011

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The answers to the questions must be written in permanent ink (no pencil); Put your name on every separate sheet of paper and number them; You can reply to the questions in the order you want but before giving an answer clearly indicate to which exercise you are referring to; Attach this text to your written exam filling the last name and first name fields.

Exercise 1
The following picture shows a transmission line with a generator v(t) = 3.3 u(t) and a resistance Rg = 100 W. The line has a length L=15cm, propagation speed v = c/2 and a characteristic impedance of 50 W. Two inverters with infinite input resistance are placed at one half (point A) and at the end point B) of the line. Their VIH=2.8 V.

Determine at which time the input of each inverter in understood as login 1.

Exercise 2

A microprocessor with a word width of 32 bit is connected to a 512 Mbytes main memory through a 2 way set associative cache with 1024 lines (512 sets) and a block size of 16 bytes. Determine the minimum address space of the processor, mapping algorithm, the tag size and the total size of the cache (in bytes). If the processor executes cyclically the following program : Address 0000 0004 0008 000C 0010 0014 . 4000 4004 4008 400C Instruction INSTR #1 INSTR #2 INSTR #3 CALL 4000 // Beginning of the main loop

INSTR #4 GO TO 0000 . INSTR #5 INSTR #6 INSTR #7 RETURN // End of the main loop

And a cache hit has a cost of 3 clock cycles and a cache miss has a cost of 15 cycles determine: The number of cycles which are required to fetch the instructions from the memory o o The first time the loop is executed At all the following executions of the loop

The content of the cache after the first execution of the loop. Assume that the cache lines of the same set are contiguous, that is set 0 comprises lines 0 and 1, set 1 lines 2 and 3 and so on

Exercise 3
Write initialization code and interrupt service routines that implement a programmable frequency generator using a processor connected with a 10key keyboard and a loudspeaker driven by a square wave. You can use a NIOS II processor, driven by a 100MHz clock, connected with: A 16bit PIO port, whose base address is represented by the PIO0_BASE macro, that will both read the 4bit input key code (an integer between 0 and 9) and write the singlebit output waveform. You can use bits 30 for the key input and bit 4 for the waveform output. The set of control and data registers (to be used directly or via the Altera IO macros) is:

A timer peripheral, whose base address is represented by the TIMER0_BASE macro, which must be used to generate twice the required frequency (since one call of its ISR will raise the waveform output, and the other will lower it). Its control and data registers are:

The period of the waveform to be generated (again, considering that the interrupt must be generated every half period) must be x msec, where x is the value read from the keyboard, and a value of 0 means that the output must not be updated at all. This means that if the pressed key is 5, then the period of the output waveform must be 5 msec. If the pressed key is 0, then the output must not change until a key different from 0 is pressed again. Write: 1. The initialization code of the PIO and Timer peripherals that will become part of the main program and that initializes: a. the PIO to have 4 inputs (bits 30) (handled in interrupt) and 1 output (bit 4), b. the timer to periodically (with an appropriate period) interrupt the CPU.

2. The Timer interrupt service routine that toggles the PIO output bit. 3. The PIO interrupt service routine that changes the timer period according to the key value (or stops the timer if the key value is 0). You can either use the actual register offsets, from the tables above, or use the macros. For the timer, they have names like: IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data), IORD_ALTERA_AVALON_TIMER_SNAPH(base), and so on. Please note that comments are very important to explain the intent of your code. Syntactic correctness is less important (even though the code must be understandable). Macro names are not important at all, but they should indicate clearly to which peripheral register you are referring, and whether you are reading them (the macro has 1 argument, namely the base address of the peripheral, and returns the value of the register) or writing them (the macro has 2 arguments, namely the base address and the value to be written).

Exercise 4
Please indicate with a cross which ones among the following ones are typical characteristics that distinguish Digital Signal Processors from generalpurpose CPUs (i.e. are very often present in DSPs and very seldom present in CPUs): Multiple register files with different functionalities Bitlevel operations (shifts, ors, ands, ) Cache management instructions (preload, flush, ) Dedicated combinational hardware multiplyandaccumulate unit(s) The ability to execute multiple instructions in a clock cycle A pipelined execution Concurrent access to several data memories Dedicated pointer register incrementers/decrementers A fast dedicated code RAM (code scratchpad) A set of peripherals such as timers, PIOs, serial ports, etc.

Exercise 5
Please check the schedulability with the Utilization Theorem and perform online preemptive static priority scheduling with the Rate Monotonic (RMS) algorithm for the following set of tasks: Task Period = Deadline WCET T1 3 1 T2 2 1 T3 6 1 Simulate the schedule for the first hyperperiod (least common multiple of the task periods), clearly indicating the first deadline violation (if any). If there is a deadline violation AND the task set can be scheduled with Earliest Deadline First (EDF), according to the Utilization Theorem, then simulate also a hyperperiod using EDF for online preemptive dynamic priority scheduling.