Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals

Xiaoping Deng, 2Mao Tian, *3Yijun Luo, 4Jin Li School of electronic information, Wuhan University 430072, China, E-mail: dengxp_whu@hotmail.com 2, School of electronic information, Wuhan University 430072, China, E-mail: mtn@whu.edu.cn *3, Corresponding Author School of electronic information, Wuhan University 430072, China, E-mail: lyj@whu.edu.cn 4, School of electronic information, Wuhan University 430072, China, E-mail: lijin2425@163.com
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Abstract
In this paper, an optimized programmable demodulation scheme suitable for M-PSK/16QAM signals is proposed. The scheme adopts the conception of component reuse by exploring the demodulation structures of M-PSK and 16QAM respectively. The carrier phase recovery circuit uses the reduced complexity Costas loop. The symbol timing synchronization circuit adopts Gardner loop with offset cancellation. The optimized scheme is implemented in Field Programmable Gate Array (FPGA). The result of the experiment shows that this scheme can realize demodulation for M-PSK and 16QAM signals in real-time with less computation and FPGA resources. And this scheme has good flexibility and adaptability.

Keywords: Demodulation, Synchronization, FPGA 1. Introduction

Flexibility and adaptability are becoming the most important features for modern telecommunication systems, owing to the rapid evolution of different standards and protocols in the world of communications. Demodulation is one of the key technologies in modern telecommunication systems. Therefore, in the last few years, the design of efficient demodulation architectures that able to support different standards, multiple radio protocols has received a great deal of attention [1]. Software defined radio (SDR), proposed decades ago, provides an ideal solution for communication systems that require flexibility and adaptability. It aims to implement the whole communication and digital signal processing system after the antenna picks up the signal [2]. Since FPGA has undergone revolutionary changes in gate densities, clock speeds and integrated functions, the state-of-the-art FPGAs are now moving us closer to the true objectives of the SDR. As the two most important issues of demodulation, carrier recovery and symbol timing synchronization have been studied in theory in a vast literature [3-5] . On the other hand, many new structures have been proposed to solve the problems. Some researchers focus on carrier recovery [6,7].While some others focus on symbol timing synchronization[8-11]. In this paper, we consider both and propose an optimized structure suitable for M-PSK and 16QAM signals. And then we carry it out in FPGA device with less computation and FPGA resources. The rest of this paper is organized as follows: Section 2 reviews the M-PSK and 16QAM signals. Section 3 discusses general architecture of digital demodulator. Section 4 provides the optimized demodulation structure for M-PSK/16QAM signals. Section 5 covers the hardware design and implementation results. Section 6 concludes the paper.

International Journal of Digital Content Technology and its Applications(JDCTA) Volume6,Number15,August 2012 doi:10.4156/jdcta.vol6.issue15.12

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

2. The M-PSK and 16QAM Signals

M-ary Phase Shift Keying (M-PSK) and Quadrature Amplitude Modulation (QAM) are two modulation schemes widely used in wireless applications such as satellite communications and mobile communications. The QPSK modulation can be considered as the combination of two orthogonal BPSK signals. For this reason it requires half the channel bandwidth for the same bit rate and provides the same error performances as the BPSK for a given transmitted energy per bit. M-PSK signal set is defined as

si (t ) = A cos(2p f c t + qi ), 0 t
where

T , i = 1, 2,..., M

(1)

qi = (2i - 1)p / M
The carrier frequency is chosen as an integer multiple of the symbol rate, therefore in any symbol interval, the signal initial phase is also one of the M phases. Usually M is chosen as a power of 2(i.e., M = 2 , n = log 2 M ). Therefore, the binary data stream is divided into n -tuples.
n

Each of them is represented by a symbol with a particular initial phase. Binary Phase Shift Keying (BPSK) and Quadrature Phase Shift Keying (QPSK) are special cases of M-PSK with M = 2 and 4, respectively [12]. Fig. 1 shows the constellations of BPSK, QPSK and 8PSK. QAM is a class of non-constant envelope schemes that can achieve higher bandwidth efficiency than M-PSK with the same average signal power. In this scheme, both amplitude and phase convey the information. Similar to M-PSK, QAM signal can be expressed as a linear combination of two orthonormal functions, the constellation of 16QAM is plotted in fig. 1.

2 (t )

2 (t )

2 (t )

2 (t )

1 (t )

(t )

(t )

1 (t )

Figure 1. Constellations for BPSK, QPSK, 8PSK and 16QAM

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

3. General Architecture of Digital Demodulator

I
) cos(2fc t

) sin(2 f c t

Q
Figure 2. Block diagram of basic M-PSK/QAM digital demodulator

Fig. 2 illustrates the block diagram of basic M-PSK/QAM digital demodulator. As shown, two correlators are required to correlate the received signal with the two quadrature carrier signals cos(2p f t + f ) and - sin(2p f t + f ) , where f is the carrier phase estimate. The carrier
c c

recovery block receives baseband signals and generates the two quadrature local carrier signals. The low-pass filters are used to eliminate the double-frequency terms following the correlators. The matched filters are used to detect the transmitted pulses in the noisy received signal. The symbol synchronizer controls the sampler decision block and decides the best time of decision. In the case of M-PSK scheme, the block of sampler decision is a phase detector, which compares the received signal phases with the possible transmitted signal phases. While in the case of QAM scheme, the block of sampler decision computes the Euclidean distance between the received noise-corrupted signal point and the M possible transmitted points, and selects the signal closest to the received point[13]. The parallel to serial converter converts the parallel symbols to a bit stream.

4. Optimization of General Structure for M-PSK/16QAM Signals

Amongst the function blocks of general architecture of digital demodulator, carrier recovery and symbol synchronizer are the most important and complex two parts[14]. The optimization of general structure for M-PSK/16QAM signals in this paper focuses on the optimization of them. The scheme adopts the conception of component reuse by exploring the demodulation structures of M-PSK and 16QAM respectively. The carrier phase recovery circuit uses the reduced complexity Costas loop. The symbol timing synchronization circuit adopts Gardner loop with offset cancellation.

4.1 Carrier recovery

There are many ways to implement carrier recovery in digital communication system. The essential of most carrier recovery methods is the phase-locked loop (PLL). In digital demodulator, the carrier recovery can be implemented with a digital phase-locked loop (DPLL) as shown in fig. 3.

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

I ( n)

Kl
z
1

) cos( 0n
Q(n)

Kp

) sin( 0n

Figure 3. Digital phase-locked loop for carrier recovery

The generation of the two estimated quadrature carrier signals takes the form of a direct digital synthesizer (DDS) [15]. A 2-order loop filter formed by a scaled digital integrator and a scaled direct path is adopted to reduce the noise level in phase error. The filter coefficient K and K determine the PLL bandwidth and damping factor. The low-pass filter and matched
p l

filter can be implemented in a low-pass filter by cascading the filter coefficients. The structures of those three parts in carrier recovery are general for both M-PSK and 16QAM. Therefore, those three parts can be used in this demodulator without any difference between M-PSK and 16QAM. The phase detector is the most complex part of the DPLL. Note that sin(D q) is monotonic with D q for - p / 2 q ? p / 2 and sin(D q) q when D q is small, so the complexity of the phase detector can be reduced by computing a signal proportional to the sine of the phase

.The reduced complexity phase detector for M-PSK and 16QAM is difference D q = q - q illustrated in fig. 4.
I ( n)

( n) I

Q (n)

(n) Q

Figure 4. Structure of phase detector for M-PSK/16QAM

The phase error is calculated by comparing the phase difference between the received ( n) . The four constellation ( n) + jQ signal I ( n) + jQ ( n) and the closest constellation point I points of QPSK signal are located in the center of the four quadrants so that the nearest constellation point corresponding to the received signal can be computed by taking the sign of

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

the in-phase and quadrature amplitudes of the signals output the low-pass filters. The sine of the phase difference is expressed as
sin(D q) = ( n) I (n) ( n )Q ( n ) - Q I 2 ( n) I 2 ( n) + Q 2 (n) 2 ( n) + Q I (2)

which shows that the difference of the cross products is proportional to the sine of the phase difference. Therefore the difference of the cross products can represent the phase error. In order to use the difference of the cross products given by Eq.(2) when 16QAM signal is received, an amplitude detector is added into the structure of phase detector. This amplitude detector monitors the in-phase and quadrature amplitudes of the signals output the low-pass filters. The output of amplitude detector decides whether to pass the phase error on to the following loop filter or not. Note that the constellation points of 16QAM can be classified as three types according to the distance between them and the origin. The function of the amplitude detector can be described as

1, I ( n) + Q ( n) > Thr Gain ( I ( n ); Q ( n )) = 0, otherwise

2 2

(3)

where Thr is the threshold classifying the constellation points with the largest distance and those falling into the other two types.

4.2 Symbol timing synchronization

Symbol timing of M-PSK/16QAM demodulator must be synchronized to the symbols of the incoming data signal. The symbol timing synchronization circuit usually takes the form of a PLL. The symbol timing synchronization circuit we adopt is illustrated in fig. 5. It contains a data filter, a Timing Error Detector (TED), a loop filter and an interpolator.

x ( m)

y (k )

Figure 5. Symbol synchronizer structure for M-PSK/16QAM

The interpolator implements resample which changes x ( m) into y ( k ) . x ( m) is the signal sampled by the receiver local clock while y ( k ) is the signal synchronized to the symbol timing of the transmitter [16]. Data filter is a low-pass filter used to smooth the signal output from the interpolator. The structure of the loop filter is the same as the one in carrier recovery part, which is shown in fig. 3. Since the TED suggested by Gardner in [17] has been widely used and of good performance, we adopt the main structure with some improvement making it suitable for 16QAM signals. If a QPSK signal is being processed, the timing error is the amount of the midway point values when transition occurs between symbols. Because when transition occurs without timing error, the values of the midway point should be zero. However in the case of 16QAM, the values of

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

the midway points can be -2,-1, 0, 1, 2 when transition occurs between symbols with no timing error. Thought the average value of the midway points is zero for large amount of symbols, timing jitter can be caused when transitions occur with midway point near -2,-1, 1 and 2. Fig. 6 illustrates the waves of QPSK and 16QAM demodulation.

y (r 1)
y (r 1/ 2)

y (r 1)
y (r 1/ 2) ( y ( r ) y ( r 1)) / 2 y (r )

y (r )
Figure 6. Waves of QPSK and 16QAM demodulation
The average value of y ( r - 1) and y ( r ) is a = ( y ( r - 1) + y (r )) / 2 .When there is no timing error exist, a should be 1. Therefore, we can get the new timing error err = y (r - 1/ 2) - a . The following process with err is the same with the midway point value of QPSK signals.

5. Hardware Implementation and Results

In order to implement the optimized demodulation scheme, a signal sampling and processing board is used. It features the prototype capabilities for wireless communication, includes an analog-to-digital converter that can operate at the conversion rate up to hundreds of MSPS and an ALTERA Stratix II family FPGA device. The top architecture view of FPGA design for the optimized demodulation scheme is shown in fig. 7.
clk0 IF[9..0] reset_n Sy mbolRate[15..0] modulate_mode[1..0]
INPUT VCC INPUT VCC reset_n INPUT VCC INPUT VCC INPUT VCC

f ir_demod_v 90 clk0
NOT

ri[23..8] rq[23..8] ast_source_data[23..0] ast_sink_ready ast_source_v alid ast_source_error[1..0]

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT

i_out[15..0] q_out[15..0] sy mb_ena i_decision q_decision

reset_p

reset_n ena_CARR Di[18..3]

clk reset_n enable ast_sink_data[15..0] ast_sink_v alid

inst15

VCC

GenNewRatio clk0 Sy mbolRate[15..0] modulate_mode[1..0] clk Sy mbRate[15..0] mode[1..0] inst5 Ratio[13..0] ena_CARR ena Ratio[13..0] ena_CARR ena_sy mb

ast_source_ready ast_sink_error[1..0] Interpolator_Gardner_TED_ena clk0 ena_sy mb clk ena i[23..0] clk reset_n enable ast_sink_data[15..0] ast_sink_v alid ast_source_data[23..0] ast_sink_ready ast_source_v alid ast_source_error[1..0] sy m_clock reset_n q[23..0] sy m_clk reset_n remain[15..0] decimal[11..0] time_error[15..0] I_decision Q_decision i_decision q_decision

GND

inst8 f ir_demod_v 90

clk0 reset_n Di[18..0] ena_CARR DQ[18..3]

Dow nConvert
clk0 IF[9..0]

ena_CARR

clk in[9..0] CarrCos[9..0] CarrSin[9..0] ENA

inst9

i[18..0] q[18..0]

Dq[18..0]

VCC

ast_source_ready ast_sink_error[1..0] inst3

GND

inst19 CarrierRecov ery _ena clk0 phase[13..0] err[23..0] LPF[43..0] clk id[23..0] qd[23..0] reset_n ena reset_n ena_CARR Ratio[13..0] modulate_mode[1..0]

estimate_value_ena
clk0

DDS f sin_o[9..0] f cos_o[9..0] data_ready phi_inc_i[13..0] clk reset clken

clk0 reset_p ena_CARR

error[23..0] LPF[43..0]

ri[23..0] rq[23..0] sy mb_ena

decimal[11..0] remain[15..0] sym_clk symb_ena

clk time_error[15..0] reset_n ena

inst14

reset_n ena_sy mb

inst

ratio[13..0] mode[1..0] inst1

Figure 7. Top architecture view of FPGA design

In this architecture view, IF[9..0] is the received signal. DownConvert module, fir_demod_v90 modules, CarrierRecovery_ena module and DDS module compose the carrier

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

recovery loop. While estimate_value_ena module and Interpolator_Gardner_TED_ena module compose symbol timing synchronization circuit. Input pins SymbolRate[15..0] represent the symbol rate received. Input pins modulate_mode[1..0] control the modulation type that need to be processed. Output pins i_out and q_out are the base-band signal I ( n ) and Q ( n ) respectively. While Output pins i_decision and q_decision represent the recovered symbols of demodulator. A signaltap II logic analyzer result for these signals in the case of QPSK is illustrated in fig. 8, which proves that this demodulator can work correctly.

Figure 8. Signaltap II logic analyzer result of demodulator

The proposed demodulator is implemented in FPGA device EP2S180F1020C3. The FPGA resource utilization is shown in table 1.

Table 1. FPGA resource utilization Combinational Dedicated logic Block memory DSP block 9-bit bits elements ALUTs registers 768 9,383,040 143,520 Total FPGA resource 143,520 53 4,605,806 19,597 Utilization before optimization 18,091 45 496,213 9,721 Utilization after optimization 6,728 Resource type
As the main resource types offered by FPGA device, combinational adaptive look-up tables (ALUTs), dedicated logic registers, block memory bits and DSP block 9-bit elements are chosen to evaluate the utilization of FPGA resource. The utilization before optimization represents the total resource utilization when M-PSK and 16QAM signals are processed separately in one FPGA device. As we can see, the utilization of all four types of FPGA resources has reduced obviously compare with that before optimization.

6. Conclusions
In this paper a new highly versatile programmable demodulator for both M-PSK and 16QAM signals is proposed. The carrier phase recovery circuit uses the reduced complexity Costas loop. While the symbol timing synchronization circuit adopts Gardner loop with offset cancellation. Moreover, its implementation in FPGA is carried out. The result shows that this demodulator can demodulate M-PSK and 16QAM signals correctly in real-time with less computation and FPGA resources. And its parameters such as carrier frequency and symbol rate can be reconfigured online. This optimized scheme is promising for the use of M-PSK/16QAM demodulation in Software Defined Radio applications.

7. References
[1] Paolo Zicari, Emanuele Sciagura, Stefania Perri, Pasquale Corsonello, A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals, Microprocessors and Microsystems, vol. 32, pp.437-446, 2008.

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Optimization and Implementation of Programmable Demodulator for M-PSK/16QAM Signals Xiaoping Deng, Mao Tian, Yijun Luo, Jin Li

[2] Anton S. Rodriguez, Michael C. Mensinger Jr., In Soo Ahn, Yufeng Lu, Model-based Softwaredefined Radio (SDR) Design using FPGA, IEEE International Conference on Electro Information Technology, pp.1-6, May 2011. [3] L.E. FRANKS, Carrier and Bit Synchronization in Data CommunicationA Tutorial Review, IEEE Trans. Commun., vol. com-28, no. 8, pp.1107-1121, August 1980. [4] Yair Linn, Robust M-PSK Phase Detectors for Carrier Synchronization PLLs in Coherent Receivers: Theory and Simulations, IEEE Trans. Commun., vol. 57, no. 6, pp. 1794-1805, June 2009. [5] Heinrich Meyr, Marc Moeneclaey, Stefan A. Fechtel, Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing, John Wiley & Sons, Inc., USA, 1998. [6] Chris Dick, Fred Harris, Michael Rice, FPGA Implementation of Carrier Synchronization for QAM Receivers, Journal of VLSI Signal Processing, vol.36, pp. 57-71, 2004. [7] Jin Li, Yijun Luo, Mao Tian, The Parallel Loop Filter and NCO in the All-Digital Parallel Receiver, International Journal of Digital Content Technology and its Applications, vol. 5, no. 12, pp484-490, December 2011. [8] Huang Lou, Pingfen Lin, A new lock detector for Gardner's timing recovery method, IEEE Transactions on Consumer Electronics, Vol.54, no.2, pp. 349-352, May 2008. [9] Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello, An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp.102-107, August 2007. [10] Aldo Nunzio DAndrea, Marco Luise, Optimization of Symbol Timing Recovery for QAM Data Demodulators, IEEE Trans. Commun., vol. 44, no. 3, pp. 339-406 , March 1996. [11] Lili Zhang, Zhiming He, A modified timing synchronization algorithm for QPSK in digital receiver, 2011 2nd International Conference on Artificial Intelligence, Management Science and Electronic Commerce, pp.1821-1824, August 2011. [12] Fuqin Xiong, Digital Modulation Techniques, Artech House Inc., UK, 2006. [13] John G. Proakis, Masoud Salehi, Digital Communications, McGraw Hill Inc., USA, 2009. [14] Chris Dick, Fred Harris, Michael Rice, Synchronization in software radios - Carrier and timing recovery using FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 195-204, April 2000. [15] Tao Wang, Signal Generator Based on Direct Digital Synthesis Techniques, International Journal of Digital Content Technology and its Applications, vol. 5, no. 8, pp. 24-30, August 2011. [16] Floyd M. Gardner, Interpolation in digital modems part Ifundamentals, IEEE Trans. Commun., vol.41, no. 3, pp.501-507, March 1993. [17] Floyd M. Gardner, A BPSK/QPSK Timing-Error Detector for Sampled Receivers, IEEE Trans. Commun., vol. com-34, no. 5, pp. 423-429, May 1986.

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