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NCO
Sine/Cosine
Generator
NCO
Sine/Cosine
Generator
NCO
Sine/Cosine
Generator
NCO
Sine/Cosine
Generator
Tuning
Frequency
Tuning
Frequency
Tuning
Frequency
Tuning
Frequency
Phase
Offset
Phase
Offset
Phase
Offset
Phase
Offset
Bit-Clock
Frame Syncs
Ready
B
0
1
8
7
-
0
1

t
CSU
t
CSPW
t
REC
t
REC
t
REC
t
REC
t
REC
t
CSU
t
CSPW
t
REC
t
CDLY
t
CDLY
CE
CE
CE
t
REC
t
CSU
t
CSU
t
CSU
Read Cycle - Normal Mode
Read Cycle - Held LOW RD
Write Cycle - Held LOW RD
t
CZ
t
CZ
t
CHD
t
CHD
WR
WR
WR
RD
C[07]
C[07]
C[07]
A[04]
A[04]
A[04]
CE
t
REC
t
CSU
Write Cycle - Normal Mode
t
CHD
WR
RD
C[07]
A[04]
T0169-01

t
CSU
t
CSPW
t
REC
CE
t
REC
t
EWCSU
t
CSU
Edge Write Mode
t
CHD
WR
RD
C[07]
A[04]
T0170-01

Input Format
and
Zero Pad
CIC Filter
Decimate by
4 to 4K
CFIR Filter
Decimate
by 2
PFIR Filter
Decimate
by 2
Resampler
(Shared
Between
Channels)
Course
Gain
IN
12 16 Bits
19
NCO
Tuning
Frequency
Phase
Offset
N
CFIR Taps
Ratio
PFIR Taps
RES Taps
Fine gain
Final Shift
Coarse
20
20
24
24
20
20
Q I
To
Output
Circuit
12, 16, 20 or 24 Bits
B0188-01

CK
SIB
Input
Sample Taken
Data is Sampled Every
(NZERO + 1) Clocks Thereafter

3 + NZERO Clocks
T0171-01

B0189-01
Frequency
32 Bits
32 Bits
16 Bits 5 Bits
Phase
23 MSBs 20 Bits 18 MSBs
Sin/Cos
Lookup
Table
Dither
Generator
Sin/Cos Out
150
100
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
f Frequency f
S
G
a
i
n

d
B
G001
FREQ = 5/24 f
S
105 dB
150
100
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
f Frequency f
S
G
a
i
n

d
B
G002
FREQ = 5/24 f
S
116 dB

150
100
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
f Frequency kHz
G
a
i
n

d
B
G003
107 dB
150
100
50
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
f Frequency kHz
G
a
i
n

d
B
G004
121 dB

Data In Data Out

C
I
C
_
S
C
A
L
E
D
e
c
i
m
a
t
e
b
y

F
a
c
t
o
r
o
f

N
20 Bits 24 Bits
Upper
24 Bits
Clocked at Full Rate Clocked at 1/N Rate
B0190-01

Frequency 0
100 dB
0 dB
Signal of Interest Passband (Typically 0.05 to 0.125 f )
CFIR
f /8
CFIR
f /4
CFIR
f /2
CFIR
Stopband (Typically Starts at 0.375 f )
CFIR
Very Wide Transition Band
P
o
w
e
r
M0061-01

Frequency
100 dB
0 dB
Signal-of-Interest Pass Band (Typically 0.125 to 0.2 f )
PFIR
f /4
PFIR
f /2
PFIR
Stop Band (Typically Starts Between 0.3 and 0.375 f )
PFIR
Narrow Transition Band
P
o
w
e
r
M0062-01

Input
Buffer
Final
Shift
and
Round
NDELAY NDEC
Interpolation Filter
Fractional
Decimation
Resampling Filter
QTAP Filter Coefs
In Out
B0191-01
RATIO + 2
26

NDEC
NDELAY
+ 2
26

INPUT SAMPLE RATE

OUTPUT SAMPLE RATE

NDELAY Images Added by Zero Padding

QTAP Filter
Frequency Response
a) Spectrum After Zero Padding
Images Reduced
by Filtering
Power
Power
Power
In-Band Aliasing Caused by Decimation by NDEC
Frequency
Frequency
Frequency
...
3f
S
3f
S
f
O
f
O
/2 f
O
/2 f
O
= (NDELAY/NDEC) f
S
2f
S
2f
S
f
S
/2
f
S
/2
f
S
/2
f
S
/2
f
S
f
S
f
S
f
S
2f
S
2f
S
3f
S
3f
S
...
b) Spectrum After Filtering
... ...
c) Final Spectrum After Decimating by NDEC
M0063-01

2 NO_SYM_RES
NDELAY FLOOR_2 256
NMULT NFILTER
-
=

CK
f
NMULT 2
(OUTPUT _RATES)

S

( )
FINAL _SHIFT
RES_SUM
RES_GAIN 2
32,768 NDELAY

=

( )
( )
5 (SHIFT SCALE 6 BIG_SCALE 62) COARSE
FINAL_SHIFT
1 CFIR_SUM
GAIN N 2 2
NZEROS 1 65,536
CFIR_SUM PFIR_SUM FINE_GAIN RES_SUM
2
65,536 65,536 1024 32,768 NDELAY
+ + -

=


+

32-Bit Wide-Word Port

Parallel Port
(Contains the 24-Bit Output Data)
Control Port
(Reads Back Zero)
MSB LSB
P
23
P
0
C
7
C
0
M0064-01

The Data Pins Go High-Impedance After the Last Bit

SCK
SFS
SOUT
SOUTA
SOUTA
SOUTA
SOUTB
SOUTB
SOUTC
SOUTD
SFS
SFS
SFS
(b) SFS_MODE = 2: One Frame Sync at the Start of Each Complex Word
One-, Two-, or Four-Channel Mux Modes (The Timing Shown is for SFS_MODE = 2 and BLOCK_SIZE = 3)
I15 I14 I1 I0 Q15 Q14 Q1 Q0
SCK
SFS
SOUT
(a) SFS_MODE = 3: Frame Sync at the Start of Each Word (16-Bit Words Shown)
I15 I14 I1 I0 Q15 Q14 Q1 Q0
Clock is Continuous
IA
IA
IA IA
IA
IA
IB
IB
IB IB
IB
IB
IC
IC
IC IC
IC
IC
ID
ID
ID
ID
ID
QA
QA
QA QA
QA
QA
QB
QB
QB QB
QB
QB
QC
QC
QC QC
QC
QC
QD
QD
QD
QD
QD
The Minimum Output Frame Length is Set by FRAME_LENGTH
Four Output Streams: NSERIAL = 3, WORDS_PER_FRAME = 1, OUTPUT_ORDER = 2
Two Output Streams: NSERIAL = 1, WORDS_PER_FRAME = 3, OUTPUT_ORDER = 1
Single Output Stream: NSERIAL = 0, WORDS_PER_FRAME = 7, OUTPUT_ORDER = 0
T0172-01

SCK
RDY (Q Valid)
SFS (I Valid)
P[0:23]
(a) Synchronous Channels, SFS_MODE = 0, BLOCK_SIZE = 3
AQ0 BI0 BQ0 CI0 CQ0 DI0 DQ0 AQ1 AI1 BI1 AI0
SCK
RDY (Q Valid)
SFS (I Valid)
P[0:23]
(c) Asynchronous Channels, SFS_MODE = 0, BLOCK_SIZE = 0
AQ0 BI0 BQ0 CQ0 CI0 AI0
SCK
P[0:23]
(d) Asynchronous Channels, SFS_MODE = 2, BLOCK_SIZE = 0
AQ0 BI0 BQ0 CQ0 CI0 AI0
T0173-01
SCK
RDY
(Fram Start)
RDY
(Fram Start)
SFS
(I or Q Valid)
SFS
(I or Q Valid)
P[0:23]
(b) Synchronous Channels, SFS_MODE = 2, BLOCK_SIZE = 3
AQ0 BI0 BQ0 CI0 CQ0 DI0 DQ0 AQ1 AI1 BI1 AI0

AIN13 (MSB)
J12
AIN12
H13
AIN11
H14
AIN10
H11
AIN9
H12
AIN8
G14
AIN7
G13
AIN6
F14
AIN5
F12
AIN4
F13
D1
CK
P7
E2
(MSB) C7
A6
C6
B7
C5
A7
C4
C8
C3
B8
C2
C9
C1
A9
C0
B9
B4
(MSB) A4
B5
A3
C5
A2
A5
GC4016
Quad
Receiver
Chip
GC4016
Quad
Receiver
Chip
GC4016
Quad
Receiver
Chip
GC4016
Quad
Receiver
Chip
SCK
D12
SFS
D13
RDY
A10
A1
B6
A0
C6
C4
A4
AIN3
E14
AIN2
E12
AIN1
E13
AIN0
D14
P8
BIN13 (MSB)
L8
BIN12
P9
BIN11
M9
BIN10
M10
BIN9
L10
BIN8
P11
BIN7
M11
BIN6
L12
BIN5
L14
BIN4
K13
BIN3
K14
BIN2
K12
BIN1
J13
BIN0
J14
CIN13 (MSB)
K1
CIN12
K3
CIN11
K2
CIN10
L1
CIN9
L3
CIN8
L2
CIN7
N4
CIN6
M4
CIN5
L4
CIN4
N5
CIN3
N6
CIN2
P6
CIN1
L6
CIN0
N7
DIN13 (MSB)
E1
DIN12
E3
DIN11
F2
DIN10
F1
DIN9
F3
DIN8
G2
DIN7
G1
DIN6
G4
DIN5
G3
DIN4
H1
DIN3
H2
DIN2
J1
DIN1
J3
DIN0
J2
D3
P13
K4
P12
J4
P11
H4
P10
H3
P9
F4
P8
D4
(FSD) P7
D5
(FSC) P6
D7
(FSB) P5
C7
(FSA) P4
D9
B10
A11
C11
B11
(MSB) P23
E11
P22
F11
P21
J11
P20
K11
P19
L11
P18
N10
P17
N9
P16
N8
P15
M7
P14
M6
14 Bit Input
Configuration
16 Bit Input
Configuration
14 Bit Differential Input
Configuration
12 Bit Plus Exponent
Configuration
AIN13
J12
AIN12
H13
AIN11
H14
AIN10
H11
AIN9
H12
AIN8
G14
AIN7
G13
AIN6
F14
AIN5
F12
AIN4
F13
D1
CK
P7
AIN3
E14
AIN2
E12
AIN1
E13
AIN0
D14
P8
BIN13 (MSB)
L8
BIN12 (MSB)
P9
BIN11
M9
BIN10
M10
BIN9
L10
BIN8
P11
BIN7
M11
BIN6
L12
BIN5
L14
BIN4
K13
BIN3
K14
BIN2
K12
BIN1
J13
BIN0
J14
CIN13
K1
CIN12
K3
CIN11
K2
CIN10
L1
CIN9
L3
CIN8
L2
CIN7
N4
CIN6
M4
CIN5
L4
CIN4
N5
CIN3
N6
CIN2
P6
CIN1
L6
CIN0
N7
DIN13 (MSB)
E1
DIN12 (MSB)
E3
DIN11
F2
DIN10
F1
DIN9
F3
DIN8
G2
DIN7
G1
DIN6
G4
DIN5
G3
DIN4
H1
DIN3
H2
DIN2
J1
DIN1
J3
DIN0
J2
D3
SIB SIB
SIB
D1 D1
CK CK
P7 P7
E2 E2 E2
SO SO SO
(MSB) C7 (MSB) C7 (MSB) C7
A6 A6 A6
C6 C6 C6
B7 B7 B7
C5 C5 C5
A7 A7 A7
C4 C4 C4
C8 C8 C8
C3 C3 C3
B8 B8 B8
C2 C2 C2
C9 C9 C9
C1 C1 C1
A9 A9 A9
C0 C0 C0
B9 B9 B9
CE CE CE
B4 B4 B4
(MSB) A4 (MSB) A4 (MSB) A4
B5 B5 B5
A3 A3 A3
C5 C5 C5
A2 A2 A2
A5 A5 A5
SCK SCK SCK
D12 D12 D12
SFS SFS SFS
D13 D13 D13
RDY RDY RDY
A10 A10 A10
A1 A1 A1
B6 B6 B6
A0 A0 A0
C6 C6 C6
WR WR WR
C4 C4 C4
RD RD RD
A4 A4 A4
DVAL DVAL DVAL
P8 P8
SIA SIA
SIA
D3 D3
P13 P13 P13
K4 K4 K4
P12 P12 P12
J4 J4 J4
P11 P11 P11
H4 H4 H4
P10 P10 P10
H3 H3 H3
P9 P9 P9
F4 F4 F4
P8 P8 P8
D4 D4 D4
(FSD) P7 (FSD) P7 (FSD) P7
D5 D5 D5
(FSC) P6 (FSC) P6 (FSC) P6
D7 D7 D7
(FSB) P5 (FSB) P5 (FSB) P5
C7 C7 C7
(FSA) P4 (FSA) P4 (FSA) P4
D9 D9 D9
B10 B10 B10
A11 A11 A11
C11 C11 C11
B11 B11 B11
(MSB) P23 (MSB) P23 (MSB) P23
P
i
n
s

S
h
a
r
e
d

W
i
t
h

S
e
r
i
a
l

O
u
t
p
u
t
s
E11 E11 E11
P22 P22 P22
F11 F11 F11
P21 P21 P21
J11 J11 J11
P20 P20 P20
K11 K11 K11
P19 P19 P19
L11 L11 L11
P18 P18 P18
N10 N10 N10
P17 P17 P17
N9 N9 N9
P16 P16 P16
N8 N8 N8
P15 P15 P15
M7 M7 M7
P14 P14 P14
M6 M6 M6
AIN13 (MSB) AIN13 (MSB)
J12 J12
AIN12 AIN12
H13 H13
AIN11 AIN11
H14 H14
AIN10 AIN10
H11 H11
AIN9 AIN9
H12 H12
AIN8 AIN8
G14 G14
AIN7 AIN7
G13 G13
AIN6 AIN6
F14 F14
AIN5 AIN5
F12 F12
AIN4 AIN4
F13 F13
AIN3 AIN3
E14 E14
AIN2 AIN2
E12 E12
AIN1 (EXP2) AIN1
E13 E13
AIN0 (EXP1) AIN0
D14 D14
BIN13 (MSB) BIN13 (MSB)
L8 L8
BIN12 BIN12
P9 P9
BIN11 BIN11
M9 M9
BIN10 BIN10
M10 M10
BIN9 BIN9
L10 L10
BIN8 BIN8
P11 P11
BIN7 BIN7
M11 M11
BIN6 BIN6
L12 L12
BIN5 BIN5
L14 L14
BIN4 BIN4
K13 K13
BIN3 BIN3
K14 K14
BIN2 BIN2
K12 K12
BIN1 (EXP2) BIN1
J13 J13
BIN0 (EXP1) BIN0
J14 J14
CIN13 (MSB) CIN13 (MSB)
K1 K1
CIN12 CIN12
K3 K3
CIN11 CIN11
K2 K2
CIN10 CIN10
L1 L1
CIN9 CIN9
L3 L3
CIN8 CIN8
L2 L2
CIN7 CIN7
N4 N4
CIN6 CIN6
M4 M4
CIN5 CIN5
L4 L4
CIN4 CIN4
N5 N5
CIN3 CIN3
N6 N6
CIN2 CIN2
P6 P6
CIN1 (EXP2) CIN1
L6 L6
CIN0 (EXP1) CIN0
N7 N7
DIN13 DIN13
E1 E1
DIN12 DIN12
E3 E3
DIN11 DIN11
F2 F2
DIN10 DIN10
F1 F1
DIN9 DIN9
F3 F3
DIN8 DIN8
G2 G2
DIN7 DIN7
G1 G1
DIN6 DIN6
(
M
u
s
t

b
e

G
r
o
u
n
d
e
d
)
(
M
u
s
t

b
e

G
r
o
u
n
d
e
d
)
G4 G4
DIN5 (EXP0) DIN5
G3 G3
DIN4 (A/ ) B DIN4
H1 H1
DIN3 (EXP0) DIN3
H2 H2
DIN2 (A/ ) B DIN2
J1 J1
DIN1 (EXP0) DIN1
J3 J3
DIN0 (A/ ) B DIN0
J2 J2
U
n
u
s
e
d
M
i
n
u
s
M
i
n
u
s
P
l
u
s
P
l
u
s
U
n
u
s
e
d
P
o
r
t
A
P
o
r
t
A
P
o
r
t

B
P
o
r
t
A
P
o
r
t

B
P
o
r
t

B
P
o
r
t

C
P
o
r
t

C
P
o
r
t

D
P
o
r
t

C
P
o
r
t

B
P
o
r
t
A
(SOUTA) P0 (SOUTA) P0 (SOUTA) P0
(SOUTB) P1 (SOUTB) P1 (SOUTB) P1
(SOUTC) P2 (SOUTC) P2 (SOUTC) P2
(SOUTD) P3 (SOUTD) P3 (SOUTD) P3
(SOUTA) P0
(SOUTB) P1
(SOUTC) P2
(SOUTD) P3
SIB
SO
CE
WR
RD
DVAL
SIA
M0065-01

out
PAD PAD out out
f
I (TYP) = (V ) (N )(C + 2 pf)
4




CORE CK
CORE
V f 225 23
I (TYP) 10 A 31 mA
2.5 80 MHz N R

= + + +

120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
Normalized Frequency
P

P
o
w
e
r

d
B
G005
17% Mode
Output Sample Rate = 1
120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
Normalized Frequency
P

P
o
w
e
r

d
B
G006
34% Mode
Output Sample Rate = 1
120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
Normalized Frequency
P

P
o
w
e
r

d
B
G007
68% Mode
Output Sample Rate = 1
120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
Normalized Frequency
P

P
o
w
e
r

d
B
G008
80% Mode
Output Sample Rate = 1

120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
Normalized Frequency
P

P
o
w
e
r

d
B
G009
100% Mode
Output Sample Rate = 1
120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
Normalized Frequency
P

P
o
w
e
r

d
B
G010
150% Mode
Output Sample Rate = 1

120
110
100
90
80
70
60
50
40
30
20
10
0
0 200 400 600 800 1000
f Frequency kHz
P

P
o
w
e
r

d
B
G011
Blocker Requirements
GSM Mode
Output Sample Rate = 270.833 kHz
Adjacent Band Rejection
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0 10 20 30 40 50 60 70 80 90 100
f Frequency kHz
P

P
o
w
e
r

d
B
G012
GSM Mode
Output Sample Rate = 270.833 kHz

( )
( )
5 (SHIFT SCALE 6 BIG_SCALE 62) COARSE
FINAL_SHIFT
1 CFIR_SUM
GAIN N 2 2
NZEROS 1 65,536
CFIR_SUM PFIR_SUM FINE_GAIN RES_SUM
2
65,536 65,536 1024 32,768 NDELAY
+ + -

=


+

120
110
100
90
80
70
60
50
40
30
20
10
0
0 30 60 90 120 150 180 210 240 270 300
f Frequency kHz
P

P
o
w
e
r

d
B
G013
Rejection Mask
DAMPS 2y Mode
Output Sample Rate = 48.6 kHz

( )
( )
5 (SHIFT SCALE 6 BIG_SCALE 62) COARSE
FINAL_SHIFT
1 CFIR_SUM
GAIN N 2 2
NZEROS 1 65,536
CFIR_SUM PFIR_SUM FINE_GAIN RES_SUM
2
65,536 65,536 1024 32,768 NDELAY
+ + -

=


+

120
110
100
90
80
70
60
50
40
30
20
10
0
0 1 2 3 4
f Frequency MHz
P

P
o
w
e
r

d
B
G014
IS95 Mode
900 kHz
87 dB
750 kHz
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.5
1.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
f Frequency MHz
P

P
o
w
e
r

d
B
G015
IS95 Mode
615 kHz

( )
( )
5 (SHIFT SCALE 6 BIG_SCALE 62) COARSE
FINAL_SHIFT
1 CFIR_SUM
GAIN N 2 2
NZEROS 1 65,536
CFIR_SUM PFIR_SUM FINE_GAIN RES_SUM
2
65,536 65,536 1024 32,768 NDELAY
+ + -

=


+

120
110
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 30
f Frequency MHz
P

P
o
w
e
r

d
B
G016
UMTS Mode (16y Input)
Input Sample Rate = 61.44 MHz
or 30.72 MHz
2.5 MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0 1 2
f Frequency MHz
P

P
o
w
e
r

d
B
G017
UMTS Mode (16y Input)
Output Sample Rate = 15.36 MHz

( )
( )
5 (SHIFT SCALE 6 BIG_SCALE 62) COARSE
FINAL_SHIFT
1 CFIR_SUM
GAIN N 2 2
NZEROS 1 65,536
CFIR_SUM PFIR_SUM FINE_GAIN RES_SUM
2
65,536 65,536 1024 32,768 NDELAY
+ + -

=


+

PACKAGE OPTION ADDENDUM

www.ti.com 19-Jan-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Samples
(Requires Login)
GC4016-PB NRND BGA GJZ 160 126 TBD Call TI Level-3-220C-168 HR
GC4016-PBZ NRND BGA ZJZ 160 126 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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