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SM012

42PD6700U

SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH

CAUTION:
Before servicing this chassis, it is important that the service technician read the “Safety
Precautions” and “Product Safety Notices” in this service manual.

Data contained within this Service


manual is subject to alteration for
improvement.
ATTENTION:
Avant d’effectuer l’entretien du châassis, le technicien doit lire les «Précautions de sécurité» Les données fournies dans le présent
et les «Notices de sécurité du produit» présentés dans le présent manuel. manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.

Die in diesem Wartungshandbuch


VORSICHT: enthaltenen Spezifikationen können sich
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise zwecks Verbesserungen ändern.
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.

SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT

Plasma TV
June 2006
TABLE OF CONTENTS

2 SERVICE MENU ITEMS 1


2.1. SOUND 1 1
2.2. SOUND 2 1
2.3. Options 2
2.4. Features 2
2.5. Teletext 3
2.6. Tuner Options 3
3 SOFTWARE UPDATE DESCRIPTION 4
3.1. ANALOG SOFTWARE UPDATE via SCART 4
2
3.2. ANALOG SOFTWARE UPDATE via I C 5
3.3. EEPROM UPDATE via SCART 6
4 INTRODUCTION 7
5 TUNER 7
6 IF PART (TDA9886) 7
7 MULTI-STANDARD SOUND PROCESSOR 8
8 VIDEO SWITCH TEA6415 8
9 AUDIO AMPLIFIER STAGE WITH TPA3004D2 8
10 POWER SUPPLY (SMPS) 9
11 MICRO-CONTROLLER 9
12 SERIAL ACCESS CMOS 4Kx8 (32KBit) EEPROM 24C32A 9
13 CLASS AB STEREO HEADPHONE DRIVER TDA1308 9
14 SAW FILTERS 9
15 IC DESCRIPTIONS 10
TEA6415C 10
15.1. 24LC02 12
15.1.1. Description 12
15.1.2. Features 12
15.1.3. Pinning 12
15.2. 24C32 13
15.2.1. General Description 13
15.2.2. Features 13
15.2.3. Pinning 13
15.2.4. PIN Function Table 14
15.3. 74LVC14A 14
15.3.1. Description 14
15.3.2. Features 14
15.3.3. Pinning 14
15.4. TEA6420 15
15.4.1. Features 15
15.4.2. Description 15
15.4.3. Pin Connections 15
15.5. CS4334 15
15.5.1. Features 15
15.5.2. General Description 16
15.5.3. Pin Descriptions 16
15.6. GAL16LV8 16
15.6.1. Description 16
15.6.2. Features 16
15.6.3. Pin connections 17
15.8. K6R4008V1D 17
15.8.1. Description 17
15.8.2. Features 17
15.8.3. Pin Description 18
15.9. KA278R33 18
15.9.1. Features 18
15.9.2. Description 18
15.10. LM1117 19
15.10.1. General Description 19
15.10.2. Features 19
15.10.3. Applications 19

i
15.11. LM317 19
15.11.1. General Description 19
15.11.2. Features 19
15.11.3. Pin Description 20
15.12. LM809 20
15.12.1. General Description 20
15.12.2. Features 20
15.12.3. Pinning 20
15.13. MSP34X1G (MSP3411G) 20
15.13.1. Introduction 21
15.13.2. Features 21
15.14. M29W040B 23
15.14.1. Description 23
15.14.2. Features 23
15.14.3. Pin Descriptions 24
15.15. MC33202 24
15.15.1. General Description 24
15.15.2. Features 24
15.15.3. Pin Connections 25
15.16. PCF8574 25
15.16.1. General Description 25
15.16.2. Features 25
15.16.3. Pinning 25
15.17. TSOP1836 26
15.17.1. Description 26
15.17.2. Features 26
15.18. PI5V330 26
15.18.1. General Description 26
15.19. SDA55XX (SDA5550) 27
15.19.1. General description 27
15.20. Sil 9993 27
15.20.1. General Description 27
15.20.2. Features 27
15.21. SN74CB3Q3305 28
15.21.1. General Description 28
15.21.2. Features 28
15.21.3. Pin Connections 28
15.22. ST24LC21 28
15.22.1. Description 28
15.22.2. Features 29
15.22.3. Pin connections 29
15.23. LM2576 29
15.23.1. General Description 29
15.23.2. Features 29
15.23.3. Pin description 30
15.24. MC34063 30
15.24.1. Description 30
15.24.2. Features 30
15.24.3. Pin connections 30
15.25. TDA1308 31
15.25.1. General Description 31
15.25.2. Features 31
15.25.3. Pinning 31
15.26. TDA9886 31
15.26.1. General Description 31
15.26.2. Features 31
15.26.3. Pinning 32
15.27. TPA3004D2 32
15.27.1. General Description 32
15.27.2. Features 32
15.27.3. Pinning 33

ii
15.29. μPA672T 34
15.29.1. General Description 34
15.29.2. Features 34
15.29.3. Pin Connection 34
15.30. VPC3230D 34
15.30.1. General Description 34
15.30.2. Pin Connections and Short Descriptions 34
15.31. MAD4868A 36
15.31.1. General Description 36
15.31.2. Features 36
15.31.3. Interfaces 36
15.31.4. Pinning 37
15.32. SVP-EX 59B 37
16 SERVICE MENU SETTINGS 37
16.1. Picture Adjust 38
16.2. SOUND 1 38
16.3. SOUND 2 38
16.4. Options 38
17 IC DESCRIPTIONS (FOR DIGITAL) 39
17.1. STI5518 39
17.1.1. General Description 39
17.2. MAX232_SMD 40
17.2.1. General Description 40
17.2.2. Features 40
17.3. 74HCU04 40
17.3.1. General Description 40
17.3.2. Pin Description 40
17.4. TSH22 41
17.4.1. General Description 41
17.4.2. Pin Connections 41
17.5. CS4334 41
17.5.1. General Description 41
17.5.2. Features 41
17.6. AMIC A43L2616 41
17.6.1. General Description 41
17.6.2. Features 41
17.6.3. Pin Description 42
17.7. MX29LV160T 43
17.7.1. General Description 43
17.7.2. Features 43
17.7.3. Pin Description 43
17.8. 24C32 44
17.8.1. General Description 44
17.8.2. Features 44
17.8.3. Pin Description 44
17.9. STV0360 45
17.9.1. General Description 45
17.9.2. Features 45
17.9.3. Pin Description 45
17.10. MAX809 47
17.10.1. General Description 47
17.10.2. Features 47
17.10.3. Pin Description 48
17.11. TDCC2345TV39A 48
17.11.1. General Description 48
17.11.2. Pin Description 48
17.12. STV0700 49
17.12.1. General description 49
17.12.2. Features 49
17.12.3. Pin Description 49

iii
18 APPENDIX A 53
18.1. EXPLODED VIEW 73

19 APPENDIX B 54
19.1. BLOCK DIAGRAM 54
19.2. SCHEMATIC DIAGRAMS 55
19.2.1. Power Board 55
19.2.2. Main Board 60
19.2.3. Amplifier Board 68
19.2.4. Front AV Board 69
19.3. CIRCUIT BOARDS 70
19.4. PCB LAYOUTS 71
19.4. CONNECTOR DIAGRAM 72

20 APPENDIX C 73
20.1. SPARES PARTLIST 73

iv
2. SERVICE MENU ITEMS

2.1. SOUND 1
a) Menu Subwoofer => If ON, Subwoofer option is available in TV set, and the item is
visible in sound menu, else Subwoofer is not available. Default “ON”.

b) Subwoofer Level (dB) => This value is gain value of Subwoofer output in dB.
-30...12. Default “0” dB.

c) Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40.
Default “22” x 10Hz = 220Hz.

d) Menu Equalizer => If ON, visible in sound menu, else invisible. Default “ON”.

e) Menu Headphone => If ON, visible in sound menu, else invisible. Default “ON”.

f) Menu Effect => If ON, visible in sound menu, else invisible. Default “ON”.

g) Menu Wide Sound => If ON, visible in sound menu, else invisible. Default “OFF”.

h) Menu Dynamic Bass => If ON, visible in sound menu, else invisible. Default “ON”.

i) Menu Virtual Dolby => If ON, visible in sound menu, else invisible. Default “ON”.

j) Carrier Mute => If ON, in the absence of an FM carrier the output is muted, else not.
Default “ON”.

k) Virtual Dolby Text => Active if VIRTUAL DOLBY is ON.According to the selection; seen
in sound menu as 3DS or VIRTUAL DOLBY. Default “3DS”.

2.2. SOUND 2

a) AVL => AVL is controlled from this menu by service user. ON/OFF. Default “ON”.

b) Menu AVL => If ON, AVL item is visible in sound menu, and AVL can be controlled from
sound menu by normal user, else AVL is invisible to normal user. ON/OFF. Default “ON”.

c) FM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127. Default “29”.

d) NICAM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127. Default “62”.

e) SCART PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for scart outputs. 0...127. Default “28”.

f) SCART VOLUME AVL ON => If AVL ON, set value in this item is used as volume value
for scart1 and scart2. 0...127. Default “116”.

1
g) FM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127. Default “15”.

h) NICAM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as
prescale value for the related standard. 0...127. Default “35”.

i) SCART PRESCALE AVL OFF => If AVL OFF, set value in this item is used as
prescale value for scart outputs. 0...127. Default “14”.

j) SCART VOLOUME AVL OFF => If AVL OFF, set value in this item is used as volume
value for scart1 and scart2. 0...127. Default “122”.

2.3. Options

a) Burn-In Mode => If ON, full screen flashes in RED, GREEN, BLUE colors unless
“Menu” button on Remote Control or Keypad is pressed. This property is used to protect the TV
set from burning on the assembly lines in factory. This item becomes automatically OFF, when
First APS item is ON or Factory Reset is pressed. ON/OFF. Default OFF.

b) First APS => This bit is set “ON” in the factory. When the TV set is opened for
the first time it directs the user to make automatic search in both digital and analog modes.

c) APS Volume => After First APS function finishes, the volume of the TV is that value.
Default “10”.

d) AGC (dB) => Tuner AGC value. Default “15”.

e) Power-Up Mode =>Normal, Last State, Stand-by. Default “Last State”

f) PDP Working Hour =>Displays Panel Run time in decimal.

g) Factory Reset => OK to activate. When OK pressed on this item, factory defaults
loaded.

h) Enter Flash Mode =>OK to activate. When OK pressed on this item, flash mode is entered,
SW starts to wait for uploading the new SW.

2.4. Features
a) Blue Background => If ON, Blue Background is visible in Features Menu else not.
Default “ON”.

b) Menu Transparency => If ON, Menu Transparency is visible in Features Menu else not.
Default “ON”.

c) Menu Timeout => If ON, Menu Timeout is visible in Features Menu else not. Default
“ON”.
d) Backlight => If ON, Backlight is visible in Features Menu else not.Default “OFF”.

e) Single Tuner => If OFF, two tuners are available on the chassis. Fixed “ON”.

f) Dynamic WB => Default

2
2.5. Teletext

a) TOP TXT => ON/OFF

b) Fast TXT => ON/OFF

c) Teletext Language => Teletext Language may be controlled from this menu by service
user.

d) Txt Start RF

e) Txt Start Ext

f) Txt Start Mix

g) Menu Teletext Language => If ON, Teletext Language item is visible in Features Menu, and
Teletext Language can be controlled from Features Menu by normal user, else Teletext
Language is invisible to normal user.

2.6. Tuner Options

a) Switch Low Band


b) Switch Mid Band
c) Switch High Band
d) Boundry1 Low Byte
e) Boundry1 High Byte
f) Boundry2 Low Byte
g) Boundry2 High Byte
h) Control Byte
These values need to be filled in the factory acording to the tuner used on the chassis.
i) Store => OK to store; when the values are entered correctly OK needs to be pressed on this
item to store the values.

3
3. SOFTWARE UPDATE DESCRIPTION

3.1. ANALOG SOFTWARE UPDATE via SCART

STEP.1

Enter service menu by pressing the buttons “MENU”,”4”,”7”,”2”,”5” respectively.

STEP.2

Select “OPTIONS” from the service menu and “ENTER FLASH MODE”

STEP.3

Connect the Software Update Tool (17tr15-3) to parellel port of your PC.

STEP.4

Connect scart-end of the cable to Scart-1 (Ext-1).

STEP.5

Connect other-end of cable to “PL 2” socket on the Update Tool (17tr15-3)

STEP.6

Run IAPWriter.exe.

STEP.7

Click “load file” and load the required software.

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3.2. ANALOG SOFTWARE UPDATE via I2C

STEP.1

Enter service menu by pressing the buttons “MENU”,”4”,”7”,”2”,”5” respectively.

STEP.2

Select “OPTIONS” from the service menu and “ENTER FLASH MODE”

STEP.3

Connect the Software Update Tool (17tr15-3) to parellel port of your PC.

STEP.4

Connect one-end of cable to “PL604” socket on the chassis socket MB15

STEP.5

Connect other-end of cable to “PL 2” socket on the Update Tool (17tr15-3)

STEP.6

Run IAPWriter.exe.

STEP.7

Click “load file” and load the required software.

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3.3. EEPROM UPDATE via SCART

STEP.1.

Insert the EEROM tool(TR16) to SCART-1

STEP.2.

Enter service menu by pressing the buttons “MENU”,”4”,”7”,”2”,”5” respectively

STEP.3.

Press “YELLOW” colour button on the remote controller.


Then you will have two options

STEP.3.a

Press “RED” colour button to copy data of external EEPROM into internal one

STEP.3.b

Press “GREEN” colour button to copy data of internal EEPROM into external one

6
4. INTRODUCTION
42” Plasma TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 1024x1024
panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards
and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Sound
system output is supplying 2x10W (10%THD) for stereo 8ȍ speakers. The chassis is equipped with many inputs
and outputs allowing it to be used as a center of a media system.

It supports following peripherals:


2 SCART sockets
1 AV input (CVBS + Stereo Audio)
1 SVHS input
1 Stereo Headphone input
1 Component input (YPbPr + Stereo Audio)
1 D-Sub 15 PC input
1 HDMI input
1 Stereo audio input for PC
1 Stereo audio output
1 Subwoofer output

5. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’, I/I’, and
D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on one of the
Tuners in use.

General description of UV1316:


The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low IF output
impedance has been designed for direct drive of a wide variety of SAW filters with sufficient suppression of triple
transient.

Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I2C-bus
4. Off-air channels, S-cable channels and Hyperband
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”

Pinning:
1. Gain control voltage (AGC) : 4.0V, Max: 4.5V
2. Tuning voltage
3. I²C-bus address select : Max: 5.5V
4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V
5. I²C-bus serial data : Min:-0.3V, Max: 5.5V
6. Not connected
7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V
8. ADC input
9. Tuner supply voltage : 33V, Min: 30V, Max: 35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2

6. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL. The
following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:

7
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO and
divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF amplifier, SIF-AGC
detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition help, Audio amplifier and
mute time constant, I²C-bus transceivers and MAD (module address), Internal voltage stabilizer.

7. MULTI STANDARD SOUND PROCESSOR


The MSP34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analogue TV-
Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analogue
sound IF signal-in, down to processed analogue AF-out, is performed on a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal
conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX
noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed
standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The
MSP 34x1G has optimum stereo performance without any adjustments.

8. VIDEO SWITCH TEA6415


In case of three or more external sources are used, the video switch IC TEA6415 is used. The main function of this device is
to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level of the
signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment is switched off by
forcing, with an external resistor bridge, 5VDC on the input. Each input can be used as a normal input or as a MAC or
Chroma input (with external Resistor Bridge). All the switching possibilities are changed through the BUS. Driving 75ohm
load needs an external resistor. It is possible to have the same input connected to several outputs.

9. AUDIO AMPLIFIER STAGE WITH TPA3004D2


The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The
TPA3004D2 can drive stereo speakers as low as 4 Ÿ. The high efficiency of the TPA3004D2 eliminates the need for
external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –
40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range
of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.

8
10. POWER SUPPLY (SMPS)
The DC voltages required at various parts of the chassis are provided by an SMPS transformer controlled by the IC
MC44608, which is designed for driving, controlling and protecting switching transistor of SMPS. The transformer
generates 145V for FBT input, +/-14V for audio amplifier, 5V and 3.3V stand by voltage and 8V, 12V and 5V supplies for
other different parts of the chassis.
An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There is a regulation
circuit in secondary side. This circuit produces a control voltage according to the changes in 145V DC voltage, via an
optocoupler (TCET1102G) to pin3 of the IC.
During the switch on period of the transistor, energy is stored in the transformer. During the switch off period
energy is fed to the load via secondary winding. By varying switch-on time of the power transistor, it controls
each portion of energy transferred to the second side such that the output voltage remains nearly independent
of load variations.

11. MICROCONTROLLER
The Micronas SDA 55xx TV microcontroller is dedicated to 8 bit applications for TV control and provides dedicated
graphic features designed for modern low class to mid range TV sets. The SDA 55xx provides also an integrated
general purposefully 8051-compatible microcontroller with specific hardware features especially suitable in TV sets.
The microcontroller core has been enhanced to provide powerful features such as memory banking, data pointers and
additional interrupts, etc. The internal XRAM consists of up to 16 kBytes. The microcontroller provides an internal
ROM of up to 128 kBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The 8-bit
microcontroller runs at 33.33 MHz internal clock. SDA 55xx is realized in 0.25 micron technology with 2.5 V supply
voltage for the core and 3.3 V for the I/O port pins to make them TTL compatible. Based on the SDA 55xx
microcontroller the MINTS software package was developed and provides dedicated device drivers for many Micronas
video & audio products and includes a full blown TV control SW for the PEPER application chassis. The SDA 55xx is
also supported with powerful design tools like emulators from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler and
TEDIpro OSD development SW by Tara Systems.

12. SERIAL ACCESS CMOS 4Kx8(32KBit)EEPROM 24C32A


The Microchip Technology Inc. 24AA32A/24LC32A(24XX32A*) is a 32 Kbit Electrically Erasable PROM. The device is
organized as four blocks of 8K x 8-bitmemory with a 2-wire serial interface. Low-voltage design permits operation
down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. It has been developed for
advanced, low-power applications such as personal communications or data acquisition. The 24XX32A also has a
page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for
up to 256Kbits address space.

13. CLASS AB STEREO HEADPHONE DRIVER TDA1308


The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package. The
device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio
applications.

14. SAW FILTERS


K9656M:
Standard:
• B/G
• D/K
•I
• L/L’

Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40.40 MHz (L’) and 39.75 MHz (L’- NICAM)
• Channel 2 (B/G, D/K, L, I) with one pass band for sound carriers between 32.35 MHz and 33.40 MHz

Terminals
• Tinned CuFe alloy

Pin configuration
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output

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K3958M:
Standard:
• B/G
• D/K
•I
• L/L’

Features
• TV IF video filter with Nyquist slopes at 33.90 MHz and 38.90 MHz
• Constant group delay

Terminals
Tinned CuFe alloy

Pin configuration
1 Input
2 Input - ground
3 Chip carrier - ground
4 Output
5 Output

15. IC DESCRIPTIONS
TEA6415C
24LC02
24C32
74LVC14A
TEA6420D
CS4334
GAL16LV8
K6R4008V1
KA278R33
LM1117
LM317T
LM809
MSP3411G
M29W040B
MC33202
PCF8574
TSOP1836
PI5V330
SDA5550
SII9993
SN74CB3Q3305
ST24LC21
LM2576
MC34063
TDA1308
TDA9886T
TPA3004D2
μPA672T
VPC3230D
MAD4868A
SVP EX-59B
TEA6415C

General Description
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only
one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for
CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or
Chroma signal the alignment is switched off by forcing, with an external resistor bridge, 5 VDC on the input. Each
input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the
switching possibilities are changed through the BUS. Driving 75Ÿ load needs an external transistor. It is possible

10
to have the same input connected to several outputs. The starting configuration upon power on (power supply: 0
to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other
case, 1 word of 16 bits is necessary to determine one configuration.
Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
Pinning
1. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
2. Data : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
4. Clock : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
5. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
6. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
7. Prog
8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
9. Vcc : 12V
10. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
11. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
12. Ground
13. Output : 5.5Vpp, Min : 4.5Vpp
14. Output : 5.5Vpp, Min : 4.5Vpp
15. Output : 5.5Vpp, Min : 4.5Vpp
16. Output : 5.5Vpp, Min : 4.5Vpp
17. Output : 5.5Vpp, Min : 4.5Vpp
18. Output : 5.5Vpp, Min : 4.5Vpp
19. Ground
20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA

11
15.1. 24LC02

15.1.1. Description
The Microchip Technology Inc. 24AA02/24LC02B (24XX02*) is a 2 Kbit Electrically Erasable PROM. The device
is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits
operation down to 1.8V, with standby and active currents of only 1μA and 1mA, respectively. The 24XX02 also
has a page write capability for up to 8 bytes of data.

15.1.2. Features
• Single supply with operation down to 1.8V
• Low-power CMOS technology
-1mA active current typical
-1μA standby current typical (I-temp)
• Organized as 1 block of 256 bytes (1 x 256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (24AA02) and 400 kHz (24LC02B) compatibility
• Self-timed write cycle (including auto-erase)
• Page write buffer for up to 8 bytes
• 2ms typical write cycle time for page write
• Hardware write-protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
• 1,000,000 erase/write cycles
• Data retention > 200 years
• 8-lead PDIP, SOIC, TSSOP and MSOP packages
• 5-lead SOT-23 package
• Pb-free finish available
• Available for extended temperature ranges:
-Industrial (I): -40°C to +85°C
-Automotive (E): -40°C to +125°C

15.1.3. Pinning

12
15.2. 24C32

15.2.1. General Description


The Microchip Technology Inc. 24C32 is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. This device has
been developed for advanced, low power applications such as personal communications or data acquisition.
The 24C32 features an input cache for fast write loads with a capacity of eight 8-byte pages, or 64 bytes. It also
features a fixed 4K-bit block of ultra-high endurance memory for data that changes frequently. The 24C32 is
capable of both random and sequential reads up to the 32K boundary. Functional address lines allow up to 8 -
24C32 devices on the same bus, for up to 256K bits address space. Advanced CMOS technology makes this
device ideal for low-power non-volatile code and data applications.

15.2.2. Features
• Voltage operating range: 4.5V to 5.5V
- Peak write current 3 mA at 5.5V
- Maximum read current 150μA at 5.5V
- Standby current 1μA typical
• Industry standard two-wire bus protocol, I2C™ compatible
-Including 100 kHz and 400 kHz modes
• Self-timed write cycle (including auto-erase)
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 Erase/Write cycles guaranteed for High Endurance Block
- 10,000,000 E/W cycles guaranteed for Standard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to 8 chips may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• Temperature ranges:
-Commercial (C): 0°C to +70°C
-Industrial (I): -40°C to +85°C

15.2.3. Pinning

13
15.2.4. PIN Function Table

PIN DESCRIPTIONS
A0, A1, A2 Chip Address Inputs
The A0...A2 inputs are used by the 24C32 for multiple device operation and conform to the two-wire bus stan-
dard. The levels applied to these pins define the address block occupied by the device in the address map. A
particular device is selected by transmitting the corresponding bits (A2, A1, and A0) in the control byte.
SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain
terminal; therefore the SDA bus requires a pull-up resistor to VCC (typical 10KQ for 100 kHz, 1KQ for 400 kHz).
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.

15.3. 74LVC14A

15.3.1. Description
The 74LVC14A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5V devices. This feature allows the use of
these devices as translators in a mixed 3.3 and 5V environment. The 74LVC14A provides six inverting buffers with
Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output
signals.

15.3.2. Features
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no.8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000V
MM EIA/JESD22-A115-A exceeds 200V.
• Specified from -40 to +85C and -40 to +125C.

15.3.3. Pinning

14
15.4. TEA6420

15.4.1. Features
• 5 Stereo Inputs
• 4 Stereo Outputs
• Gain Control 0/2/4/6dB/Mute for each Output
• Cascadable (2 different addresses)
• Serial Bus Controlled
• Very low Noise
• Very low Distortion

15.4.2. Description
The TEA6420 switches 5 stereo audio inputs on4stereo outputs. All the switching possibilities are changed
through the I2C bus.

15.4.3. Pin Connections

15.5. CS4334

15.5.1. Features
• Complete Stereo DAC System: Interpolation, D/A, Output Analog Filtering
• 24-Bit Conversion

15
• 96 dB Dynamic Range
• -88 dB THD+N
• Low Clock Jitter Sensitivity
• Single +5V Power Supply
• Filtered Line Level Outputs
• On-Chip Digital De-emphasis
• Popgaurd® Technology
• Functionally Compatible with CS4330/31/33

15.5.2. General Description


The CS4334 family members are complete, stereo digital-to-analog output systems including interpolation, 1-
bitD/A conversion and output analog filtering in an 8-pinpackage. The CS4334/5/6/7/8/9 support all major audio
data interface formats, and the individual devices differ only in the supported interface format. The CS4334
family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to
an ultra-linear analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2
kHz and 100 kHz simply by changing the master clock frequency. The CS4334 family contains on-chip digital
de-emphasis, operates from a single +5V power supply, and requires minimal support circuitry. These features
are ideal for set-top boxes, DVD players, SVCD players, and A/V receivers.

15.5.3. Pin Descriptions

15.6. GAL16LV8

15.6.1. Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available
in the PLD market. The GAL16LV8C can interface with both 3.3V and 5Vsignal levels. The GAL16LV8 is
manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with
Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be
reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all
architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during
manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all
GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

15.6.2. Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz

16
- 2.5 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
- JEDEC-Compatible 3.3V Interface Standard
- 5V Compatible Inputs
- I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- Glue Logic for 3.3V Systems
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS

15.6.3. Pin connections

15.7.

15.8. K6R4008V1D

15.8.1. Description
The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by
8 bits. TheK6R4008V1D uses 8 common input and output lines and has an output enable pin which operates
faster than address access time at read cycle. The device is fabricated using SAMSUNGƍs advanced CMOS
process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-
speed system applications. The K6R4008V1D is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic
TSOP type II.

15.8.2. Features
• Fast Access Time 8, 10ns(Max.)
• Low Power Dissipation
- Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
- Operating K6R4008V1D-08 : 80mA(Max.)

17
K6R4008V1D-10 : 65mA(Max.)
• Single 3.3 ±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008V1D-J : 36-SOJ-400
K6R4008V1D-K : 36-SOJ-400(Lead-Free)
K6R4008V1D-T : 44-TSOP2-400BF
K6R4008V1D-U : 44-TSOP2-400BF(Lead-Free)
• Operating in Commercial and Industrial Temperature range.

15.8.3. Pin Description

15.9. KA278R33

15.9.1. Features
• 2A / 3.3V Output low dropout voltage regulator
• TO220 Full-Mold package (4PIN)
• Overcurrent protection, Thermal shutdown
• Overvoltage protection, Short-Circuit protection
• With output disable function

15.9.2. Description
The KA278R33 is a low-dropout voltage regulator suitable for various electronic equipments. It provides
constant voltage power source with TO-220 4 lead full mold package. Dropout voltage of KA278R33 is below

18
0.5V in full rated current (2A). This regulator has various function such as peak current protection, thermal shut
down, overvoltage protection and output disable function.

15.10. LM1117

15.10.1. General Description


The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same
pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which
can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed
voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-223, TO-
220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve
the transient response and stability.

15.10.2. Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C

15.10.3. Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
Connection Diagrams

15.11. LM317

15.11.1. General Description


This monolithic integrated circuit is an adjustable 3-terminal positive voltage regulator designed to supply more
than 1.5A of load current with an output voltage adjustable over a 1.2 to 37V. It employs internal current limiting,
thermal shut-down and safe area compensation.

15.11.2. Features
• Output Current In Excess of 1.5A
• Output Adjustable Between 1.2V and 37V
• Internal Thermal Overload Protection
• Internal Short Circuit Current Limiting
• Output Transistor Safe Operating Area Compensation
• TO-220 Package

19
15.11.3. Pin Description

15.12. LM809

15.12.1. General Description


The LM809/810 microprocessor supervisory circuits can be used to monitor the power supplies in microprocessor and
digital systems. They provide a reset to the microprocessor during power-up, power-down and brown-out conditions.
The function of the LM809/810 is to monitor the VCC supply voltage, and assert a reset signal whenever this voltage
declines below the factory-programmed reset threshold. The reset signal remains asserted for 240 ms after VCC rises
above the threshold. The LM809 has an active-low RESET output, while the LM810 has an active-high RESET output.
Seven standard reset voltage options are available, suitable for monitoring 5V, 3.3V, and 3V supply voltages. With a
low supply current of only 15μA, the LM809/810 are ideal for use in portable equipment.

15.12.2. Features
• Precise monitoring of 3V, 3.3V, and 5V supply voltages
• Superior upgrade to MAX809/810
• Fully specified overtemperature
• 140 ms min. Power-On Reset pulse width, 240 ms typical
Active-low RESET Output(LM809)
Active-high RESET Output(LM810)
• Guaranteed RESET Output valid for VCC•1V
• Low Supply Current, 15μAtyp
• Power supply transient immunity

15.12.3. Pinning

15.13. MSP34X1G (MSP3411G)


Multistandard Sound Processor Family

20
15.13.1. Introduction
The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all
analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure
shows a simplified functional block diagram of the MSP 34x1G.
The MSP 34x1G has all functions of the MSP 34x0G with the addition of a virtual surround sound feature.
Surround sound can be reproduced to a certain extent with two loudspeakers. The MSP 34x1G includes the
Micronas virtualizer algorithm “3D-PANORAMA” which has been approved by the Dolby 1) Laboratories for with
the "Virtual Dolby Surround" technology. In addition, the MSP 34x1G includes the “PAN-ORAMA” algorithm.
These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming
to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or
alternatively, Micronas Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio
standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and
EIA-J. The MSP 34x1G has optimum stereo performance without any adjustments.
The MSP 34x1G has built-in automatic functions: The IC is able to detect the actual sound standard automat-
ically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/stereo/bilingual; no I 2 C interaction is necessary (Automatic
Sound Selection).

Source Select
I2S bus interface consists of five pins:
1. I2S_DA_IN1, I2S_DA_IN2: For input, four channels (two channels per line, 2*16 bits) per sampling cycle (32
kHz) are transmitted.
2. I2S_DA_OUT: For output, two channels (2*16 bits) per sampling cycle (32 kHz) are transmitted.
3. I2S_CL: Gives the timing for the transmission of I2S serial data (1.024 MHz).
4. I2S_WS: The I2S_WS word strobe line defines the left and right sample.

15.13.2. Features
• Standard Selection with single I2C transmission
• Automatic Standard Detection of terrestrial TV standards
• Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
• Two selectable sound IF (SIF) inputs
• Automatic Carrier Mute function
• Interrupt output programmable (indicating status change)
• Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness
• AVC: Automatic Volume Correction
• Subwoofer output with programmable low-pass and complementary high-pass filter
• 5-band graphic equalizer for loudspeaker channel
• Spatial effect for loudspeaker channel
• Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs

21
• Complete SCART in/out switching matrix
• Two I2S inputs; one I2S output
• Dolby Pro Logic with DPL 351xA coprocessor
• All analog FM-Stereo A2 and satellite standards; AM-SECAM L standard
• Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
• Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
• ASTRA Digital Radio (ADR) together with DRP 3510A
• All NICAM standards
• Korean FM-Stereo A2 standard
Pin connections

NC = not connected; leave vacant

LV = if not used, leave vacant


OBL = obligatory; connect as described in circuit diagram
DVSS: if not used, connect to DVSS
AHVSS: connect to AHVSS

Connection
Pin No. Pin Name Type Short Description
(if not used)
PLCC PSDIP PSDIP PQFP PLQFP
68-pin 64-pin 52-pin 80-pin 64-pin
1 16 14 9 8 ADR_WS OUT LV ADR word strobe
2 - - - - NC LV Not connected
3 15 13 8 7 ADR_DA OUT LV ADR Data Output
2
4 14 12 7 6 I2S_DA_IN1 IN LV I S1 data input
2
5 13 11 6 5 I2S_DA_OUT OUT LV I S data output
2
6 12 10 5 4 I2S_WS IN/OUT LV I S word strobe
2
7 11 9 4 3 I2S_CL IN/OUT LV I S clock
2
8 10 8 3 2 I2C_DA IN/OUT OBL I C data
2
9 9 7 2 1 I2C_CL IN/OUT OBL I C clock
10 8 - 1 64 NC LV Not connected
11 7 6 80 63 STANDBYQ IN OBL Stand-by (low-active)
2
12 6 5 79 62 ADR_SEL IN OBL I C bus address select
13 5 4 78 61 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0
14 4 3 77 60 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1
15 3 - 76 59 NC LV Not connected
16 2 - 75 58 NC LV Not connected
17 - - - - NC LV Not connected
Audio clock output
18 1 2 74 57 AUD_CL_OUT OUT LV
(18.432 MHz)
19 64 1 73 56 TP LV Test pin
20 63 52 72 55 XTAL_OUT OUT OBL Crystal oscillator
21 62 51 71 54 XTAL_IN IN OBL Crystal oscillator
22 61 50 70 53 TESTEN IN OBL Test pin
IF Input 2 (can be left
AVSS via
23 60 49 69 52 ANA_IN2+ IN vacant, only if IF input 1 is
56 pF/LV
also not in use)
IF common (can be left
AVSS via
24 59 48 68 51 ANA_IN- IN vacant, only if IF input 1 is
56 pF/LV
also not in use)
25 58 47 67 50 ANA_IN1+ IN LV IF input 1
26 57 46 66 49 AVSUP OBL Analog power supply 5V
- - - 65 - AVSUP OBL Analog power supply 5V
- - - 64 - NC LV Not connected
- - - 63 - NC LV Not connected
27 56 45 62 48 AVSS OBL Analog ground
- - - 61 - AVSS OBL Analog ground
28 55 44 60 47 MONO_IN IN LV Mono input
- - - 59 - NC LV Not connected
Reference voltage IF A/D
29 54 43 58 46 VREFTOP OBL
converter
30 53 42 57 45 SC1_IN_R IN LV SCART 1 input, right
31 52 41 56 44 SC1_IN_L IN LV SCART 1 input, left
32 51 - 55 43 ASG1 AHVSS Analog Shield Ground 1
33 50 40 54 42 SC2_IN_R IN LV SCART 2 input, right
34 49 39 53 41 SC2_IN_L IN LV SCART 2 input, left
35 48 - 52 40 ASG2 AHVSS Analog Shield Ground 2
36 47 38 51 39 SC3_IN_R IN LV SCART 3 input, right

22
37 46 37 50 38 SC3_IN_L IN LV SCART 3 input, left
38 45 - 49 37 ASG4 AHVSS Analog Shield Ground 4
39 44 - 48 36 SC4_IN_R IN LV SCART 4 input, right
40 43 - 47 35 SC4_IN_L IN LV SCART 4 input, left
41 - - 46 - NC LV or AHVSS Not connected
42 42 36 45 34 AGNDC OBL Analog reference voltage
43 41 35 44 33 AHVSS OBL Analog ground
- - - 43 - AHVSS OBL Analog ground
- - - 42 - NC LV Not connected
- - - 41 - NC LV Not connected
44 40 34 40 32 CAPL_M OBL Volume capacitor MAIN
45 39 33 39 31 AHVSUP OBL Analog power supply 8V
46 38 32 38 30 CAPL_A OBL Volume capacitor AUX
47 37 31 37 29 SC1_OUT_L OUT LV SCART output 1, left
48 36 30 36 28 SC1_OUT_R OUT LV SCART output 1, right
49 35 29 35 27 VREF1 OBL Reference ground 1
50 34 28 34 26 SC2_OUT_L OUT LV SCART output 2, left
51 33 27 33 25 SC2_OUT_R OUT LV SCART output 2, right
52 - - 32 - NC LV Not connected
53 32 - 31 24 NC LV Not connected
54 31 26 30 23 DACM_SUB OUT LV Subwoofer output
55 30 - 29 22 NC LV Not connected
56 29 25 28 21 DACM_L OUT LV Loudspeaker out, left
57 28 24 27 20 DACM_R OUT LV Loudspeaker out, right
58 27 23 26 19 VREF2 OBL Reference ground 2
59 26 22 25 18 DACA_L OUT LV Headphone out, left
60 25 21 24 17 DACA_R OUT LV Headphone out, right
- - - 23 - NC LV Not connected
- - - 22 - NC LV Not connected
61 24 20 21 16 RESETQ IN OBL Power-on-reset
62 23 - 20 15 NC LV Not connected
63 22 - 19 14 NC LV Not connected
64 21 19 18 13 NC LV Not connected
2
65 20 18 17 12 I2S_DA_IN2 IN LV I S2-data input
66 19 17 16 11 DVSS OBL Digital ground
- - - 15 - DVSS OBL Digital ground
- - - 14 - DVSS OBL Digital ground
67 18 16 13 10 DVSUP OBL Digital power supply 5V
- - - 12 - DVSUP OBL Digital power supply 5V
- - - 11 - DVSUP OBL Digital power supply 5V
68 17 15 10 9 ADR_CL OUT LV ADR clock

15.14. M29W040B

15.14.1. Description
The M29W040B is a 4 Mbit (512Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations
can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode
where it can be read in the same way as a ROM or EPROM. The M29W040B is fully backward compatible with the
M29W040.The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while
old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from
modifying the memory. Program and Erase commands are writ-ten to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase operation can be detected and
any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip
Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to
most microprocessors, often without additional logic.

15.14.2. Features
• SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS
• ACCESS TIME: 55ns
• PROGRAMMING TIME
- 10μs per Byte typical8
• UNIFORM 64 Kbytes MEMORY BLOCKS
• PROGRAM/ERASE CONTROLLER
- Embedded Byte Program algorithm
- Embedded Multi-Block/Chip Erase algorithm
- Status Register Polling and Toggle Bits

23
• ERASE SUSPEND and RESUME MODES
- Read and Program another Block during Erase Suspend
• UNLOCK BYPASS PROGRAM COMMAND
- Faster Production/Batch Programming
• LOW POWER CONSUMPTION
- Standby and Automatic Standby
• 100,000 PROGRAM/ERASE CYCLES per BLOCK
• 20 YEARS DATA RETENTION
- Defectivity below 1 ppm/year
• ELECTRONIC SIGNATURE
- Manufacturer Code: 20h
- Device Code: E3h

15.14.3. Pin Descriptions

15.15. MC33202

15.15.1. General Description


The MC33201/2/4 family of operational amplifiers provide railítoírail operation on both the input and output.
The inputs can be driven as high as 200mV beyond the supply rails without phase reversal on the outputs, and
the output can swing within 50 mV of each rail. This railítoírail operation enables the user to make full use of
the supply voltage range available. It is designed to work at very low supply voltages (±0.9 V) yet can operate
with a supply of up to +12V and ground. Output current boosting techniques provide a high output current
capability while keeping the drain current of the amplifier to a minimum. Also, the combination of low noise and
distortion with a high slew rate and drive capability make this an ideal amplifier for audio applications.

15.15.2. Features
• Low Voltage, Single Supply Operation (+1.8 V and Ground to +12 V and Ground)
• Input Voltage Range Includes both Supply Rails
• Output Voltage Swings within 50 mV of both Rails
• No Phase Reversal on the Output for Overídriven Input Signals
• High Output Current (ISC = 80 mA, Typ)
• Low Supply Current (ID = 0.9 mA, Typ)
• 600 Ÿ Output Drive Capability
• Extended Operating Temperature Ranges (í40° to +105°C and í55° to +125°C)
• Typical Gain Bandwidth Product = 2.2 MHz
• PbíFree Packages are Available

24
15.15.3. Pin Connections

15.16. PCF8574

15.16.1. General Description


The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I2C).The device consists of an 8-bit quasi-bidirectional port and an I2C-bus
interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for
directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the
microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is
incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a
simple slave device.

15.16.2. Features
• Operating supply voltage 2.5 to 6V
• Low standby current consumption of 10 μA maximum
• I2C to parallel port expander
• Open-drain interrupt output
• 8-bit remote I/O port for the I2C-bus
• Compatible with most microcontrollers
• Latched outputs with high current drive capability for directly driving LEDs
• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)
• DIP16, or space-saving SO16 or SSOP20 packages.

15.16.3. Pinning

25
15.17. TSOP1836

15.17.1. Description
The TSOP18.– series are miniaturized receivers for infrared remote control systems. PIN diode and preamplifier
are assembled on lead frame, the epoxy package is designed as IR filter. Carrier frequency for TSOP1836 is 36
kHz.
The demodulated output signal can directly be decoded by a microprocessor. The main benefit is the reliable
function even in disturbed ambient and the protection against uncontrolled output pulses.

15.17.2. Features
• Photo detector and preamplifier in one package
• Internal filter for PCM frequency
• TTL and CMOS compatibility
• Output active low
• Improved shielding against electrical field disturbance
• Suitable burst length .6 cycles/burst

Special Features
• Small size package
• Enhanced immunity against all kinds of disturbance light
• No occurrence of disturbance pulses at the output
• Short settling time after power on (<200_s)

15.18. PI5V330

15.18.1. General Description


The PI5V330 is well suited for video applications when switching composite or RGB analogue. A picture-in-
picture application will be described in this brief. The pixel-rate creates video overlays so two or more pictures
can be viewed at the same time. An inexpensive NTSC titler can be implemented by superimposing the output
of a character generator on a standard composite video background.

26
15.19. SDA55XX (SDA5550)

15.19.1. General description


The SDA55XX is a single chip teletext decoder for decoding World System Teletext data as well as Video
Programming System (VPS), Program Delivery Control (PDC), and Wide Screen Signalling (WSS) data used for
PAL plus transmissions (Line 23). The device also supports Closed caption acquisition and decoding. The
device provides an integrated general-purpose, fully 8051-compatible Microcontroller with television specific
hardware features. Microcontroller has been enhanced to provide powerful features such as memory banking,
data pointers, and additional interrupts etc. The on-chip display unit for displaying Level 1.5 teletext data can
also be used for customer defined on screen displays. Internal XRAM consists of up to16 Kbytes. Device has an
internal ROM of up to 128 KBytes. ROMless versions can access up to 1 MByte of external RAM and ROM. The
SDA 55XX supports a wide range of standards including PAL, NTSC and contains a digital slicer for VPS, WSS,
PDC, TTX and Closed Caption, an accelerating acquisition hardware module, a display generator for Level 1.5
TTX data and powerful On screen Display capabilities based on parallel attributes, and Pixel oriented characters
(DRCS).
The 8-bit Microcontroller runs at 360 ns. cycle time (min.). Controller with dedicated hardware does most of the
internal TTX acquisition processing, transfers data to/from external memory interface and receives/ transmits
data via I2C-firmware user-interface. The slicer combined with dedicated hardware stores TTX data in a VBI
buffer of 1 Kilobyte. The Microcontroller firmware performs all the acquisition tasks (hamming and parity-checks,
page search and evaluation of header control bits) once per field. Additionally, the firmware can provide high-
end Teletext features like Packet-26-handling, FLOF, TOP and list-pages. The interface to user software is
optimized for minimal overhead. SDA 55XX is realized in 0.25 micron technology with 2.5 V supply voltage and
3.3 V I/O (TTL compatible). The software and hardware development environment (TEAM) is available to
simplify and speed up the development of the software and On Screen Display. TEAM stands for TVT Expert
Application Maker. It improves the TV controller software quality in following aspects:
– Shorter time to market
– Re-usability
– Target independent development
– Verification and validation before targeting
– General test concept
– Graphical interface design requiring minimum programming and controller know how.
– Modular and open tool chain, configurable by customer.

15.20. Sil 9993

15.20.1. General Description


The SiI 9993 is the first generation of PanelLink receivers that are designed for the HDMI 1.0 (High Definition Multimedia
Interface) specification. DTVs, plasma displays, LCD TVs and projectors can now provide the purest level of protected
digital audio/video over a simple, low cost cable. Backwards compatibility with DVI 1.0 allows HDMI systems to connect
to any DVI 1.0 host (DVD players, HD set top boxes, D-VHS players and receivers, PC). The SiI 9993 incorporates a
flexible audio and video interface. The receiver can connect to RGB input and output YCbCr using an integrated color
space converter. This allows full backward compatibility to DVI, and interfaces to all major video processors. A S/PDIF
port can output PCM encoded data as well as Dolby Digital, DTS and all other formats capable of being sent over S/PDIF.
A 2-channel I2S port outputs data converted from S/PDIF. The SiI 9993 comes pre-programmed with HDCP keys, greatly
simplifying the manufacturing process, lowering costs, all the while providing the highest level of HDCP key security.
Silicon Image’s PanelLink receivers use the latest generation of PanelLink TMDS core technology. These PanelLink cores
pass all HDMI compliancy tests.

15.20.2. Features
• HDMI 1.0 and DVI 1.0 compliant receiver
• Integrated PanelLink core supports DTV resolutions (480i/576i/480p/576p/720p/1080i)
• Digital video interface supports video processors:
o 24-bit RGB 4:4:4
o 24-bit YCbCr 4:4:4
o 16/20/24-bit YCbCr 4:2:2
o 8/10/12-bit YCbCr 4:2:2 embedded syncs
• Analog RGB and YPbPr output:
o 10-bit DAC
o Separate or Composite Syncs (Sync on G)

27
• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC 60958
and IEC 61937.
• Programmable I2S interface for connection to low-cost audio DACs.
• Integrated HDCP decryption engine for receiving protected audio and video content
• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
• Programmable registers via slave I2C interface
• 3.3V operation in 100-pin TQFP package
• Flexible power management

15.21. SN74CB3Q3305

15.21.1. General Description


The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.

15.21.2. Features
• High-Bandwidth Data Path (Up To 500 MHz)
• 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
• Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Ÿ Typical)
• Rail-to-Rail Switching on Data I/O Ports
í 0- to 5-V Switching With 3.3-V VCC
í 0- to 3.3-V Switching With 2.5-V VCC
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5 pF Typical)
• Fast Switching Frequency (fOE = 20 MHz Max)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (ICC = 0.25 mA Typical)
• VCC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
í 2000-V Human-Body Model (A114-B, Class II)
í 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-
Distortion Signal Gating

15.21.3. Pin Connections

15.22. ST24LC21

15.22.1. Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This
device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered, the device is
in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The
device will switch to the I2C bidirectional mode upon the falling edge of the signal applied on SCL pin. The

28
ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only mode (except when the power
supply is removed). The device operates with a power supply value as low as 2.5V. Both Plastic Dual-in-Line
and Plastic Small Outline packages are available.

15.22.2. Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V to 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances

15.22.3. Pin connections

DIP Pin connections CO Pin connections

NC: Not connected

Signal names

SDA Serial data Address Input/Output


2
SCL Serial Clock (I C mode)
Vcc Supply voltage
Vss Ground
VCLK Clock transmit only mode

15.23. LM2576

15.23.1. General Description


The LM2576 series of regulators are monolithic integrated circuits ideally suited for easy and convenient design of a step–
down switching regulator (buck converter). All circuits of this series are capable of driving a 3.0 A load with excellent line
and load regulation.
These devices are available in fixed output voltages of 3.3 V, 5.0 V, 12 V, 15 V, and an adjustable output
version. These regulators were designed to minimize the number of external components to simplify the power
supply design. Standard series of inductors optimized for use with the LM2576 are offered by several different
inductor manufacturers.
Since the LM2576 converter is a switch–mode power supply, its efficiency is significantly higher in comparison
with popular three–terminal linear regulators, especially with higher input voltages. In many cases, the power
dissipated is so low that no heatsink is required or its size could be reduced dramatically.
A standard series of inductors optimized for use with the LM2576 are available from several different
manufacturers. This feature greatly simplifies the design of switch–mode power supplies.
The LM2576 features include a guaranteed ±4% tolerance on output voltage within specified input voltages and
output load conditions, and ±10% on the oscillator frequency (±2% over 0°C to 125°C). External shutdown is
included, featuring 80 mA (typical) standby current. The output switch includes cycle–by–cycle current limiting,
as well as thermal shutdown for full protection under fault conditions.

15.23.2. Features
• 3.3 V, 5.0 V, 12 V, 15 V, and Adjustable Output Versions

29
• Adjustable Version Output Voltage Range, 1.23 to 37 V ±4% Maximum Over Line and Load Conditions
• Guaranteed 3.0 A Output Current
• Wide Input Voltage Range
• Requires Only 4 External Components
• 52 kHz Fixed Frequency Internal Oscillator
• TTL Shutdown Capability, Low Power Standby Mode
• High Efficiency
• Uses Readily Available Standard Inductors
• Thermal Shutdown and Current Limit Protection
• Moisture Sensitivity Level (MSL) Equals 1

15.23.3. Pin description

15.24. MC34063

15.24.1. Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC–to–DC converters.
These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with
an active current limit circuit, driver and high current output switch. This series was specifically designed to be
incorporated in Step–Down and Step–Up and Voltage–Inverting applications with a minimum number of external
components.

15.24.2. Features
• Operation from 3.0 V to 40 V Input
• Low Standby Current
• Current Limiting
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation to 100 kHz
• Precision 2% Reference

15.24.3. Pin connections

30
15.25. TDA1308

15.25.1. General Description


The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic
package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable
digital audio applications.

15.25.2. Features
• Wide temperature range
• No switch ON/OFF clicks
• Excellent power supply ripple rejection
• Low power consumption
• Short-circuit resistant
• High performance
• high signal-to-noise ratio
• High slew rate
• Low distortion
• Large output voltage swing.

15.25.3. Pinning

SYMBOL PIN DESCRIPTION PIN VALUE


OUTA 1 Output A (Voltage swing) Min : 0.75V, Max : 4.25V
INA(neg) 2 Inverting input A Vo(clip) : Min : 1400mVrms
INA(pos) 3 Non-inverting input A 2.5V
VSS 4 Negative supply 0V
INB(pos) 5 Non-inverting input B 2.5V
INB(neg) 6 Inverting input B Vo(clip) : Min : 1400mVrms
OUTB 7 Output B (Voltage swing) Min : 0.75V, Max : 4.25V
VDD 8 Positive supply 5V, Min : 3.0V, Max : 7.0V

15.26. TDA9886

15.26.1. General Description


The TDA9886 is an alignment-free single standard (without positive modulation) vision and sound IF signal PLL.

15.26.2. Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation, good
intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all negative and
positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as crystal
oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative modulated
signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analogue converter; AFC bits via
I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single
reference QSS mode and in intercarrier mode, switchable via I2C-bus

31
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).

15.26.3. Pinning

SYMBOL PIN DESCRIPTION


VIF1 1 VIF differential input 1
VIF2 2 VIF differential input 2
OP1 3 output 1 (open-collector)
FMPLL 4 FM-PLL for loop filter
DEEM 5 de-emphasis output for capacitor
AFD 6 AF decoupling input for capacitor
DGND 7 digital ground
AUD 8 audio output
TOP 9 tuner AGC TakeOver Point (TOP)
SDA 10 I2C-bus data input/output
SCL 11 I2C-bus clock input
SIOMA 12 sound intercarrier output and MAD select
n.c. 13 not connected
TAGC 14 tuner AGC output
REF 15 4 MHz crystal or reference input
VAGC 16 VIF-AGC for capacitor; note 1
CVBS 17 video output
AGND 18 analog ground
VPLL 19 VIF-PLL for loop filter
VP 20 supply voltage (+5 V)
AFC 21 AFC output
OP2 22 output 2 (open-collector)
SIF1 23 SIF differential input 1
SIF2 24 SIF differential input 2

15.27. TPA3004D2

15.27.1. General Description


The TPA3004D2 is a 12-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo speakers. The
TPA3004D2 can drive stereo speakers as low as 4 Ÿ. The high efficiency of the TPA3004D2 eliminates the need for
external heatsinks when playing music.
Stereo speaker volume is controlled with a dc voltage applied to the volume control terminal offering a range of gain from –
40 dB to 36 dB. Line outputs, for driving external headphone amplifier inputs, are also dc voltage controlled with a range
of gain from –56 dB to 20 dB.
An integrated 5-V regulated supply is provided for powering an external headphone amplifier.

15.27.2. Features
• 12-W/Ch Into an 8-Ÿ Load From 15-V Supply
• Efficient, Class-D Operation Eliminates Heatsinks and Reduces Power Supply Requirements
• 32-Step DC Volume Control From í40 dB to 36 dB
• Line Outputs For External Headphone Amplifier With Volume Control
• Regulated 5-V Supply Output for Powering TPA6110A2
• Space-Saving, Thermally-Enhanced PowerPADTM Packaging
• Thermal and Short-Circuit Protection.

32
15.27.3. Pinning

33
15.28.

15.29. µPA672T

15.29.1. General Description


The μPA672T is a super-mini-mold device provided with two MOS FET elements. It achieves high-density
mounting and saves mounting costs.

15.29.2. Features
• Two MOS FET circuits in package the same size as SC-70
• Automatic mounting supported

15.29.3. Pin Connection

15.30. VPC3230D

15.30.1. General Description


The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and
100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x)
and/or it can be used with 3rd-party products.
The main features of the VPC 323xD are
• high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking
• multi-standard colour decoder PAL/NTSC/SECAM including all substandards
• four CVBS, one S-VHS input, one CVBS output
• two RGB/YCr Cb component inputs, one Fast Blank (FB) input
• integrated high-quality A/D converters and associated clamp and AGC circuits
• multi-standard sync processing
• linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling ‘Panorama-vision’
• PAL+ preprocessing
• line-locked clock, data and sync, or 656-output interface
• peaking, contrast, brightness, color saturation and tint for RGB/ YC r C b and CVBS/ S-VHS
• high-quality soft mixer controlled by Fast Blank
• PIP processing for four picture sizes (1/4, 1/9, 1/16 or 1/36 of normal size) with 8-bit resolution
• 15 predefined PIP display configurations and expert mode (fully programmable)
• control interface for external field memory
• I2C-bus interface

• one 20.25-MHz crystal, few external components

• 80-pin PQFP package

15.30.2. Pin Connections and Short Descriptions


NC = not connected
LV = if not used, leave vacant
X = obligatory; connect as described in circuit diagram
SUPPLYA = 4.75...5.25 V, SUPPLYD = 3.15...3.45 V

34
Pin No. Pin Name Type Connection Short Description
PQFP (if not used)
80-pin
1 B1/CB1IN IN VREF Blue1/Cb1 Analog Component Input
2 G1/Y1IN IN VREF Green1/Y1 Analog Component Input
3 R1/CR1IN IN VREF Read1/Cr1 Analog Component Input
4 B2/CB2IN IN VREF Blue2/Cb2 Analog Component Input
5 G2/Y2IN IN VREF Green2/Y2 Analog Component Input
6 R2/CR2IN IN VREF Read2/Cr2 Analog Component Input
7 ASGF X Analog Shield GNDF
8 FFRSTWIN IN LV or GNDD FIFO Reset Write Input
9 VSUPCAP OUT X Digital Decoupling Circuitry Supply Voltage
10 VSUPD SUPPLYD X Supply Voltage, Digital Circuitry
11 GNDD SUPPLYD X Ground, Digital Circuitry
12 GNDCAP OUT X Digital Decoupling Circuitry GND
2
13 SCL IN/OUT X I C Bus Clock
2
14 SDA IN/OUT X I C Bus Data
15 RESQ IN X Reset Input, Active Low
16 TEST IN GNDD Test Pin, connect to GNDD
17 VGAV IN GNDD VGAV Input
18 YCOEQ IN GNDD Y/C Output Enable Input, Active Low
19 FFIE OUT LV FIFO Input Enable
20 FFWE OUT LV FIFO Write Enable
21 FFRSTW OUT LV FIFO Reset Write/Read
22 FFRE OUT LV FIFO Read Enable
23 FFOE OUT LV FIFO Output Enable
24 CLK20 IN/OUT LV Main Clock output 20.25 MHz
25 GNDPA OUT X Pad Decoupling Circuitry GND
26 VSUPPA OUT X Pad Decoupling Circuitry Supply Voltage
27 LLC2 OUT LV Double Clock Output
28 LLC1 IN/OUT LV Clock Output
29 VSUPLLC SUPPLYD X Supply Voltage, LLC Circuitry
30 GNDLLC SUPPLYD X Ground, LLC Circuitry
31 Y7 OUT GNDY Picture Bus Luma (MSB)
32 Y6 OUT GNDY Picture Bus Luma
33 Y5 OUT GNDY Picture Bus Luma
34 Y4 OUT GNDY Picture Bus Luma
35 GNDY SUPPLYD X Ground, Luma Output Circuitry
36 VSUPY SUPPLYD X Supply Voltage, Luma Output Circuitry
37 Y3 OUT GNDY Picture Bus Luma
38 Y2 OUT GNDY Picture Bus Luma
39 Y1 OUT GNDY Picture Bus Luma
40 Y0 OUT GNDY Picture Bus Luma (LSB)
41 C7 OUT GNDC Picture Bus Chroma (MSB)
42 C6 OUT GNDC Picture Bus Chroma
43 C5 OUT GNDC Picture Bus Chroma
44 C4 OUT GNDC Picture Bus Chroma
45 VSUPC SUPPLYD X Supply Voltage, Chroma Output Circuitry
46 GNDC SUPPLYD X Ground, Chroma Output Circuitry
47 C3 OUT GNDC Picture Bus Chroma
48 C2 OUT GNDC Picture Bus Chroma
49 C1 OUT GNDC Picture Bus Chroma
50 C0 OUT GNDC Picture Bus Chroma (LSB)
51 GNDSY SUPPLYD X Ground Sync Pad Circuitry
52 VSUPSY SUPPLYD X Supply Voltage, Sync Pad Circuitry
53 INTLC OUT LV Interlace Output
54 AVO OUT LV Active Video Output
55 FSY/HC/HSYA OUT LV Front Sync/ Horizontal Clamp Pulse/Front-End
Horizontal Sync Output
56 MSY/HS IN/OUT LV Main Sync/Horizontal Sync Pulse
57 VS OUT LV Vertical Sync Pulse
58 FPDAT/VSYA IN/OUT LV Front End/Back-End Data/Front-End Vertical Sync
Output
59 VSTBYY SUPPLYA X Standby Supply Voltage
60 CLK5 OUT LV CCU 5 MHz Clock Output

35
61 NC - LV or GNDD Not Connected
62 XTAL1 IN X Analog Crystal Input
63 XTAL2 OUT X Analog Crystal Output
64 ASGF X Analog Shield GNDF
65 GNDF SUPPLYA X Ground, Analog Front-End
66 VRT OUTPUT X Reference Voltage Top, Analog
67 I2CSEL IN X I2C Bus Address Select
68 ISGND SUPPLYA X Signal Ground for Analog Input, connect to GNDF
69 VSUPF SUPPLYA X Supply Voltage, Analog Front-End
70 VOUT OUT LV Analog Video Output
71 CIN IN LV Chroma/Analog Video 5 Input
72 VIN1 IN VRT Video 1 Analog Input
73 VIN2 IN VRT Video 2 Analog Input
74 VIN3 IN VRT Video 3 Analog Input
75 VIN4 IN VRT Video 4 Analog Input
76 VSUPAI SUPPLYA X Supply Voltage, Analog Component Inputs Front-End
77 GNDAI SUPPLYA X Ground, Analog Component Inputs Front-End
78 VREF OUTPUT X Reference Voltage Top, Analog Component Inputs
Front-End
79 FB1IN IN VREF Fast Blank Input
80 AISGND SUPPLYA X Signal Ground for Analog Component Inputs, connect
to GNDAI

15.31. MAD4868A

15.31.1. General Description

The Micronas Audio Delay IC MAD 4868A acts as a delay line for TV audio and consumer audio applications.
The IC is designed for synchronizing audio and video signals ensuring "Lip Sync" by delaying the audio signal
with the same amount of time as the video signal is delayed in a TV's video processing.

For TV designs, independent signals for loudspeakers, headphones, and line-out or S/PDIF out must be pro-
vided, resulting in the need to delay six independent audio channels.

15.31.2. Features
x 32 k audio samples RAM:
x Total delay time of 680 ms at 48 kHz or 1020 ms at 32 kHz sampling rate
- 32/18-bit word width:
x 32-bit High-Resolution mode or 18-bit Standard mode
x Sampling rates from 32 kHz to 48 kHz for
serial 8-channel mode are supported
x Sampling rates from 4 kHz to 192 kHz for
parallel 2-channel mode are supported
x Memory allocation:
x MAD 4868A's memory can be allocated for 1... 8 audio channels. Delay time can be programmed for
each channel individually.

15.31.3. Interfaces
x 8-channel Micronas I2S input and output:
x In combination with Micronas ICs (serial mode) (e.g. MSP 44/46xyK, MAS 35xyH), eight audio channels
can be routed through MAD 4868A by using four lines only.
x 4x2-channel standard I2S inputs and outputs (paral
lel mode) allow routing eight audio channels with
sampling rates of 4... 192 kHz through MAD 4868A
x I2C control for delay time programming
x Address select to set one out of two available I2C addresses.

36
15.31.4. Pinning

15.32. SVP-EX 59B


General Description
To improve the video quality of the PAL CVBS and HD video input, the all layer changed EX59 improve video sharpness
function in HD channel and enhance the 3D PAL quality compared to EX52 Rev. D chips.

16. SERVICE MENU SETTINGS


To enter the service menu, first enter the MENU by pressing “ ” button and then press the digits 4, 7, 2 and 5
respectively.

37
Service Menu Items

16.1. Picture Adjust


x Source => All possible sources given with the chasis as a list.
x Mode => Three items as a list; NATURAL, DYNAMIC, CINEMA
x Colour Temp => Three items as a list; COOL, NORMAL, WARM
x Contrast => Slider Bar. Changing value between 0 to 63.
x Brightness => Slider Bar. Changing value between 0 to 63.
x Sharpness => Slider Bar. Changing value between 0 to 16.
x Colour => Slider Bar. Changing value between 0 to 99.
x R => Slider Bar. Changing value between 0 to 100.
x G => Slider Bar. Changing value between 0 to 100.
x B => Slider Bar. Changing value between 0 to 100.
In this menu preset values for each Mode (Contrast, Brightness, Sharpness, Colour values for each Mode-
NATURAL, DYNAMIC, CINEMA) and for each Colour Temp. (R, G, B values for each Colour Temp- COOL,
NORMAL, WARM) are determined for each source.

16.2. SOUND1
x Menu Subwoofer => If ON, Subwoofer option is available in TV set, and the item is visible
in sound menu, else Subwoofer is not available.
x Subwoofer Level (dB) => This value is gain value of Subwoofer output in dB. -30...12
x Subwoofer Corner Freq. (x10Hz) => Last low frequency value that is amplified. 5...40
x Menu Dolby Prologic => No functionality now.
x Menu Equalizer => If ON, visible in sound menu, else invisible.
x Menu Lineout => No functionality now.
x Menu Headphone => If ON, visible in sound menu, else invisible.
x Menu Hyper Sound => If ON, visible in sound menu, else invisible.
x Menu Wide Sound => If ON, visible in sound menu, else invisible.
x Menu Dynamic Bass => If ON, visible in sound menu, else invisible.
x Menu Virtual Dolby => If ON, visible in sound menu, else invisible.
x Carrier Mute => If ON, in the absence of an FM carrier the output is muted, else not.
x Virtual Dolby Text => Active if VIRTUAL DOLBY is ON. According to the selection; seen in
sound menu as 3D PANORAMA or VIRTUAL DOLBY.

16.3. SOUND 2
x AVL => AVL is controlled from this menu by service user. ON/OFF
x Menu AVL => If ON, AVL item is visible in sound menu, and AVL can be controlled from
sound menu by normal user, else AVL is invisible to normal user.
x FM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127
x NICAM PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for the related standard. 0...127
x SCART PRESCALE AVL ON => If AVL ON, set value in this item is used as prescale value
for scart outputs. 0...127
x SCART VOLUME AVL ON => If AVL ON, set value in this item is used as volume value for
scart1 and scart2. 0...127
x FM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127
x NICAM PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for the related standard. 0...127
x SCART PRESCALE AVL OFF => If AVL OFF, set value in this item is used as prescale value
for scart outputs. 0...127
x SCART VOLOUME AVL OFF => If AVL OFF, set value in this item is used as volume value for
scart1 and scart2. 0...127

16.4. Options
x Screen Saver =>
x FIRST APS => If ON, first APS menu is opened when the TV opened with the
factory default settings.

38
x APS VOLUME => After First APS function finishes, the volume of the TV is that value.
x AGC => Tuner AGC value.
x Factory Reset => OK to activate. When OK pressed on this item, factory defaults
loaded.
x Enter Flash Mode =>
TV Norm
x BG => If ON, supported, else not supported
x DK => If ON, supported, else not supported.
x I => If ON, supported, else not supported.
x L => If ON, supported, else not supported.
x LP => If ON, supported, else not supported.
x M => If ON, supported, else not supported.
Features
x PIP/PAP => If ON, PIP/PAP available else not.
x Blue Background => If ON, Blue Background is visible in Features Menu else not.
x Menu Transparency => If ON, Menu Transparency is visible in Features Menu else not.
x Menu Timeout => If ON, Menu Timeout is visible in Features Menu else not.
x Backlight => If ON, Backlight is visible in Features Menu else not.
x Single Tuner =>
Teletext
x Teletext Language => Teletext Language may be controlled from this menu by service
user.
x Menu Teletext Language => If ON, Teletext Language item is visible in Features Menu, and
Teletext Language can be controlled from Features Menu by normal user, else Teletext Language is
invisible to normal user.
Source
x TV
x SC1
x SC2
x SC2 SVHS
x SC3
x SC3 SVHS
x YPBPR
x FAV
x SVHS
x HDMI
x PC
This menu is related with the options of the chassis. These items may be ON or OFF. If ON, the source is
available in TV set, and the item is visible in source menu, else the source may be available but invisible to user.

17. IC DESCRIPTIONS (FOR DIGITAL)


STI5518 24C32
MAX232_SMD STV0360
74HCU04 MAX809
TSH22 TDCC2345TV39A
CS4334 STV0700
AMIC A43L2616
MX29LV160T

17.1. STI5518
17.1.1. General Description
The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top boxes. It
integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport demultiplexing and descrambling,
modules for MPEG-2 video and audio decoding with 3D-surround and MP3 support, advanced display and graphics
features, a digital video encoder and all of the system peripherals required in a typical low-cost interactive receiver.

39
To cover the needs of DVD-capable set-top boxes, STi5518 integration options include a CSS decryption block, a Dolby
Digital audio decoder and Macrovision copy protection.
An ATAPI interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the STi5518
is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and time-shifting.
The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy migration from the
previous generation.
The high level of integration in a single PQFP-208 package makes the STi5518 ideally suited for low-cost, high-volume
set-top box applications.

17.2. MAX232_SMD
17.2.1. General Description
The MAX220–MAX249 family of line drivers/receivers is intended for all EIA/TIA-232E and V.28/V.24 communications
interfaces, particularly applications where ±12V is not available.
These parts are especially useful in battery-powered systems, since their low-power shutdown mode reduces power
dissipation to less than 5μW. The MAX225, MAX233, MAX235, and MAX245/MAX246/MAX247 use no external
components and are recommended for applications where printed circuit board space is critical.

17.2.2. Features
x Operate from Single +5V Power Supply (+5V and +12V—MAX231/MAX239)
x Low-Power Receive Mode in Shutdown (MAX223/MAX242)
x Meet All EIA/TIA-232E and V.28 Specifications
x Multiple Drivers and Receivers
x 3-State Driver and Receiver Outputs
x Open-Line Detection (MAX243)

17.3. 74HCU04
17.3.1. General Description
The M54/74HCU04 is a high speed CMOS HEX INVERTER (SINGLE STAGE) fabricated in silicon gate C2MOS
technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption.
As the internal circuit is composed of a single stage inverter, it can be used in crystal oscillator.
All inputs are equipped with circuits against static discharge and transient excess voltage.

17.3.2. Pin Description

40
17.4. TSH22
17.4.1. General Description
The TSH22 is a dual bipolar operational amplifier offering a single supply operation from 3V to 30V with very good
performances: medium speed (25MHz), unity gain stability and low noise.
The TSH 22 is therefore an enhanced replacement of standard dual operational amplifiers.

17.4.2. Pin Connections

17.5. CS4334
17.5.1. General Description
The CS4334 family members are complete, stereo digital-to-analogue output systems including interpolation, 1-bit D/A
conversion and output analogue filtering in an 8-pin package. The CS4334/5/6/7/8/9 support all major audio data interface
formats and the individual devices differ only in the supported interface format.
The CS4334 family is based on delta-sigma modulation, where the modulator output controls the reference voltage input to
an ultra-linear analogue low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and
100 kHz simply by changing the master clock frequency.
The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power supply, and requires minimal
support circuitry. These features are ideal for portable CD players and other portable playback systems.

17.5.2. Features
x Complete Stereo DAC System: Interpolation, D/A, Output Analogue Filtering
x 24-Bit Conversion
x 96 dB Dynamic Range
x Low Distortion
x Low Clock Jitter Sensitivity
x Single 5 V Power Supply
x Filtered Line Level Outputs
x On-Chip Digital De-emphasis
x Soft Ramp to Quiescent Output Voltage
x Functionally Compatible with CS4330/31/33

17.6. AMIC A43L2616


17.6.1. General Description
The A43L2616-PH is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576
words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows
precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of
operating frequencies, programmable latencies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.

17.6.2. Features
x JEDEC standard 3.3V power supply
x LVTTL compatible with multiplexed address
x Four banks / Pulse RAS
x MRS cycle with address key programs

41
x All inputs are sampled at the positive going edge of the system clock
x Clock Frequency: 166MHz @ CL=3
143MHz @ CL=3
x Burst Read Single-bit Write operation
x DQM for masking
x Auto & self refresh
x 64ms refresh period (4K cycle)
x 54 Pin TSOP (II)

17.6.3. Pin Description

42
17.7. MX29LV160T
17.7.1. General Description
The MX29LV160T/B & MX29LV160AT/AB is a 16-megabit Flash memory organized as 2M bytes of 8 bits or 1M words
of 16 bits. MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access
memory. The MX29LV160T/B & MX29LV160AT/AB is packaged in 44-pin SOP, 48-pin TSOP and 48-ball CSP. It is
designed to be reprogrammed and erased in system or in standard EPROM programmers.
The standard MX29LV160T/B & MX29LV160AT/AB offers access time as fast as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the MX29LV160T/B &MX29LV160AT/AB has separate
chip enable (CE) and output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The
MX29LV160T/B & MX29LV160AT/AB uses a command register to manage this functionality. The command register
allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is
designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and program operations produces reliable cycling. The
MX29LV160T/B & MX29LV160AT/AB uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is
proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.

17.7.2. Features
x Extended single - supply voltage range 2.7V to 3.6V
x 2,097,152 x 8/1,048,576 x 16 switchable
x Single power supply operation
x Fast access time: 70/90ns
x Low power consumption
x Command register architecture
x Auto Erase (chip & sector) and Auto Program
x Erase Suspend/Erase Resume
x Status Reply
x Ready/Busy pin (RY/BY)
x Sector protection
x CFI (Common Flash Interface) compliant (for MX29LV160AT/AB)
x 100,000 minimum erase/program cycles
x Latch-up protected to 100mA from -1V to VCC+1V
x Boot Sector Architecture
x Low VCC write inhibit is equal to or less than 1.4V
x Compatibility with JEDEC standard

17.7.3. Pin Description

43
17.8. 24C32
17.8.1. General Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only
memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to
8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial
applications where low power and low voltage operation are essential. The AT24C32/64 is available in space
saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP (AT24C64) packages and is
accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V
(1.8V to 5.5V) versions.

17.8.2. Features
x Low-Voltage and Standard-Voltage Operation
x Low-Power Devices (ISB= 2 μA at 5.5V) Available
x Internally Organized 4096 x 8, 8192 x 8
x 2-Wire Serial Interface
x Schmitt Trigger, Filtered Inputs for Noise Suppression
x Bidirectional Data Transfer Protocol
x 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
x Write Protect Pin for Hardware Data Protection
x 32-Byte Page Write Mode (Partial Page Writes Allowed)
x Self-Timed Write Cycle (10 ms max)
x High Reliability
x Automotive Grade and Extended Temperature Devices Available
x 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages

17.8.3. Pin Description

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wire-ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left
not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices
may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).
When the pins are not hardwired, the default A2, A1, and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied
high to VCC, all write operations to the upper quadrant (8/16K bits) of memory are inhibited. If left unconnected, WP is
internally pulled down to GND.

44
17.9. STV0360
17.9.1. General Description
The STV0360 is a single-chip COFDM (coded orthogonal frequency division multiplex) demodulator that performs IF to
MPEG-2 block processing of OFDM carriers. It is intended for digital terrestrial receivers for compressed video, sound and
data services.
The chip implements all the functions from the tuner IF output up to the MPEG-2 transport stream input.
The STV0360 is fully compliant with the DVB-T specification (ETS 300 744) and handles 2K/8K modes.
The STV0360 integrates an A/D converter that delivers the required performance to handle up to 64 QAM carriers in a
direct IF sampling architecture, thus eliminating the need for an external down-converter. The chip also integrates an
internal programmable gain amplifier (PGA) to compensate for SAW filter level degradation, thus eliminating the need for
external IF amplifiers. A 10-bit ADC, intended for RF signal strength indication, eliminates the need for external
components when using wide-band AGC tuners.
In addition to all the demodulation and FEC (forward error correction) functions required for recovery of the QAM
modulated bit streams with very low BER, it also includes several features that give easy and immediate access to various
quality monitoring parameters or lock status. The STV0360 also provides output such as delayed AGC or noise-free I²C bus
dedicated to tuner control, which facilitates the design of high quality integrated receiver decoders.
The STV0360 outputs error-corrected MPEG-2 transport streams and complies with the DVB common interface format,
with programmable data clock frequency. It also interfaces seamlessly with the packet de-multiplexers embedded in the
STi55xx Omega family of single-chip decoders.

17.9.2. Features
x Decodes DVB-T (ETS300744) and NorDig II
x TPS decoded or automatic FEC mode detection
x Embeds PGA for IF level adaptation
x Generates system clock on-chip from 20 to 27-MHz crystal quartz
x Four I²C addresses available
x Low power consumption (< 500 mW)
x Small footprint: TQFP64 (10 X 10 mm)
x 1.8 V operation, CMOS technology

17.9.3. Pin Description

45
46
17.10. MAX809
17.10.1. General Description
The MAX803/MAX809/MAX810 are microprocessor (μP) supervisory circuits used to monitor the power supplies in μP
and digital systems. They provide excellent circuit reliability and low cost by eliminating external components and
adjustments when used with +5V, +3.3V,+3.0V, or +2.5V powered circuits. These circuits perform a single function: they
assert a reset signal whenever the VCC supply voltage declines below a preset threshold, keeping it asserted for at least
140ms after VCC has risen above the reset threshold. Reset thresholds suitable for operation with a variety of supply
voltages are available. The MAX803 has an open-drain output stage, while the MAX809/MAX810 have push-pull outputs.
The MAX803’s open-drain RESET output requires a pull-up resistor that can be connected to a voltage higher than VCC.
The MAX803/MAX809 have an active-low RESET output, while the MAX810 has an active-high RESET output. The
reset comparator is designed to ignore fast transients on VCC, and the outputs are guaranteed to be in the correct logic state
for VCC down to 1V. Low supply current makes the MAX803/MAX809/MAX810 ideal for use in portable equipment. The
MAX803 is available in a 3-pin SC70 package, and the MAX809/MAX810 are available in 3-pin SC70 or SOT23
packages.

17.10.2. Features
x 1 Precision M onitorin g of +2.5V, +3V,.3V,
+3 and +5V Power-Su ppl y Voltages
x Fully Specifie d Over Tem peratu re
x Available in T hree Output Config uratio ns
Open-Drain RESET Output (MAX803)
Pus h-Pull RESET Output (MAX809)
Pus h-Pull RESET Output (MAX810)
x 140ms min Pow er-On Reset Pulse Wid th
x 12μA Supply Current
x Guarantee d Reset Valid to VCC= +1V
x Powe r Suppl y Transi ent Immunity
x No External Comp one nts
x 3-Pin SC7 0 and SOT23 Pa ckage s

47
17.10.3. Pin Description

17.11. TDCC2345TV39A
17.11.1. General Description
x Receiving System : Designed to cover all bands in VHF and UHF including digital terrestrial channels for DVB-T
system.
x Receiving Channel : 47 MHz ~ 862 MHz
x Intermediate Frequency : Digital (center) 36.125 MHz
x Input Impedance : 75Ÿ, Unbalanced.
x IF Output Impedance : 75Ÿ, Balanced.
x Loop through RF output Impedance : 75Ÿ, Unbalanced.
x Band Change-Over System : PLL system
x Tuning System : PLL system
x Pin-out for the port to control the switchable saw

17.11.2. Pin Description

48
17.12. STV0700
17.12.1. General description
The STV0700 controller contributes to offer an optimized, homogeneous and complete solution for digital TV receiver and
Set Top Box manufacturers that want to quickly implement the Common Interface. The STV0700 includes the necessary
I/Os to interface to the MPEG Transport stream generated by the receiver demodulator and daisy chain it through two
independent Common Interface modules and back to the demultiplexer. The STV0700 interfaces with major digital TV
receiver microprocessors. An I2C bus is used for initialization and module selection, while a Universal Control Signal
Generator (UCSG) maps CPU control bus into Command Interface control signals. To minimize pin count, host address and
data buses transit through external buffers that are driven by the STV0700. The STV0700 includes a memory mode that
allows the use any of the Common Interface slots to read and write an 8-bit PC Card Memory card. This feature gives the
receiver memory extension capability for software upgrade or better performance.

17.12.2. Features
x Module Interface
x Host microprocessor Interface
x 2 independent module capability
x Universal Control Signal Generator(UCSG)
x Common Interface Standard compliant o PC Card control signals generation
o DVB_CI (CENELEC EN-50221) o Supports PowerPC, ARM, ST20,68xxx, TMS,
o NRSS-B (SCTE IS-679 Part B)
LSI 64008, TC81220F & IDTR3041
o DAVIC v1.2 (CA0 interface)
x I2C port
x Memory PCMCIA compliance (R2)
o STV0700 Set-up
o 8-bit data access
o Slot selection
o 26-bit address Memory Card
o Cascade mode management (up to 4STV0700)
x Attribute Memory access (CIS, Tupple)
x Chip Select bank and Interrupt facilities
x High speed capability
x 3.3V (5V tolerant) I/O buffers
o Up to 20Mbits/s on Command Interface
x Digital Video Stream Interface
o Up to 100Mbits/s on Transport Stream
x Polling and Interrupt modes x MPEG II Transport Stream compliant
x Hot Insertion (Automatic and Reset VCC handling) (serial/parallel configurable interface)
x 3.3V (5V tolerant) I/O buffers x 3.3V (5V tolerant) I/O buffer for direct interface
x IEEE 1149.1 Boundary Scan Compliant with FEC and DEMUX ICs
Test Access Port

17.12.3. Pin Description

49
50
51
52
18. APPENDIX A

18.1. EXPLODED VIEW


MAIN BOARD ASSEMBLY
43
V4

44 AV BOARD ASSEMBLY
V1 V4 48

V4 V4

V1

V2

V4

V1
V1

39
V2

V2 V1

V1 V3
V2

V1 V3

V2
V1

V3
V3
V0
V5 V1
23
35 V2
V2 V1
V1 V3
V8
V1
V6 V2
V3
V7
34
33 V5
V2

V9

V1

LED BOARD
ASSEMBLY
V4

PANEL CONNECTION SCREWS

SM012 ASSEMBLY DIAGRAM (EXPLODED VIEW)


53
19. APPENDIX B

19.1. BLOCK DIAGRAM

MAIN BOARD
AUDIO AMP BOARD
AUDIO MAIN_L, MAIN_R
DECODING
MSP3411G AUDIO
MICRONAS AMPLIFIER
D-CLASS
AUDIO / VIDEO / GRAPHICS IN / OUT

IDTV, SVHS,MMC(RGB), PC IN

SVP-EX59
LVDS OUT

VPC3230D 8-BIT YUV


VIDEO PROCESSOR
PIP PICTURE
MICRONAS SDA5550
MCU
MICRONAS
24-BIT RGB
HDMI DECODER
SIL9993

PSU

SM012 BLOCK DIAGRAM


54
19.1. SCHEMATIC DIAGRAMS

SM012 POWER BOARD - SHEET 1


55
SM012 POWER BOARD - SHEET 2
56
SM012 POWER BOARD - SHEET 3
57
SM012 POWER BOARD - SHEET 4
58
SM012 POWER BOARD - SHEET 5
59
QSS_TUN2

8V_FILTERED
L1003
22u
26R_100MHZ_1.5A
L2000 C2004
Q2002

C1014
R1013 470p
BC848B

50V
47u
100R SIOMAD 50V
12 NC 13

1N4148

R1036
IC204

12k
TU1000
50V 22u
SCL R1004 R1029 SC1_AUDIO_L_OUT

AGC 1 100R 11 SCL TAGC 14 C2005

QSS_TUN2
C1020
TUN2_CVBS Q2001
100R

25V
33p
BC848B

QSS_TUN1
C1034 X1000 50V 22u

R1032

R1037
SDA

R1043
SC3_AUDIO_L_OUT

10k

47k
R1008

75R
TU 2 100R 10 SDA REF 15 C2006

C1021

R2006
22p 4MHz

25V
33p

1k

R2009
25V

1k
FB_CONTROL

VCCA_3V3
VCC_5V
C1036 C1128
VCC_5V R2004
56p
AS 3 9 TOP VAGC 16 R1042 AUDIO_L_OUT 100R Q2003
C1123
BC848B

50V
470n

C1120
56p

50V
220R

C1122
63V

1p8
50V 22u

1p8
R1025 SC1_AUDIO_R_OUT
SCL 4 8 AUD CVBS 17 BC848B R2005
47R Q2004
Q1003 C1130 AUDIO_R_OUT 100R BC848B C2007
C1007
C1113
50V 56p

C1125
25V
33p
50V 22u

R104
100n

X1002
4k7
47u
25V SC3_AUDIO_R_OUT

18.432MHz
R1078

56p
SDA 5 7 DGND AGND 18 C2008
100R
C1013
L1018

R2007
N. C
C2200

25V
33p

1k
VCC_5V
CTF5543_HOR

C1042

R2008
R2200
50V
22u

1n5

1k
TDA9885T

47R
C1028 C1037
R1038
16V R1070 C1137
AFD

1n5
NC 6 6 VPLL 19 100n

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

C1144

C1152
330R C1195 560p

10u
470n 100n
C1002

C1045
C1011

SCL 100R
100n
25V

50V

50V
10u

10n
63V 25V

D_ CT R_ I/O_ 1

XT AL _ I N

T EST EN

ANA_ I N 2 +

ANA_ I N 1 +
NC6

C_ CT R_ I/O_0

NC4

TP

AVSUP
STANDBYQ

NC5
ADR_ SEL

ANA_ I N -
AUD_CL_OUT

XTAL _ O UT
C1029
VCC_5V 100n

C1084
50V
39p
VS 7 5 DEEM VP 20 VCC5V_FILTERED

10n

R1022
N.C

C1048
R1071 C1166

22k
50V

16V
10u
10u

VCC_33V
C1024 C1035 R1128 SDA 100R
R1011 1 12C_CL AVSS 48
4R7 33V_FILTERED
NC/ADC 8 4 FMPLL AFC 21

C1085
C1169
C1006

39p
5k6 2 12C_DA MONO_IN 47
50V
10u

10n 100n L1019


VCC5V_FILTERED R1104
50V 25V
C1025 1k SC1_AUDIO_R_IN

C1201

C1202

C1203

C1204
I2S_CL 3 12S_CL VREFTOP 46 C1156

100n

100n

100n
R1000 33V_FILTERED 22k

R1031

50V

50V
50V

50V
10u
OP1 1n

6k8
VST 9 2k2 3 OP2 22 R1028
390p I2S_WS 4 12S_WS SC1_IN_R 45
C1138 330n L1022
S1008 50V C1174 R1105

R1068
C1005 SAW_SW2 I2S_DA_OUT SC1_AUDIO_L_IN
3 5 12S_DA_OUT SC1_IN_L 44 1k

1k
Q1007 1n
IF2 10 GND 2 VIF2 SIF1 23 330n
2 IN2 OUT2 5 BC858B C1177
I2S_DA_IN1 6 12S_DA_IN1 ASG1 43
1n R1069 C1157 R1106 L1020
L1002

SF_63962
50V
1u

Z1000 R1127 470R 1k AV_AUDIO_R_IN

K
VCC_5V

2
BZT55C3V6
7 ADR_DA SC2_IN_R 42 1n
1 IN1 OUT1 4 4R7 VCC5V_FILTERED 330n

IC206
IF1 11 1 VIF1 SIF2 24 C1148 C1176
R1107 L1023
8 ADR_WS MSP3452G SC2_IN_L 41
1k AV_AUDIO_L_IN
1n
IC207 IC208

1
A
330n

C1200

C1205

C1206
C1170

C1197

C1198

C1199
IC200 9 ADR_CL ASG2 40

100n

100n

100n

100n

100n
470R L1021

50V

50V
50V

50V

50V

50V
10u
C1158 R1108
IF1

S1009 R1067 1N4148 1k AUDIO_R


10 DVSUP SC3_IN_R 39 1n S2011
270p 470p
C1080 C1171
100u C1140 330n AUDIO_R2
3 50V 50V R1110 L1024
C1081 C1086 11 DVSS SC3_IN_L 38
GND 1k AUDIO_L S2008
100R 2 IN2 OUT2 5 1n
L1008 330n C1153 SC3_AUDIO_R_IN
VCC5V_FILTERED R1124 K9356M 12 12S_DA_IN2 ASG3 37
VCC_5V L1025
C1192

C1194

R1111
100n

S1003 C1164 S2007


16V

16V

22u
1u

Z1003 IDTV/MMC/DVD_R_IN
R1125

R1126

1n 1k
1 IN1 OUT1 4
10k

13 NC1 SC4_IN_R 36
1k

C1079
50V C1078 330n C1147 R1109 L1026 S2005
1n5 C1175
10n VCC5V_FILTERED 10u
50V 14 NC2 SC4_IN_L 35 1k IDTV/MMC/DVD_L_IN
50V
1n
330n S2006
IF1 C1193 15 NC3 AGNDC 34
BA782

D1003

D1007

BA591

SC3_AUDIO_L_IN

R1048

R1050
C1163
L1032

ESD

15k

2k4
16 RESETQ AHVSS 33
RESETQ_MSP
C1055 C1145 C1149 S2010
C1087

S C 2_OUT_R

S C 1_OUT_R
AUDIO_L2

S C 2_OUT_L
DACM _SUB
QSS_TUN1 470p

C 1_OUT_L
Q1015 3u3 100n

CA P L_M
R1123

CA P L_A
DACM _S
DACM _R
C1052

DACM_C
DACM _L
1kV

AHVSUP
DACA_R
S1010

DACA_L

VREF 1
VREF 2
BC848B 47k Q1005 22n
BC848B 50V
Q1016
C1191

100n
16V

BC848B 10p
25V

S
19

27
17

18

20

21

22

23

24

25

26

28

29

30

31

32
SAW_SW2

R1049
R1121 R1122

4k7
HP_R

R1051
10k 10k

C1118
75R

1n
C1116
HP_L

1n
C1112

VCC_8V
50V

P L1002
R1052

1
560R
1n
L1001 1n 4R7 8V_FILTERED
MUTE_AMP 50V
C1114 R1130
5
HEADPHONE

50V
C1154

C1054

R1089

C1134
4

100R
C1010

R1093
R1010

C2202

100R
50V
22n

C300

C295
100u

100n
50V
47u

D1000 D1001

50V

16V
10u
100R 12 SIOMAD NC 13 A K K A

P L1001
1N4148

10u
R1039

1 2 2 1
IC205

R1114 3 10u 50V


MAIN_R
12k

TU1001
2k2
C1097 50V

R2202
2

220R
R1005 R1030 1n
50V C1182 C1185
SCL 100R 11 SCL TAGC 14 TUN1_CVBS 1n5 2n2 2n2
AGC 1
C1022

1 50V

C1119
100R PL1003 50V
25V
33p

MAIN_L 50V C1126


SDA

C1121

L1030
1n
50V

50V

L1029
1n

1n
50V

50V
R1034

R1040

C1106 C1150

C1133
C1038 X1001 1 IDTV/MMC/DVD_L_IN

SUBW

1n
1u
10k

47k

R1009 R1103
100R 10 SDA REF 15 4k7
TU 2 16V
C1023

2 100u HP_R
25V
33p

R1095

R1098
4MHz
R1044

22p

100R

100R
C1165
75R

25V
50V
VCC_5V

C1039 3 IDTV/MMC/DVD_R_IN 1n C1178 22u


S1000 C1117 50V C1151

C1167

100u
9 TOP VAGC 16 R1035 470p L1028
AS 3
1n
470n 63V 2k2 R1129

AUDIO_L_OUT
AUDIO_R_OUT
R1090
L1027

R1094
100R

100R
C1136 4R7
BC848B C1196 VCC5V_FILTERED 22u
8 AUD CVBS 17 47R Q1002 100n 100u
SCL 4
R1026 C1172
C1008

IC209

C1180

C1183
25V
33p

100u
IC2000

1n
50V
SDA 5 7 DGND AGND 18 R2017 C1162 8 VDD OUTA 1
47u
1 GND 28 100R 100n C1179
C1043

SDA

R1112

C1184
C1015

220p
50V
1n5

47k
25V

TDA9885T
33p

SDA

2n2
C1030 C1040 47p

8V_FILTERED
R1041 C2201
CTF5543_HOR

R2201

C2009 C2025
6 AFD VPLL 19 OUTB INA-

R1102
47R

NC 6 R2018 7 2

R1101

47k
150R R1092 R1096

10k
470n 220n 2 CAPACITANCE 27 100R 22u
C1047

SCL

C1181
1k 1k 220p
TDA1308
50V
10n

63V 16V C1173


C1003

C1012

SCL
100n

22u C2026

1u
C1031 BC848B L1017 50V
10u

BC848B
VCC_5V 50V Q1009
VCC5V_FILTERED C2010 47p Q1011
VS 7 5 DEEM VP 20 8V_FILTERED 4k7 6 INB- INA+ 3
S2000
R1100
C1049

10n 3 VS 26
R1023

ADDR
16V
10u

50V
22k

100n

2n2
C1026 C1041

C1168
R1012
16V

C1159
C2027

50V
1n

50V
C2012 C2028

1u
NC/ADC 4 FMPLL AFC 21 C2011 INB+
50V

8 R2010 R2019 5 VSS 4


1n
C1009

VCC_5V
50V
10u

5k6 10n 100n SC2_AUDIO_L_IN 1k 4 L1 25 1k SC2_AUDIO_R_IN


R1
50V 25V
C1027 330n 330n IDTV/MMC/DVD_R_IN
33V_FILTERED R1027 S2002 S2009
R1001 10k
R1024

IDTV/MMC/DVD_L_IN C2029

HP_L
C2014 C2030
6k8

3 OP1 OP2 22 22k C2013 R1113


50V

50V

50V

50V
VST 9 R2011 R2020
1n

1n
S2001 S2003

C1124

C1132
2k2 390p SC3_AUDIO_L_IN 1k 5 L2 R2 24 1k SC3_AUDIO_R_IN
50V SAW_SW1

22u

22u
C1004 S1007 330n 330n
3 C2015 C2032
GND 2 VIF2 SIF1 23 C2016 C2031
50V

50V
IF2 10 R2012 R2021
1n

1n
2 IN2 OUT2 5

SC2_AUDIO_R_OUT

SC2_AUDIO_L_OUT
1n PC_AUDIO_L_IN 1k 6 23 1k PC_AUDIO_R_IN
L3 R3
L1000

50V K3953M
1u

330n 330n STBY_3V3


Z1001
1 IN1 OUT1 4 16V
S1006

IF1 11 1 VIF1 SIF2 24


7 NC1 NC4 22

3
IC201 GND TEA6420
IF

2 IN2 OUT2 5

BZT55C5V1
K9356M 8 NC2 NC3 21

R100

R101
D1005

C255

4k7

4k7
Z1002

50V
4n7
1 IN1 OUT1 4 C2033
C2017
1n

C2018 C2034 S107


R2013 R2022

1n
L216 PC_AUDIO_R_IN MUTE_AMP
SAW_SW1

YPBPR_AUDIO_L_IN 1k 9 L4 R4 20 1k YPBPR_AUDIO_R_IN
SW01=H L' 10k 10k R102
330n 330n Q100
R1120 R1119 HEADPHONE

JACK-AK16
SW01=L BG,DK,I,L PC_AUDIO_L_IN BC848B 4k7
C2020 C2037 C2036

JK200
R2014 R2023
1n

12 3
BC848B L219
DAC_AOL 1k 10 19 1k DAC_AOR
C1189

L5 R5 S108
100n

Q1014
16V

C257
C2019

330n 330n MUTE_AMP

50V
4n7
S2010 & R2208 are for mute option

BZT55C5V1
S1005

1n

D1004
BC848B L218 Mute is active high
47k C2022
L2001

R103
R1118 R2015
Q1013

4k7
100R 11 L0UT1 ROUT4 18
BLM21B201S
AUDIO_L
C2021 22u
1n
L1031

C2024
BA591

D1006

D1002

BA782

R2016 L2002

C1187 100R 12 ROUT1 LOUT4 17


BLM21B201S
AUDIO_R
IF C2023 22u
1n

50V
10n L2018 22u C1127
R2203 R1091
50V
100R 13 LOUT2 ROUT3 16 100R AUDIO_R_LINE_OUT
C1001

AUDIO_L2 C254 22u 50V


R1117

R1116

50V
C247

1n
C1186

50V

50V
10k

1n
1k
C1188

16V
1u
100n

L2019 22u
16V

R2204 22u 50V R1097


R1115 100R 14 ROUT2 LOUT3 15 100R AUDIO_L_LINE_OUT
BLM21B201S
VCC5V_FILTERED
C1000

100R AUDIO_R2 C251 C1139


50V
C249

1n
50V
1n

SM012 MAIN BOARD - TUNER/IF/AUDIO CIRCUIT


60
SC3_AUDIO_R_OUT
SC3_AUDIO_L_OUT

SC3_AUDIO_R_IN
SC3_AUDIO_L_IN
SVHSfromSC2_C
VCCA_3V3
LG_1/IRQPDP
VCC_8V
VIDEO SWITCH TEA6415C

SC3_V_OUT
PANEL_VCC
39p 4R7 V8

VCCA_3V3

SC3_V_IN

PIN8_SC3
VCCA_3V3 VCCA_3V3

VCC_12V
C304 R229
5V

BZT55C10

K D2101 A
1
100n
C298

C294
10u

16V
75R IDTV/MMC/DVD_CVBS

R251

R250

150p
C301

C270
4k7

4k7
V8

50V

50V
1n
SDA_PANEL
R264

SCL_PANEL
S111
A D221 K
IC210

2
1 2

S113

S112
BZT55C10 330R
SC1_V_IN C274 C282

S648
Q200 PL203 L203 R249
1 INPUT1 INPUT8 20 MAIN PICTURE C284

S109
BC848B DISP_EN/PDWN
N.C TO SVP
220n 220n R235 SC2_AUDIO_R_OUT
C285
R203

16V 16V 75R CVBS_SVP

S638

S639
PANEL_VCC
39p
75R

50V

K D2003 A 4n7
R206 2 1

1
S643

S642
PDP_GO/BL_ON_OFFCPU_GO L207 50V

V8
C303
100R 2 DATA GND2 19 1k

S641
47p
25V
R239 K D2004A BZT55C10 BZT55C10 BZT55C10 SC2_AUDIO_R_IN
SDA 10k 2 1

2
VCC_12V N.C L209 R253
R220 2 1 2 1
K D2105 A K D2104A
C260 A D2000K BZT55C10 330R SC2_AUDIO_L_OUT

R2024

R2025
SC2_V_IN R226 1 2

3
330R

330R
Q203 S640 4n7 150p
3 INPUT2 OUTPUT6 18 100R

L2006
C264 C277

BZT55C10
BC848B BZT55C10 50V C2045 BZT55C10

K D2002 A
1
N.C
C292
R204

L2005
R240 1n

L2114
39p

220n
75R

50V

4n7 BZT55C10
2 1

PL103

11

13

15

17

19

21

23

25

27

29
16V 10k 75R VxtoVPC C2040 K D2103 A

9
C2044 1n
R221 2 1
C287

K D223 A

L2003
R207 R227

L2125
47p
25V

50V

A
1
C2042

C2038

D2001
4 CLOCK OUTPUT5 17

2
100R 100R 1k

C2039
GOES TO VPC3230

150p
150p
50V

S636
1n SC2_AUDIO_L_IN
R241 FOR PIP PICTURE
SCL 10k

L2004

6
L2008 L214
TUN1_CVBS R222
C265 4n7 C266

2
K

7
L2007 D203

10
1 2

12

14

16

18

20

22

24

26

28

30
R200

C259

5 INPUT3 OUTPUT4 16 A K

S646

S647
39p
75R

50V

A K PIN8_SC2
N.C 1 2

8
220n D205

V8

TXCLKOUT+
16V
TEA6415C

TXCLKOUT-
TXOUT3+

TXOUT2+

TXOUT1+

TXOUT0+
SC2_B

TXOUT3-

TXOUT2-

TXOUT1-

TXOUT0-
C279
R230

9
23 25 27 29 31 33 35 37 39 41 75R R288 BZT55C5V1 D2100
6 INPUT4 OUTPUT3 15 100R
N.C A K
R205

C280

AV1_V_IN 1 2D207

10
39p

220n
75R

50V

Q202 22 24 26 28 30 32 34 36 38 40 42 TV_LINK
16V 10k

BZT55C10
PL205
BC848B

K D222 A
1
N.C R223

PARITY

11
S201 R237

C258
R289 75R

4n7
50V
L213
7 PROG OUTPUT2 14 75R SC2_V_OUT 75R R290 SC2_G

V8

12
S200
SELECTABLE VIDEO OUT 2 1

2
VCC_8V 10k 1k FOR SCART 2 K D208 A
SVHS_Y_IN
CONNECT C288 R224 Q1004 R242 LVDS OUTPUT 2 4 6 8 10 12 14 16 18 20

13
R1033 L204 SC2_R
S204
C297

8 INPUT5 OUTPUT1 13 100R R1046


39p

BC848B
50V

1 3 5 7 9 11 13 15 17 19 21 C2049
N.C

75R SC1_V_OUT

14
R201 220n SVHSfromSC2_C

L206
S205
75R 16V 10k R1045 C293 100n

C252
150p
V8
R225

50V
L200 1k

15
150p 16V
9 VCC GND1 12 75R SC2_FB

2
K
100u

220n
C283

C299

C273

VCC_8V

16
R2001

S220BZT55C10
D212
22u

C267
16V

50V

16V

L208 R275

150p
2
150p

C248
Q2000

A D204 K

50V
1n
100R BC848B

R286

330R
R252
C250 75R

L210
2

2
K

K
75R
C275 2 1
K D218 A

17
R276

D202
S221

R287
D209

75R
A
10 INPUT6 INPUT7 11

1
TUN2_CVBS R2002 1n

R260
BZT55C10 SC2_V_OUT

L205
75R
C276

1
75R SC3_V_OUT

18
220n
39p

K D2102 A

2
K

K
C291 1 2

A
R231

1
16V R2003 A D214 K 2 1
75R

C296 2 1
C268

SC3_V_IN 1k K D211 A

19
39p

R254
330R
50V

BZT55C10
R202 220n

R285
IDTV/MMC/DVD_CVBS 50V SC2_V_IN

75R
S212

A
1

1
75R 16V D210

20
4n7 C286

1
MMC_CVBS

K D220 A

BZT55C10
BZT55C10

2
A D213 K
21
A
1

N.C
C269 150p
N.C

2 1
K D2500 A

D219
D206 50V

2
R261 BZT55C10 150p 50V

1
75R C253
1 2

2
A D224 K

K
C278 150p
150p
C261

SC1_AUDIO_R_OUT
SC1_AUDIO_L_OUT
50V

SC1_AUDIO_R_IN
SCSCL

SC1_AUDIO_L_IN
SC1_FB

SCSDA
SC1_V_OUT

SC1_G
SC1_R

SC1_B
SC1_V_IN

PIN8_SC1
AV1_V_IN
BZT55C5V1
N.C

A D215 K
PL201
1 2 CHROMA SWITCH
V8
1

2 C263 SVHS_Y_IN S635


39p
1 2
A D217 K
3
220n CIN
R267
4 10k

R266
18k
1 2 R232 C262
A D216 K
5 75R I2C BUFFER FOR PANEL
6
C245
R270
Q204 C246
MMC/DVD
L202
100R BC848C Q205
VIDEO INPUTS IC215
CIN
7 220n BC848C
DIMMING SELECTION

VCC_5V
AV_AUDIO_R_IN
16V 220n DVD_12V_SENSE
C271

1 NC1 VCC 8
R268

R273
1n

16V
8
47k

10k

MMC_CVBS

S645
R274
SDA2

1k

MMC_G
MMC_R
MMC_B
2 NC2 VCLK 7

S213
AV_AUDIO_L_IN
ST24LC21

S644
SCL2
C272

L201
50V

3 NC3 SCL 6
1n

SVHSfromSC2_C S633 S651


4k7 VCC_5V SDA_PANEL SCL_PANEL
CHROMA_SW

R271 4 VSS SDA 5

PL1
R269 C_SELECTED
Q206

6
C2050

100n

47k BC848C S652


16V

VCCA_3V3
EXTERNAL INPUT
S634

SEL
VCCA_3V3 IC214

STBY_5V
STBY_3V3
C290 VCC_5V
gnd

1Q 1 VCC 16

C2051

C2052

C2053
100n

100n

100n
IC213 100n
S650

S637

16V
STBY_3V3
gnd

2Q 2 Q0 15
R211

R212

1 A0 VDD 16
2k

2k

100n
R280

C281
150k
DDC_CLK_PC
IC211
STBY_3V3

VCCA_3V3
15 R279
SDA2 VCCA_3V3
R215 3Q 3 DSERIAL 14 10k
2 A1 SDA 15

VCC_5V
330R
R255 14 22R 1 1A VCC 14 1N4148

VGA_VSIN
100n
C289

16V
D200
13

DDC_5V
S223

S649
R277

R265

R246

R248

SCL2
4k7

4k7

4k7

4k7

DDC_DATA_PC 1N4148 4Q 4 OE 13
3 A2 SCL 14 330R

100n
C302
12 21 Y 6A 13

16V
R256
74HC595D

VGA_HSIN
BZT55C12

BZT55C12

D201
2

2
A D2501K

A D2502K

11
5Q 5 STOP 12

R216

R217
R213

10k

10k
R257

CHROMA_SW 4 P0 INT 13
4k7

10 22R 32 A 6Y 12
DDC_5V
R258

R259

1
4k7
4k7

PCF8574 9 74LVC14A IC212 6Q 6 SHCP 11


DISP_EN/PDWN 5 P1 P7 12 LG_1/IRQPDP
8 42 Y 5A 11
PGAGND

8 VCC NC1 1 VCCA_3V3

7
VGA_VSIN 7 VCLK NC2 2 7Q 7 MR 10
RGB_SW2 6 P2 P6 11 RGB_SW3

R281

R283
6 53 A 5Y 10 ST24LC21

10k

10k
R214 VGA_VSIN DDC_CLK_PC 100R 6 SCL NC3 3
VGA_HSIN 22R 22R R218
5
R238 DDC_DATA_PC 100R 5 SDA VSS 4 8 GND Q7OUT 9 PC_STBY
RGB_SW1 7 P3 P5 10 SW_ENABLE

R282
63 Y 4A 9 R219
4

10k
3 75R
Q207
gnd

R208 BC848C
8P VSS 4 9
2 75R 7 GND 4Y 8
PANEL_VCC_ON/OFF R209
Q208
75R BC848C
1 PGAGND

R284
R210

47k
PL200
VGA_GIN
VGA_RIN

VGA_BIN

PORT EXPANDER D-SUB 15 PC INPUT & DDC CIRDUIT


PC STAND-BY

SM012 MAIN BOARD - IN/OUT CIRCUITS


61
VCC_5V

I2S_DA_OUT
I2S_DA_IN1

BLM21B201S
I2S_WS
IC316

I2S_CL
S303

L2009
VCCD2_3V3 VCCD_3V3
RGB_SW3 R2030 C362

DHS_2EX
RESETQ_MSP

100n
DVS_2EX 1k 1A R 16 VCC_5V
VCCD2_3V3
SC1_R 2B O 15

C331

C333
10u

2n2
50V
25V
SCL SDA C2046

R2 7

R3 6

R4 5
R2028
SC2_R 3C N 14 SC1_FB

S302
L2010

BLM21B201S
18 R1
10R

YPBPR_AUDIO_R_IN
YPBPR_AUDIO_L_IN
STBY_5V R2032
10u BLM21B201S

AUDIO_R_LINE_OUT

AUDIO_L_LINE_OUT
VCC_5V 33R RGB_R_VPC 4D M 13

L313
50V
2

4
PI5V330_SOIC
R2026

R2027

L308 SC2_FB
100R

100R

R2031
C2047 C2048 VCC_5V 16V 33R SC1_G 5E L 12 FB_VPC
BLM21B201S 220n

C330

C332
3p3

3p3
50V

50V
SC2_G 6F K 11 SC1_B

R316

R317
BLM21B201S

22R

22R
10n 100n
50V 25V C318 25V VCCD2_3V3
47n RGB_G_VPC 7G J 10 SC2_B

L311
44

43

42

41

40

39

38

37

36

35

34
50V 20.25MHz

BLM21B201S
1n5 8H I 9 RGB_B_VPC
C340
I2S_DEL_OUT1

I2S_DEL_IN1

DVSUP1

DVSS1
I2S_DEL_WS

RESETQ
SDA
SCL

ADR_SEL

I2S_DEL_CL

TEST

L314
X300
C319 50V
1n5

S331

S330

S323

S324
50V
68n

R315
50V

10k
390p

1 NC1 NC25 33
C341
C343
RGB SWITCHING FOR VPC
C320
2 NC2 NC24 32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45
C317

BZT55C10
2
A D225 K

BLM21A601S

BLM21A601S

BZT55C10
2
3 NC3 NC23 31

A D226 K

AVO

C3
C2

GNDC

VSUPC
L316

L317
10u

C1
C0
VS
NC2

CLK5
XTAL1
50V

XTAL2

INTLC
4 NC4 NC22 30

ASGF2

FPDAT
VSTBY

FSY/HC

GNDSY
MSY/HS

VSUPSY
1
25V

1
47n
5 NC5 NC21 29 R322
DIN[0]
IC2001 33R

C359

C360
470p

470p

SVHSfromSC2_C
50V

50V
18 R1
6 NC6 NC20 28 C323 65 GNDF Y0 40
DIN[1]

7 NC7
MAD4868A NC19 27 66 VRT Y1 39 2 R2 7

VxtoVPC
DIN[2]
3 6
8 NC8 NC18 26 23 1 23 1 67 I2CSEL Y2 38 R3

BACK RIGHT

CIN
DIN[3]
BACK LEFT

4 5
9 NC9 NC17 25 A A 68 ISGND Y3 37 R4

DIN[0-23]
L2011
I2S_DEL_OUT2

I2S_DEL_OUT3

I2S_DEL_OUT4

C344
10 NC10 NC16 24 JK303 JK304 69 VSUPF VSUPY 36 VCCD2_3V3
SVP ENTEGRESINE
I2S_DEL_IN4
I2S_DEL_IN2

I2S_DEL_IN3

BLM21B201S
L AUDIO FAV R AUDIO FAV
11 NC11 NC15 23 70 VOUT GNDY 35 100n R323
C321 16V DIN[4]
33R
DVSUP2

18 R1
DVSS2

75R 71 CIN Y4 34
NC13

NC14
NC12

R304 C361 DIN[5]


1n
2 7
75R
R305
1n
C322
72 VINI IC216 Y5 33 R2
DIN[6]
3 6
75R 73 VIN2 VPC323XD Y6 32 R3
20

21

22
17

18

19
12

13

14

15

16

R306 DIN[7]
680n
4 5
75R 74 VIN3 Y7 31 R4
R307

100n

C346
75R 75 VIN4 GNDLLC 30

16V
L300 R300
VCC_5V 76 VSUPAI VSUPLLC 29 L315
100u

220n

390p
C350

C348

C349

C305
VCCD2_3V3

1n8
16V

16V

50V
VCC_5V

BLM21B201S
77 GNDAI LLC1 28

C306

C316
R321

47n

10u
25V

50V
N.C
78 VREF LLC2 27 22R CLK_2EX
PL301

R2029
79 FB1IN VSUPPA 26

10k
1 AUDIO_R_LINE_OUT

C345

C347
1n5

47n
50V

25V
S325

R1/CR1IN

R2/CR2IN
B1/CB1IN

B2/CB2IN
R312

80 AISGND GNDPA 25

VSUPCAP
G1/Y1IN

G2/Y2IN
4k

GNDCAP
FB_VPC

FFRSTW
ASGF1

YCOEQ
VSUPD
S316

GNDD

CLK20
RESQ

VGAV

FFWE
TEST

FFOE
NC1
3

FFRE
AUDIO_L_LINE_OUT

FFIE
SDA
SCL
S326 220n C363
RCA_Y

SCART RGB

4 SUBW
RCA_PB

10

11

12

13

14

15

17

18

19

20
16
220p

220n
C356

21

22

23

24
C364

9
1P_RED_FAVWHITE_FAV WHITE_FAV

R331
75R
30032233

JK300

50V

220n C365 50V


N.C
123

330p 16V
Y

S301
RCA_PR

C311 220n
RGB_B_VPC
R313

100R
R318
100R
R319
100R
R320
C327
30032234

1k
JK301

bu caplerin yerine tek 100nf takabilirsin.


220p

C357
123
Pb

R332

50V 50V
A

50V
75R

330p
N.C 16V 270p 390p C342
50V

C312 220n
VCC_5V

RGB_G_VPC
Pr

C334 C337 220n


JK302

C328 16V
123

N.C
IC317
220p

C358

25V
A

560p 50V
50V

1n5 RGB_SW1 R325


50V
N.C

100n
C352
330p 16V 1k 1A R 16 VCC_5V

16V
C335
C313 220n
R333

C338
75R

SC1_R 2B O 15

SDA3
RGB_R_VPC 16V

SCL3

RX1_RST#
D102 D104 D106 100n
BAV99 BAV99 BAV99 C329 16V
220n SC2_R 3C N 14 SC1_FB
N.C

S340
SC2_FB
330p
C308

C336
50V

4D M 13

BLM21B201S
C339
S310
R309
C324
PI5V330_SOIC
MMC RGB INPUTS

MMC_B 75R SC1_G 5E L 12

L312
220n
16V SC2_G 6F K 11 SC1_B
N.C
IC318
330p
C309

50V

7G J 10 SC2_B
C325 S311
RGB_SW2 R326 C353 R310
VCCD2_3V3

8H I 9
100n

1k 1A R 16 VCC_5V MMC_G 75R


RGB_GIN S312
220n
RCA_PR 2B O 15 16V
S309
N.C
330p
C310

VGA_RIN 3C N 14
50V

S314 C326 RGB_RIN


RIN2 4D M 13 R311
PI5V330_SOIC MMC_R 75R
RCA_Y 5E L 12 220n
S308 16V
VGA_GIN 6F K 11 RCA_PB
GIN2 RGB_BIN
S307 7G J 10 VGA_BIN
S336

S337

8H I 9
FB

BIN2

RGB SWITCHING FOR SVP


VGA&YPbPr SWITCHING

SM012 MAIN BOARD - VPC3230 CIRCUIT


62
100n

100n
C434

C435
PAVDD1

VDDMQ_2V5

VDDMQ_2V5
R435
22R VL1_8

ODD_PINK

VD1_8
DHS_2EX
IC107

CAS#

RAS#

CS0#
C2206

C2203

C2204

C2205

WE#
100n

100n

100n

100n

100n
C440

C444
10u
16V

16V

16V

16V

16V
16V

VD1_8
CLK_2EX
74LX1G86STR

STBY_3V3
MLF1 C438 R2210
R2214
10k

DIN[7]

DIN[6]

DIN[5]

DIN[4]

DIN[3]

DIN[2]

DIN[1]

DIN[0]

CLKE
18 R1

GND
BA1

BA0

VCC
2n7

R430R431
50V

22R
PAVDD2 2 R2 7
R436

VD1_8

11 A

21 B

41 Y
22R

22R
3

C2207

C2208

C2209

C2210

C2211
6

R429

5
100n

100n

100n

100n

100n

C443
R3

22R
10u
16V

16V

16V

16V

16V
16V

S110

VDDMQ_2V5
ODD_PINK
PLF2 C439 C425 C428 4 R4 5 C470 C471
R434 DVS_2EX

DIN[7]

DIN[6]

DIN[5]

DIN[4]

DIN[3]

DIN[2]

DIN[1]

DIN[0]

VD1_8
16V R2216 1k
2n7 R432 100n 100n 100n 33R

R2 7

R3 6

R4 5
100n 100n

R2213
50V 10k C424 16V 16V 16V

18 R1
R433 C418
10k

VCCA_3V3
S437

4
100n

MCLK0#
PL104

MCLK0
16V

10

11

12
26R_100MHZ_1.5A

DQM[3]

DQM[2]
MD[31]

MD[30]
MD[29]

MD[28]

MD[27]

MD[26]

MD[25]

MD[24]
MD[23]

MD[22]
MD[21]

MD[20]

MD[19]

MD[18]

MD[17]

MD[16]
DQS[3]

DQS[2]
MPUGPIO4

MVREF
PDVDD L407 MD[0]
MD[1]

R2215
DIGITAL IDTV INPUTS [ITU 601]

33R
VL1_8 MD[2]
C2216

C2217

C2218

C2219
C437
100n

100n

100n

100n

100n
C455

C459
10u
16V

16V

16V

16V

16V
16V
MD[3]
MD[4]
100n MD[5]
MCA[14] 16V
S413 MD[6]
MCA[15]
MD[7]

192
191
190

178
177
189
188
187
186
185
184
183
182
181
180
179

176
175
174
173
172
171

152
151
170

150
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153

149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
MD[8]
S411 MD[9]
R236
MCAD[0] 100R

VSSC10

VSSM16

VSSM15

CS0_
VSSM14

VSSM13

VSSM12

VSSM11

VSSM10
MPUGPIO1
MPUGPIO2
MPUGPIO3
MPUGPIO4

DQS3

DQS2
MD[10]

VSSH4

VSSC9

VSSC8

VSSC7
VDDC10

CS1

VSSM9
VDDM16

VDDM15

VDDM14

VDDM13

VDDM12

VDDM11

VDDM10
MD28
MD31

MD30
MD29

MD27

MD26

MD25

MD24
MD23

MD22
MD21

MD20

MD19

MD18

MD17

MD16

VSSR
VDDH4

VDDC9

VDDC8

VDDC7

MCK0_
DQM3

DQM2

VDDM9
BA1

BA0

CAS
RAS

MCK0
VDDR
WE
NC
18 R1

MVREF
CLKE
MD[11]
MCAD[1]
MD[12]
2 R2 7
MD[13]
MCAD[2]
3 MD[14]
C403 6

MCAD[0-7]
GIN2 R3 VDDMQ_2V5 MD[15]
MCAD[3] 193 128
Y_G2 MPUGPIO0 VDDL VDDL MD[16]
4 5 194 127
100n R4 A_D0 VSSL MD[17]
195 126 MA[0]
R406

16V VD1_8 A_D1 MA0


75R

R234 196 125 MD[18]


MCAD[4] MA[1]

100n
C413
A_D2 MA1

MCA[0-19]
100R

16V
197 124 MD[19]
18 R1
A_D3 VDDM8 MD[20]
MCAD[5] 198 123 MA[2]
R233 VDDC12 MA2 MD[21]
MCA[0] 2 7 199 122 MA[3]
100R R2 VSSC12 MA3 MD[22]
18 R1 MCAD[6] 200 121
3
A_D4 VSSM8 MD[23]
C404 MCA[1] 6 201 120 C447 MA[4]
BIN2 R3 A_D5 MA4 MD[24]
2 7 MCAD[7] 202 119
A_D6 VDDM7

MA[0-11]
PB_B2 R2 100n 16V MD[25]
MCA[2] 4 5 203 118 MA[5]
100n 3
R4 A_D7 MA5 MD[26]
6 204 117 C446 MA[6]
R407

16V R3 STBY_3V3 VDDH5 MA6


75R

205 116 MD[27]


MCA[3]
VSSH5 VSSM7 MD[28]
4 5 206 115 MA[7]
PC&YPbPr INPUT R228
R4
207
ADDR0
ADDR1
MA7
MA8
114 100n 16V MA[8]
MD[29]
MD[30]
MCA[4] 208 113
100R ADDR2 VDDC6 VD1_8 MD[31]
18 R1 209 112 MA[9]
ADDR3 MA9
C405 MCA[5] 210 111 MA[10]
RIN2 ADDR4 MA10
2 7 211 110
PR_R2 R2 ADDR5 VSSC6 DQM[0]
212 109

DQM[0-3]
MCA[6] MA[11]
100n 3
ADDR6 MA11 DQM[1]
6 213 108
R408

16V R3 ADDR7 MD15 MD[15] VD1_8


75R

R243 214 107 DQM[2]


MCA[7] 100R VDDC11 VDDC5
215 106 DQM[3]
4 5 18 R1 100n C448
R4 RD_EMU VD1_8 VSSC11 MD14 MD[14]
216 105
RD VSSM6
2 7 217 104
WR_EMU R2 WR MD13 MD[13]

DQS[0-3]
C411 100n DQS[0]
218 103
3
ALE VDDM6 16V 16V DQS[1]
6 219 102 100n
ALE_EMU R3 MPUCSON MD12 MD[12] DQS[2]
220 101
INT# 100R INT VSSM5 DQS[3]
4 5 221 100
C401 MPUCSON R4 R244 AVDD_ADC3 AVDD_ADC3 DQS1 DQS[1] C456
222 99
C_SELECTED S430 AVSS_ADC3 VDDM5 VDDMQ_2V5 DIN[0]
223 98
C VREFN_3
VREFP_3
224
225
VREFN_3
VREFP_3 IC224 VSSM4
DQM1
97
96
DQM[1]
DIN[1]
DIN[2]
R401

100n PR_R1 PR_R1 MD11 MD[11]


75R

226 95 DIN[3]
PR_R2 PR_R2 VDDM4 DIN[4]
MAIN PICTURE 227 94
C400
AVDD_ADC2
228
229
AVDD_ADC2
AVSS_ADC2 SVP_EX_51 MD10
MD9
93
92
MD[10]
MD[9] C449
DIN[5]
DIN[6]
CVBS_SVP CVBS2 VREFN_2 VREFN_2 VSSC5 DIN[7]
230 91
100n VREFP_2 VREFP_2 MD8 MD[8] 100n DIN[8]
231 90
R400

16V C C MD7 MD[7] 16V VD1_8


75R

232 89 DIN[9]
C402
S431 PB_B1 PB_B1 VDDC4 DIN[10]

DIN[0-23]
233 88
CVBS3 PB_B2 PB_B2 MD6 MD[6] DIN[11]
234 87
CVBS_SVP 100n AVDD3_AVSP2 AVDD3_AVSP2 VSSM3 DIN[12]
235 86
16V AVSS3_BG_ASS MD5 MD[5]
R402

DIN[13]
75R

R427 236 85
75R CVBS_OUTP VDDM3 DIN[14]
237 84
CVBS_OUTN MD4 MD[4] DIN[15]
S441 238 83
AVDD_ADC1 AVDD_ADC1 VSSM2 DIN[16]
239 82
AVSS_ADC1 DQS0 DQS[0] DIN[17]
240 81
VREFN_1 VREFN_1 VDDM2 DIN[18]
241 80
VREFP_1
S439
VREFP_1 VSSM1 DIN[19]
242 79
CVBS1 DQM0 DQM[0] DIN[20]
243 78
CVBS2 CVBS2 MD3 MD[3] DIN[21]
S438 244 77
CVBS3 CVBS3 VDDM1 VDDMQ_2V5 DIN[22]
C406 245 76

100n
C451
S425 AIN_N1 MD2 MD[2]

16V
246 75 DIN[23]
Y_G1 Y_G1 Y_G1 MD1 MD[1]
247 74
RGB_GIN 100n AIN_N2 VSSC4
248 73
16V Y_G2 Y_G2 MD0 MD[0]
249 72
R403
75R

AIN_N3 DIN20 DIN[20]


100n 250 71

100n
C452
VSSC13 DIN21 DIN[21]
251 70
C409 VDDC13 DIN22 DIN[22]
252 69
VD1_8 PDVDD PDVDD DIN23 DIN[23]
253 68
PDVSS VSSC3 VD1_8
254 67
S426 PAVDD PAVDD VDDC3
255 66
PR_R1 PAVSS VSSH3
256 65
RGB_RIN XTALI VDDH3 VDDH

TESTMODE

LVDSVDDP
100n
R404

LVDSGND
75R

VREFP_1

VREFP_2

VREFP_3
VREFN_1

VREFN_2

VREFN_3
LVDSVCC
16V C407

PLL_GND
PLL_VCC
PAVDD1

PAVDD2

AIN_HS
PAVSS1

PAVSS2

AIN_VS

FLD_IO
50V

VDDH1

VDDH2
VDDC1

VDDC2
VSSH1

VSSH2
VSSC1

VSSC2
TCLK+
RESET
XTALO

DIN19
DIN18
DIN17
DIN16
DIN15
DIN14
DIN13
DIN12

DIN11
DIN10
TCLK-
20p

TD1+

TB1+
TC1+

TA1+
MLF1

V5SF

DIN9

DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN8

DIN1
DIN0
TD1-
PWM

TB1-
TC1-
PLF2

TA1-

GPO
SDA
SCL

CLK
14.31818MHz

DE
H
V
C414
X400

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

35
36
32
33
34

37
38
39
40
41
42
43
44
45

57
46

58
47
48

59
60
49

61
50
51
52
53
54

62
55

63
56

64
1
2
3
4
5
6
7
8
9
S427
PB_B1 50V

R418

R419
RGB_BIN 20p
100n
R405
75R

R422
16V C408

10k

100n

100n

100n

100n

100n

100n
C450

C457

C460

C462

C463

C467
C415

22R
22R

16V

16V

16V

16V

16V

16V
DIN[19]
DIN[18]
DIN[17]
DIN[16]
DIN[15]
DIN[14]
DIN[13]
DIN[12]

DIN[11]
DIN[10]
DIN[9]
R2217 DIN[8]

DIN[7]
DIN[6]
DIN[5]
DIN[4]
DIN[3]
DIN[2]
DIN[1]
DIN[0]
VDDH
PLF2
PAVDD1

PAVDD2
MLF1

MAIN RGB INPUT

TXCLKOUT+
SDA_EX

TXCLKOUT-
SCL_EX
RST_H

TXOUT3+

TXOUT2+

TXOUT1+

TXOUT0+
VGA_HSIN
VGA_VSIN

TXOUT3-

TXOUT2-

TXOUT1-

TXOUT0-

33R
VCCA_3V3
PARITY
R2218 2u2

4k7
VCCA_3V3

VCCA_3V3

R420
33R AVDD_ADC3 L404
LVDS OUT

DHS_2EX
S415 DVS_2EX
26R_100MHZ_1.5A VA1_8
VDDL L401 VD1_8 C436

C2234
C2231
C426

C2232

C2233
S440

100n
100n

C442

C445
100n

100n

100n

10u
16V
16V
16V
16V

16V

16V
PWM2
C2404

100n
C2401

C2402

C2403
C2212

C2213

C2214

C2215

C2400

10u

C429
16V
100n

100n

100n
100n

100n

100n

100n

100n

100n
100n
C431

C433

C420

16V

CLK_2EX
16V

16V

16V
10u

100n
16V

16V

16V

16V

16V
16V

16V
16V

100n
C422

16V

DIGITAL SINC
C427
100n
R423

R425
10k

10k

16V
100n
VD1_8

VD1_8
SC2_FB_SVP
26R_100MHZ_1.5A

VDDH
1N4148

MPUCSON MPUGPIO4
D101

VCCA_3V3 AVDD_ADC1 L406

DE_2EX
STBY_3V3 FB_CONTROL VA1_8

TXCLKOUT+
R424

R426

TXCLKOUT-
10k
1k

C2239

C2242
C2241
C2240
100n

100n

100n
C454

C458
100n
100n
16V

10u
16V

16V
16V
16V
150R 600mA lik ferit 26R_100MHZ_1.5A
R428

L400 AVDD_ADC2 L409


1k

VDDH VCCA_3V3 VA1_8


R2211

R2212
100n
C472
R439

10k

10k
1k

STBY_5V

C2230
C2229
C2228

100n
C2220

C2221

C2254

C2222

100n

100n
C465

C468
100n
100n

100n

100n

100n

100n
C421

C423

16V

10u
16V

16V
16V
R413

16V
10u
16V

16V

16V

16V

16V
16V

C2227

100n
SDA_EX 68R SDA3
TXCLKOUT+

16V
TXCLKOUT-
R440
1R SC2_FB_SVP
R414
Q402
BC848B

VCCA_3V3

SCL_EX 68R SCL3


C473

S442
10p

Q401
FB BC848B 26R_100MHZ_1.5A
C410

C412
68p

68p

150R 600mA lik ferit PAVDD L408


S445 L402 VL1_8
VCCA_3V3

C2235

C2236

C2238
100n

100n

100n

100n
C466
C2237
AVDD3_AVSP2

100n
C2226

C469
C2224

C2225

100n

10u
100n
C430
C2223

C432
100n

100n
100n

16V

10u
16V
16V
16V

16V
16V

SM012 MAIN BOARD - VIDEO DECODER CIRCUIT


63
MD[28]

MD[29]

MD[30]

MD[31]
MD[0-31]
VDDMQ_2V5_FLT VDDMQ_2V5_FLT
VDDMQ_2V5_FLT
R500 MVREF
MD[27] 10R
18 100n
R1

1
MD[26] C505

1u R508
10R
R4

R3

R2

R1
2 7 VCCA_2V5_FLT
R2 C518
MD[25]

C501
R512

R510
100u

7
3

1k
R3 6 1k 16V

100n
C517
MD[24] 50V
4 5 C502 4n7
R4 VCCA_2V5_FLT

8
R501

DQM[2]
DQM[3]
DDQS2
DDQS3
MD[23] 10R
1u C525
18
R1 50V 50V
MD[22] 4n7
2 7 C516
R2
MD[21]
3 C524
6
R3 50V

107
108

144

106
100u

24
35
36
48
59
60
71
72
95
96

11
83
12
84

31
30
46
99
58
70
94
14
16
18
19
21
23
38
47
51
63
87
MD[20] 4n7 16V
4 5
R4 16V

DQ26_C11

DQ15_E11

DQ13_F11

DQ11_H11

DQ9_J11

DM3_A11
DM1_G11

VDDQ_B11

VDDQ_D11
DQ14_E12
DQ25_C12
DQ24_D12

DQ12_F12

DQ10_H12

DQ8_J12

VDDQ_E3
VDDQ_F3
VDDQ_H3
VDDQ_J3
DQS3_A12

VDD_D10
DQ27_B12

DQS1_G12
VREF_M12

VDDQ_E10
VDDQ_F10
VDDQ_H10
VDDQ_J10
VDD_C7
VDDQ_B9

VDDQ_D2
VDDQ_B2

VDDQ_B7

VDD_C6
VDDQ_B6
VDDQ_B4
100n
R502 C523
MD[19] 10R 50V
18 4n7
R1 C532
MD[18] 16V
2 7 100n
R2 C522
MD[17] 9 39
3
DQ28_A9 VDD_D3 50V
8 118
R3 6 DQ29_A8 VDD_K10 4n7
C531
MD[16] 20 115
DQ30_B8 VDD_K7 16V
4 5 7 114 100n
R4 DQ31_A7 VDD_K6 C521
22 111
NC_B10 VDD_K3 50V
82 92 4n7
NC_G10 VSS_H8 C530
DQS[0] 120 91
R513 NC_K12 VSS_H7 16V
119 90 100n
15R DDQS0 NC_K11 VSS_H6 C506
DQS[1] 123 89
R514 NC_L3 VSS_H5 50V
134 80
DQS[0-3]

4n7
15R DDQS1
MCLK01# NC_M2 VSS_G8 C529
DQS[2] 122 79
R515 NC_L2 VSS_G7 16V
75 78 100n
15R DDQS2 NC_G3 VSS_G6 C507
DQS[3] 15 77
R516 MCLK01 NC_B3 VSS_G5 25V
116 68 10n
15R DDQS3 NC_K8 VSS_F8 C528
129 67
NC_L9 VSS_F7 16V
131 66 100n
R503 CK-_L11 VSS_F6 C508
130 65
WE#
18
R1 CLKE
R517
33R
143
110
CK_L10
CKE_M11 EM6A9320 VSS_F5
VSS_E8
56
55
25V
10n
C527

CAS#
2
R2
7 109
121
WE-_K2
CAS-_K1 IC1 VSS_E7
VSS_E6
54
53 C509
16V
100n

3
RAS-_L1 VSS_E5
6 133 45
RAS# R3 CS-_M1 VSS_D9 25V C515
BA0 R518 135 43 10n
33R BA0_M3 VSS_D7 16V
4 5 124 42 100n
CS0# R4 BA1_L4 VSS_D6
MA[11] 126 40
A11_L6 VSS_D4 C510
MA[10] 113 104
BA1 R519 A10_K5 VSS_J8 25V C504
MA[9] 127 103 10n
33R A9_L7 VSS_J7 16V
MA[8] 142 102 100n
A8/AP_M10 VSS_J6
MA[7] 141 101
R520

R521

A7_M9 VSS_J5 C511


33R

33R

MA[0-11]

MA[6] 140 117


A6_M8 VSS_K9 C503
MA[5] 128 112
A5_L8 VSS_K4 25V 16V
MA[4] 139 105 10n 100n
A4_M7 VSQ_J9
MA[3] 138 93
A3_M6 VSSQ_H9
MA[2] 125 100
A2_L5 VSSQ_J4 C512 C2253
MA[1] 137 88
A1_M5 VSSQ_H4 25V 16V
MA[0] 136 81 10n 100n
A0_M4 VSSQ_G9

VSSQ_C10
VSSQ_A10
DQS2_G1
DQ20_H2
DQ21_H1

VSSQ_D5

VSSQ_G4
VSSQ_D8
DQS0_A1

VSSQ_C3
VSSQ_C4
VSSQ_C5
VSSQ_C8
VSSQ_C9
VSSQ_A3
DQ16_E2
DQ17_E1

VSSQ_E4
VSSQ_E9
DQ18_F2
DQ19_F1

VSSQ_F4
VSSQ_F9
DQ22_J1
DQ23_J2

DM2_G2
DQ7_D1

DM0_A2
DQ5_C2
DQ6_C1
DQ4_B1
DQ1_B5
DQ0_A6

DQ2_A5
DQ3_A4

NC_L12
C513 C2252
DQM[0] 25V
DQM[0-3]

DQM[1] 10n 16V


DQM[2] 100n
DQM[3] 132 C514
74
97
98
86
85
62
61
37
50
49
13
26
25
17

73

10
27
28
29
32
33
34
41
44
52
57
64
69
76
2

1
6

5
4

3 25V C2251
10n 16V
100n

C519
DQM[1]
DQM[0]
DDQS1
DDQS0

MCLK0 R2209 MCLK01 25V C2250


10R 10n 16V
R2 7

R3 6

R4 5

100n
R506

18 R1
10R

R504
C520

47R

BLM21B201S

BLM21B201S
C526
2

R2 7

R3 6

R4 5

C500
R507

L501

L500
18 R1
10R

10n
2

R2 7

R3 6

R4 5

R2 7

R3 6

R4 5
R509

R511

R505
25V
18 R1

18 R1
10R

10R

47R
MD[15]

MD[14]

MD[13]

MD[12]

MD[11]

MD[10]

4
MD[9]

MD[8]

MD[7]

MD[6]

MD[5]

MD[4]

MD[3]

MD[2]

MD[1]

MD[0]

R2208 VDDMQ_2V5 VCCA_2V5


10R
MCLK0# MCLK01#

SM012 MAIN BOARD - DDR RAM CIRCUIT


64
1 NC1 NC10 44

2 NC2 NC9 43

PWM

PWM2
MCA[0]

RD_EMU
MCA[0] 3 NC8 42

WR_EMU
0

GAL_IAP
PSEN_UP

S412

S414
MCA[19]
MCA[18]
MCA[17]
R415 MCA[1] MCA[19]
1k2
MCA[1] 4 A1 A18 41 MCA[19]

VCCA_2V5

22R
S621
S620

R412
50V MCA[2] MCA[18]

S622
10u
MCA[2] 5 A2 A17 40 MCA[18]

8
7
6
5
4
C416
MCA[3] MCA[17]
R416

I6
I5
I4
I3
I2
4k7 MCA[3] 6 A3 A16 39 MCA[17]

VCC_5V
MCA[16]

Q400
MCA[4]

BC337
22R
R417
16V MCA[4] 7 A4 A15 38 MCA[16]
100u
MCA[16]

SM012
9 I7 I1 3 MCA[16]
MCA[15]
C417 MCA[15] S623
MCA[15] 8 CS OE 37
10 GND I0 2 MCA[15]
C419
MCA[14]

SRAM_OE
11 OE CLK 1 MCA[14] MCAD[0] MCAD[7]
100n
16V MCAD[0] 9 I/O1 I/O8 36 MCAD[7]
12 Q0 VCC 20

IC622
13 Q1 Q7 19 MCAD[1] MCAD[6]

GAL16LV8
MCAD[1] 10 I/O2 I/O7 35 MCAD[6]

IR

BRIGHTNESS CONTROL
11 VCC VSS1 34

BRT_CNTL
FL_A14
FL_A15
Q2
Q3
Q4
Q5
Q6
STBY_3V3
16V
16V

C600
C601

100n
100n

14
15
16
17
18
12 VSS VCC1 33

STBY_3V3

4k7
STBY_3V3

R604
LED1 R6018 MCAD[2] MCAD[5]
22k BC848B
5 MCAD[2] 13 I/O3 I/O6 32 MCAD[5]

STBY_5V
Q6006

FL_OE
K6R4008V1C-I/C-P
4

FL_A16
FL_A17
FL_WE
MCAD[3] MCAD[4]

SRAM_OE
R6019

SRAM_WE
22k BC848B 3 MCAD[3] 14 I/O4 I/O5 31 MCAD[4]
Q6007 S6300
LED2
2
MCA[14]
S624
S6310 1 15 WE A14 30 MCA[14]

SRAM_WE
PL600
MCA[5] MCA[13]

220R
R6015
MCA[5] 16 A5 A13 29 MCA[13]

220R
R6016
MCA[6] MCA[12]
MCA[6] 17 A6 A12 28 MCA[12]
S6312 S6311
STBY_5V STBY_3V3
PL607
MCA[19] MCA[7] MCA[11]
12 MCA[19] MCA[7] 18 A7 A11 27 MCA[11]
MCA[18]

3 4 MCA[18]
MCA[17] MCA[8] MCA[10]
56 MCA[17] MCA[8] 19 A8 A10 26 MCA[10]
CIRCUIT OF SW UPDATE FROM SCART2 MCA[16]

7 8 MCA[16]
MCA[0] MCAD[0] MCA[9]
MCA[0] 9 10 MCAD[0] MCA[9] 20 A9 NC7 25
S605 S6315 MCA[1] MCAD[1]
MCA[1] 11 12 MCAD[1]
MCA[2] MCAD[2]
SCSCL 100R MCA[2] 13 14 MCAD[2] 21 NC3 NC6 24

SCL3
R6006 MCA[3] MCAD[3]
MCA[3] 15 16 MCAD[3]
MCA[4] MCAD[4]

4k7
R600
Q600

10k
MCA[4] MCAD[4] 22 NC4 NC5 23

Q604
17 18

R6007
MCA[5] MCAD[5]
MCA[5] 19 20 MCAD[5]
R6005 MCA[6] MCAD[6]
STBY_5V IC217
47k MCA[6] 21 22 MCAD[6]
MCA[7] MCAD[7]
MCA[7] MCAD[7]

SW_ENABLE
23 24
MCA[8]

Q605

10k
4k7
25 26 MCA[8]

Q601
R601

R6010
MCA[9]
STBY_3V3 27 28 MCA[9]
SCSDA 100R MCA[10]

SDA3
R6011
MCA[0]
MCA[1]
MCA[2]
MCA[3]
MCA[4]
MCA[5]
MCA[6]
MCA[7]

S606 S6316
MCAD[0]

29 30 MCA[10]
MCA[11]
31 32 MCA[11]
MCA[12]
33 34 MCA[12]
MCA[13]

35 36 MCA[13]
MCA[7]

MCA[1]
MCA[2]
MCA[3]
MCA[5]
MCA[6]

MCA[0]

MCA[14]

37 38 MCA[14]
MCA[15]
MCA[15]
MCA[4]

39 40

41 42 FL_OE
S6320
PSEN_UP

Q602
MCAD[0]

43 44

BSN20
100R

SCL
SRAM_OE

SCL3
R606 45 46
S6319
9A
8A
7A
6A
5A
FL_A16

FL_A15

47 48 RD_EMU
12 A0
11 A1
10 A2
3
4
5
6
7

13 DQ0

10k
SRAM_WE

R607
49 50
S6318
VCCA_3V3
51 52 WR_EMU MCAD[1] MCA[12]
STBY_5V
MCAD[1] 14 DQ1 A12 4
53 54 STBY_3V3 MCAD[2] MCA[12]
S6317
MCAD[2] 15 DQ2 A15 3

10k
RST#

R610
55 56
16 VSS A16 2
57 58 ALE_EMU MCAD[3]
100R MCAD[3] 17 DQ3 A18 1
MCA[18]

SDA
MCA[18]

SDA3
R611 59 60 MCAD[4]
ST M29F040 Flash
CORRESPONDS TO

LEVEL SHIFTER
MCAD[4] 18 DQ4 VCC 32 STBY_3V3

BSN20
Q603
MCAD[5]
IC219

MCAD[5] W
25V

19 DQ5 31
100n

MCAD[6]
Winbound W27E040 EPROM &
M29W040B

MCAD[6] 20 DQ6 A17 30


C605

S604

DQ7 21
E 22
A10 23
G 24
A11 25
A9 26
A8 27
A13 28
A14 29

E2
5 SDA SDA2 VSS 4
FL_WE

FL_A17

SCL2

65
6 SCL A2 3
MCAD[7]
FL_A14

FL_OE

24LC32A
MCA[10]
MCA[9]
MCA[8]

MCA[11]
MCA[13]

7WP A1 2
NVM_WP

S603

STBY_3V3
8 VCC A0 1
MCAD[7]

VCCD3.3V_FLT
MCA[0]
MCA[1]
MCA[2]
MCA[10]
MCA[9]
MCA[8]

C603
S602
MCA[10]
MCA[11]
MCA[13]

SCL2
SDA2

100u
16V

16V
C604
100n

IC218
MCAD[5]
MCAD[0]
MCAD[6]
MCAD[7]

S608
S607

VCCA_3V3
MCA[3]
MCA[5]
MCA[4]
MCA[9]
MCA[6]
MCA[8]
MCA[7]

MCA[0]
MCA[1]
MCA[2]
MCA[11]

MCA[10]

MCAD[5]
MCAD[0]
MCAD[6]
MCAD[7]
PSEN_UP

SCL3
SDA3
ALE_EMU

8
7
6
5

25V
MCA[3]
MCA[5]
MCA[4]
MCA[9]
MCA[6]
MCA[8]
MCA[7]

100n
R1
R2
R3
R4
MCA[11]

4
3
2
10R
R625

18
1
2
3
4
5
6
7
8
5
6
7
8

R4
R3
R2
R1

C606
10R
R624
R3
R2
R1
R4
R3
R2
R1

5
6
7
10R
10R

R626
R627

R4 4
3
2
1
4
3
2
1

1k
R6037

PDP_GO1/BL_ON_OFF

R629
10R MCA[13]
18 R1 MCA[13]
S600

STBY_3V3
Q6009

MCA[12]
BC848B

4k7 2 R2 7
MCA[12]
97 A0
94 A1
93 A2
89 A3
86 A4
84 A5
83 A9
82 A6
81 A8

100 D5
99 D0
98 D6
96 D7

R6035 MCA[14]
87 ALE

90 A10
85 A11

LOC_KEY

3 R3 6 MCA[14]
88 PSEN

91 VSS3

95 FL_CE

10R MCA[15]
MCAD[1] 4 R4 5
D600

R628 MCA[15]
92 VDD3_3_3

MCAD[1] R4
BZT55C5V1

5 4 1D 1 FL_RST 80
MCAD[4]

MCAD[4] R3
6 3 2D 4 A7 79
MCAD[2]
CPU_GO1/STBY
1k

1
2

MCAD[2] R2
R6038

7 2 3D 2 A13 78
MCAD[3]
PL606
PDP_GO/BL_ON_OFF

STBY_3V3 MCAD[3]
R1
R6036 8 1 4D 3 A12 77
STBY_3V3

4k7
L600
5 XROM A14 76
STBY_2V5

L601

3
2
1

VCCD3.3V_FLT
6 VDD2_5 VDD3_3_2 75
PL604
Q6008
BLM21B201S
C613
100n

BC848B
50V
25V
16V
100n

22u
C610

C607
C608
100n

7 VSS VSS2 74
25V
C609

100n

22u

R688
CPU_GO
STBY_3V3

25V

8 VDD3_3 VDD2_5_1 73
C611
C612
100n

STBY_3V3 4k7
STBY_2V5
SDA2
4k7

9 P0_0 FL_PGM 72
R632

SDA SCL
R689 4k7
SCL2 10 P0_1 A15 71 R639
10R MCA[17]
R6030 4k7 18 R1
R6013
MAIN BOARD - MCU INTERFACE CIRCUIT

MCA[17]
AC_INFO 47R 11 P0_2 A17 70 MCA[16]
R690
R6031 4k7 2 R2 7
MCA[16]
MUTE_AMP 47R 12 P0_3 A16 69 MCA[18]
R694 4k7 3 R3 6
MCA[18]
RX1_RST# 13 P0_4 A18 68 MCA[19]
WR_EMU

R695 4k7 4 R4 5 MCA[19]


RX1_INT 14 P0_5 A19 67
R696 4k7
RD_EMU R640 STBY_3V3
CPU_GO1/STBY 15 P0_6 NC5 66
4k7
15k
UP_IRQ

C615
UP_TXD

R698
UP_RXD

16 P0_7 RD 65
DVD_12V_SENSE 100n
S610
3k9

17 ENE WR 64
R697
IC220

S615 18 STOP NC4 63


STBY_3V3
R648
S627
S628
S629
SDA5550M

19 OCF P1_7 62 4k7

20 EXTIF NC3 61
4
3
2
1

21 CVBS R6042 S601


PL308

R684 1k
STBY_2V5
UART SOCKET FOR IDTV

22 VDDA2_5 75R
L603
R685
25V

C621
100n

R6043
50V
22u

VSSA
C620

23 75R
4k7
R686
PIN8_SC1 15k 24 P2_0 75R
STBY_3V3

R654 L604
STBY_2V5
Q6011

25 P2_1 VDDA2_5_1 56
BC848B

25V

3k9
R653
C622
100n
25V

26 P2_2 VSSA1 55
C623
100n

PIN8_SC2 15k
2
1

15k 27 P2_3 NC2 54 50V


R655
R656 33p
PL605
25V

3k9 28 NC XTAL1 53
RST_H

C625
100n
25V

3k9
R660
C626
100n

R657
C624
29 HS_SSC XTAL2 52
LOC_KEY
X600
6MHz

R2305 C627
10k STBY_2V5 1k
R661
30 VS NC1 51
BC848B 50V
Q2299 33p
MMC_IR GIRISI
25V
100n
C628
RST

VSS1

P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P4_2
P4_3

100R

PIN8_SC3
R2306
31
32
33
34
35
36
37
38
39
VDD3_3_1 40
41
42
43
44
45
46
47
48
49
50
STBY_3V3

25V
IR
VCC_8V
S6313

100n 25V
C633
100n

100n
VCCD3.3V_FLT

BC848B
4k7

Q6010

R6040
4k7
R6014

R692

4k7
4k7

C630
R691
4k7

C631
R693

VCCD3.3V_FLT
RST#
3

R679
PC_STBY
1

4k7
100R
IC221

R6039
L609

4k7
LM809 2

STBY_5V

STBY_3V3 R680
STBY_3V3

VCCA_2V5
BLM21B201S

4k7
S614 R681 100k 4k7
R2301
R687 R676
VCCD_3V3

47k 4k7
Q2300
SC2_FB

R682
BC848B
TV-LINK

R6017
10k

S613
R2303

4k7
SDA_TVLINK
FB

R2304
100R R6041
TV_LINK 4k7
RST#

Q2301 R2302 S6314


2k7
VCCD_3V3

BC848B 47k HDMI_CEC R6044


R2300

4k7
IR
PROTECT
PORT

SDA_TVLINK
PDP_GO1/BL_ON_OFF

NVM_WP
GAL_IAP

UP_IRQ

UP_TXD
LED2
SDA3
SCL3
INT#

PWM

LED1

STBY_3V3
UP_RXD
STBY_3V3
IC3000
HDMI_3V3 LM1117
P1_5V

P1_EVCC5
IN OUT 2

R2066

R2067
VCC_5V 3 HDMI_3V3_PLL

470k

470k

R2070
GNDVOUT

1k
C3000 C3001 1 4
100n 100u 100n C3003 C3004
16V 16V 16V 100n 100u
DSDA C3002
16V 16V
1 S1 D1 6 P1_HPD

R2069
IC2013

C2072

R2062

10k
S1

100n
1 D1 6

4k7
25V
VCC_5V 4k7 2 G1 G2 5
IC2012 IC3001

R2063
R2068

47k
RX1_RST# LM1117

2 G1 G2 5 DSCL
UPA672T VCC_5V 3 IN OUT 2 HDMI_3V3
GNDVOUT
R2098 D2 C3005 C3006 1 4
Q2 3 S2 4
1 A0 VCC 8 BC848B 100R SW_ENABLE UPA672T 100n
16V
100u
16V
100n
16V
C3008
100n
C3009
100u
C3007 16V 16V
3 D2 S2 4

AUDIO_AGND

AUDIO_AGND
2 A1 WP 7
IC2003
24LC02 DIN[0-23]
3 A2 SCL 6

AMP_PIN7
DIN[10]

DIN[11]

DIN[12]

DIN[13]

DIN[14]

DIN[15]

DIN[16]

DIN[17]

DIN[18]

DIN[19]

DIN[20]

DIN[21]

DIN[22]

DIN[23]
DIN[8]

DIN[9]

DIN[0]

DIN[1]

DIN[2]

DIN[3]

DIN[4]

DIN[5]

DIN[6]

DIN[7]
HDMI_3V3_PLL
R2064
P1_DDC_SCL 56R
4 VSS SDA 5

C2100

R2088
100k
2n7
50V
R2 7

R3 6

R4 5

R2 7

R3 6

R4 5
R2052

R2050
R2065

18 R1

18 R1
33R

33R
P1_DDC_SDA 56R

SDA3

SCL3
C2101

4
DAC_AOR 560R

R2 7

R3 6

R4 5

R2 7

R3 6

R4 5
R2051

R2049
R2087 R2091

18 R1

18 R1
10u

33R

33R
RX1_RST#
25V 50V 20k AUDIO_AGND

OGND_SII

OGND_SII
RX1_INT
100n

0VCC_SII

0VCC_SII
GND_SII

VCC_SII

AMP_PIN6
AUDIO_AVCC5
S818

S819
60R_100MHZ_3A
C2103
C2068

R2053
AUDIO_AGND

Place close to pins 79&80

4k7
L2014
10u
50V
C2104
25V AUDIO_AGND

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

Q7 59

Q8 58

OGND3 57

OVCC3 56

Q13 51
C2069 100n C2102

Q9 55

Q10 54

Q11 53

Q12 52
100n R2089
AUDIO_AGND 25V 47k

Q1

GND3

VCC3

Q3

Q5
RSVDL2

Q0

Q2

Q6
OVCC4

OGND4

Q4
CSDA

CSCL

RESET

INT
10u C2099 270p R2090 AUDIO_AVCC5
50V 50V 47k
C2070

5
H

E
F
100n CLK_2EX
TP100

25V DSDA 76 DSDA Q14 50

AMP_PIN3
C2071
R2094
DSCL 77 DSCL Q15 49 33R
1n
50V OGND_SII 78 OGND5 Q16 48
MC33202
IC2008
19 P1_HPD 79 PGND1 OVCC2 47 0VCC_SII
R2048
18 P1_CBL5V 80 PVCC1 ODCK 46 33R
R2047

D
C
A

B
33R
18 R1
17 RX1_AVCC3 81 EXT_RES OGND2 45 OGND_SII

4
2 7
16 P1_DDC_SDA AVCC_SII 82 AVCC Q17 44 R2
50V
3 6 10u C2093
15 P1_DDC_SCL 83 RXC- Q18 43 R3 R2081 AUDIO_AGND

AMP_PIN3
S817 DAC_AOL 560R

AMP_PIN6

AMP_PIN7
4 5
14 84 RXC+ Q19 42 R4 C2092 270p

C2091

R2080
100k
50V

2n7
S816

50V
13 CEC 85 AGND1 GND2 41 GND_SII
S815 AGND_SII

12 86 RX0- VCC2 40 VCC_SII


R2046
S814 33R
18 R1
11 87 RX0+ Q20 39

AUDIO_AGND

AUDIO_AGND

R2085

R2086
IC2002

1k2

5k6
2 7
10 AGND_SII 88 AGND2 Q21 38 R2

R2078

R2079
SII9993

5k6

1k2
3 6 C2098
9 AVCC_SII 89 AVCC1 Q22 37 R3
AUDIO_AGND
4 5 C2090
8 AGND_SII 90 AGND3 Q23 36 R4 2n7

R2084
S813 R2045 AUDIO_AGND 50V

4k7
7 91 RX1- DE 35 33R DE_2EX 2n7

R2077

AUDIO_AVCC5
50V

AUDIO_AGND
S812 R2044

4k7
C2097
6 92 RX1+ VSYNC 34 33R DVS_2EX
S811 R2043 AUDIO_AGND
C2089
5 AVCC_SII 93 AVCC2 HSYNC 33 R2042
33R DHS_2EX 2n7
S810 33R AUDIO_AGND 50V

R2082

R2083
18 R1
94 AGND4 SCK 32

2k32

2k32
AGND_SII DAC_SCK
4 2n7
50V

5
R2075

R2076
2 7
95 AVCC3 WS 31

2k32

2k32
3 AVCC_SII R2 DAC_WS
C2095
3

C2096
6
2 96 RX2- SDO 30 R3 DAC_SD0

3u3
50V
10u

C2088
4 5
1 97 RX2+ SPDIF 29 R4 50V R2074

3u3
50V
25V 270k AUDIO_AGND

AOUTR
PL2001 100n
AGND_SII 98 AGND5 OGND1 28 OGND_SII R2073
R2040 R2041 AUDIO_AGND 270k
GND_SII 99 GND4 MCLKIN 27 33R 33R DAC_MCLK C2094

6
DACGNDR

DACGNDG
DACVCCR

100 VCC4 MCLKOUT 26


DACGNDB

VCC_SII
DACVCCG

DACVCCB
DACGND
DACVCC

RSVDO1

RSVDO2
RSVDL1
ANRPR

PGND2
ANBPB

PVCC2
COMP

GND1

VA
RSET

ANGY

PLLIN
OVCC
VCC1

CS4334
IC2006
NC1

NC2

NC3

AOUTL

LRCK AGND
HDMI_3V3

DEM/SCLK
10

11

12

13

14

15

16

17

18

19

20

25
21

22

23

24
1

SDATA

MCLK
R2035
RX1_AVCC3

100R

60R_100MHZ_3A
R2038
TOCOMP

HDMI_3V3 Place PLL circuit as

0VCC_SII
4k7
VCC_SII
C2054

C2055

C2056

C2057

C2058

C2059

compact and as close to


100n

100n

100n

L2012 50V
10u
25V

HDMI_3V3
1n

1n

1n chip as possible 25V

VCC_5V

4
10u
GND_SII

C2062 3k9
Close to pin9 25V R2039
C2067
100n 25V
47n
IC2014
Place close to pins 22&23

DAC_MCLK
S805

DAC_WS
DAC_SD0

DAC_SCK
C2063
C2060

S809

S808
50V C2066
10u
1 1OE A8 8
60R_100MHZ_3A

R2095
HDMI_3V3 AVCC_SII L2016 10n

10k
60R_100MHZ_3A
C2073

C2074

C2075

C2076

C2077
100n

100n

100n

L2015 VCC_5V AUDIO_AVCC5 25V TOCOMP


10u

C2064
25V

16V

25V

25V

50V

330R_100MHZ_3A
1n

C2061

R2097

R2096
L2013

21 A 2OE 7

330k
S800

27k
AGND_SII L2017 10u
AUDIO_AGND 16V
VCC_5V

330R_100MHZ_3A Place cap.s


S807
close to C2065 HDMI_CEC
S801 31 B 2B 6
HDMI_3V3 VCC_SII pin8
Q1
C2078

C2079

C2080

C2081

C2082

2N7002
100n

100n

P1_5V
10u

100n
16V

25V

25V

50V

50V
1n

1n

25V
S802 4A 4 2A 5
1N5817

D2022

GND_SII HDMI_3V3_PLL

R2071 D2021 SN74CB3Q3305


S803 P1_CBL5V 10R P1_EVCC5 S806
BZT55C5V6

HDMI_3V3 0VCC_SII 1N5817 CEC


2
A D2020K

BZT55C5V6
C2083

C2084

C2085

C2086

C2087
100n

100n
10u
16V

25V

25V

50V

50V
1n

1n

D2023
S804
1

OGND_SII

SM012 MAIN BOARD - HDMI/DAC CIRCUIT


66
L918
PL903
VCC_12V

PL904
VCC_5V
1

1
PANEL_VCC1 S908

PL902
L917 VCCA_3V3
VCCA_3V3 2

7
S909
STBY_3V3
3 S910
STBY_5V
L906
5V
PDP_GO1/BL_ON_OFF LG_1/IRQPDP 4 MMC

VCC_12V
100u

C900
16V
SUPPLY
5V
AC_INFO

PL900 L909 STBY_5V


N.C
S903
STBY_5V STBY_3V3

S904
1 FAN1616AS-3.3 D905
L905 SOT 223 L923
L913
2 +12V IC902 1N4007
3 2 STBY_2V5 10u
L920 D906

1000u

100n

220u
C906

C908

C920
3 C916 1

16V

50V

16V
220u

C914
16V
100n
L900 16V 1N4007 IC904

L907
4
L901 R918
5 1 SW.COLL. DRI.COL. 8
L902 LM317
IC900
6

R916
100R

R917
100R
STBY_3V3 2 EMITTER SENSE 7
C942

R922
L903 3I N OUT 2

3k3
ADJ
7 C901 1 3 CAP. VCC 6

47u
C904

50V

R914
L904 VCC_8V 56p

10k
100n
8 16V 4 GND COMP. 5

100p
C944
R902 C910
9

R907
1k 100n

10k
C909
MC34063A

47u
16V

50V

VCC_12V
10

1N4148
R912 D907

D912
R903
BC858B

5k6
10k VCC_5V
PROTECT Q901
11 1N4148 56k
R908 R921
Q900 D908
12 BC848B 10k C945
VCCA_3V3

R910

R920

R919
1.8V_ON/OFF

10k

6k8

2k2
1N4148
L919
VCC_5V D909 22u
22u 1000u

100n

100n

100n

100n
C912
C932

C933

C934

C935
C903 100n VCCD_3V3
16V

N.C 56p
1N4148
R900 CS52015-3
STBY_3V3 470R IC901 D910
C943

PANEL_VCC1

PANEL_VCC
VCC_8V

L924

22u
47u 3 VIN VOUT2
R901 GND 1N4148
1 C919

100u

C931
470R C915

16V

R909
120R
C902 L912 100u
100n 16V
16V VDDMQ_2V5
C922

100n

22u C917
N.C D900

16V
100n
16V R915 10u

STBY_2V5
PL901

C918
1N4007 470R STBY_2V5 C946

50V
PDP_GO/BL_ON_OFF 120R 1R N.C
1 D901 R911 R913 S907

A_DIM_PWM 2 1N4007

VCC_33V
L921

6
DIG_DIM_PWM 3 D902 SOT 223
BLM21B201S

FDC642P
IC223 IC903
3 LD1117 2 VCCA_2V5

Q902
SEL 4 1N4007 L922

R925
1

10k
1N4148
C921

47u
C923

50V
LM2576

D913
D903 BLM21B201S
FEEDBACK

PROTECT 5 100n
16V
OUTPUT

ON/OFF

1N4007

34
6

1
CPU_GO1/STBY SAP 30030067 ADJ TYPE
VCCA_3V3

D914
GND
VIN

VCC_33V 7 L915 C947


1_8VMAIN
S905

100n

100n

100u
C925

C936

C939
22u
8

16V

16V
16V
100u

C927

330R
R923
VCC_12V 1.8V_ON/OFF 10u

16V
VL1_8
1

S911 16V
S913
9
VCCD_3V3

R905 S902 Q903

S912
L908
D915

PORT 160R 1_8VMAIN


10 VCC_12V
22u R904 L914 VD1_8
L911
330R 1_8VMAIN
100u

100n

100n

100u
C905

C924

C937

C940
22u
16V

16V

16V
16V
100u

C928
22uH_3.9A_SMD

16V

R924
L910

10k
S900
STPS745

A_DIM_PWM BRT_CNTL 22u


SS33
D911

VA1_8
1000u
D904

100n
C911
C913

S901 L916
16V

16V

DIG_DIM_PWM 1_8VMAIN

100n

100u

100n

100u
C926

C929

C930
C938

C941
22u

22u
16V

16V
16V
PANEL_VCC_ON/OFF

SM012 MAIN BOARD - POWER SUPPLY CIRCUIT


67
SM012
4
3
2
1

PL700
1 VIN

35V
470u D901

N.C
22u
2 OUTPUT

L729
C821

S730
STPS745 D904
SS33 3 GND
IC708

22u
LM2576

L904
L109

4 FEEDBACK
25V
1000u
22uH_3.9A_SMD

1
2
25V
22u
L727

1000u

PL702
C822 5 ON/OFF
C820

R754 R755
C808 C807 1k8 22k
C826

470n 470n
63V 63V 100n
25V

L726

40uH
L725

40uH

C815 C816
15V_AUD

15V_AUD

15V_AUD
100n 100n
25V 25V
50V 50V
1n 1n

C796 C795
L721

L722

C803
50R_100MHZ_3A

50R_100MHZ_3A

50V 220u 50V


10n 25V 10n

C818
C794 C793
C802 C801

22n
50V 100n 100n
2 50V 50V
R766 R767
12k 3k3

PL707
1

vcc 5v
24
23
22
21
20
19
18
17
16
15
14
13

S737
Q709
BSLP
BSLN

BC848B
C817 1u
PVCCL4
PVCCL3
PVCCL2
PVCCL1

LOUTP2
LOUTP1
LOUTN2
LOUTN1

PGNDL2
PGNDL1

16V

25 VCLAMPL REFGND 12 33k


22n
50V C792 R745

26 AGND1 VOLUME 11
S723
S724

1
R742

IC703
2 LM809
120k 27 ROSC VARMAX 10

68
C779

3
220p 50V
R756 28 COSC VARDIFF 9
100k 25V
100n 50V
1k

S732

100u 18k
29 AVDD VREF 8
R770

R746
C778
C811 30 AGND2 AVDDREF 7
1u

S734 S733 31 VAROUTL LINN 6 MAIN_OUT_L 1


1u
C790
IC702

32 VAROUTR LINP 5 2
1u
C789
Q710

33 AVCC V2P5 4 3
TPA3004D2

1u
BC848B

MUTE_3V3
C791
MUTE 34 MODE RINP 3 4
1u
C788
RESET OUT

35 MODE_OUT RINN 2 MAIN_OUT_R 5


C776
C787
36 VCLAMPR SD_NOT 1
1u
S736
1k

15V_AUD 16V
PL701

R771

C824
S735
BSRP
PVCCR4

PVCCR2
ROUTP2
PGNDR2
ROUTN2
PVCCR3
BSRN

PVCCR1
ROUTP1
PGNDR1
ROUTN1

100n 50V
9k1

100n
R768

25V
HIGH=ON
LOW=OFF

37
38
39
40
41
42
43
44
45
46
47
48
Q715

BC848B

S738 C777
MUTE_3V3

25V
220u
Q604
Q603

50V 50V
BSN20
BSN20

C775
100n 100n
S739

4k
25V

C825
100n
R772

50V C783 C782 50V


MUTE

10n C813 10n R773


3k3
C814 R765
C781 100n C780
25V 25V 12k
220u C823
100n
25V 100n
25V
C784
L719
L718

15V_AUD

50V 50V
15V_AUD

1n 1n
50R_100MHZ_3A
50R_100MHZ_3A

C786 C785
AMPLIFIER BOARD - D-CLASS AMPLIFIER CIRCUIT
L724
L723

40uH
40uH

15V_AUD
15V_AUD

C806 C805

470n 470n
63V 63V
PL703

2
1
2

D100
1

33p
50V
C100
BZT55C10
4P

L101 L100
JK100
4

SVHS_Y
600R_100MHZ_200mA

SM012
BZT55C10

33p
50V
C101
D101

L103 L102
SVHS_C

S100
PL103
S101
BZT55C10

1
C102

33p
50V
D102

L105 L104
2

FRONT_VIDEO
3
A
JK101

1
YELLOW_FAV

PL100
PL104
1 FRONT_VIDEO
50V
BZT55C10

100p
C103

1
D103

R100 L107 L106


R109 2
2

FRONT_AUDIO_R
2 R107
3

SVHS_C
A

SVHS_C R110 3
JK102

3 R108
SVHS_Y 4 SVHS_Y
4
1P_RED_FAV

5
FRONT_VIDEO 5
6 FRONT_AUDIO_R
50V
BZT55C10

100p
C104

6
D104

7 R101 L109 L108


2

FRONT_AUDIO_L
FRONT_AUDIO_R 7
3
A

8 FRONT_AUDIO_L
JK103

FRONT_AUDIO_L 8
WHITE_FAV

9 PL102

LINE_OUT_R 10 1 LINE_OUT_R
L110

LINE_OUT_L 11 2 HEADPHONE

9 6
50V

69
100p

LINE_OUT_SUB 12 3 LINE_OUT_L
C105

8 5
4 LINE_OUT_SUB
R102 L112
7 4
HP_R
D105

L111
BZT55C10

PL105 PL101 3
4n7
50V
C106

2
HP_R 1 1 HP_R 1

R103
4n7
50V
C107

2 2
JK104

HP_L
PHJACK

L114 L113
HP_L 3 3 HP_L

HEADPHONE 4 4 HEADPHONE
D106
BZT55C10

FRONT AV BOARD CIRCUIT


D107

50V
100p
BZT55C10

C108

R104
2

LINE_OUT_SUB
L116 L115
3
A
JK105

1
WHITE_FAV

D108

50V
100p
C109
BZT55C10

R105
2

LINE_OUT_L
L118 L117
3
A
JK106

1
WHITE_FAV

D109

50V
100p
C110
BZT55C10

R106
2

LINE_OUT_R
L120 L119
3
A
JK107

1
1P_RED_FAV
19.3. CIRCUIT BOARDS
1 2 3

1. Y-SUS Board (TS06288) 6. IDTV Board 17DB23 (VS20252456)

2. Power Board (VS30043468) 8 7 6 4&5

7. Main Board 17MB15-E5 (VS20251818)


4. Audio Board 18AMP05 (VS20217003)

8. Joint Board 17DB21 (VS20252456)


3. X-SUS Board (TS06287) 5. Filter Board 17FL2-02 (VS20225622)

SM012 CIRCUIT BOARDS


70
19.4 PCB LAYOUTS
17PING08
VER:E2

PL707

C807
L725 006LP
18/06/04

PL101
L726
C61

C836

C805

PL702
101LP

C315
S305
14C

C829

C834

L108
C833

C877

L110
L119
L111
PL700
VpRxD
C821 IC5 L14 C256R136
PL106

S304
S302
L729
R126

C257
L13
S303
C52 V3.3

R121
R59 C133

R148
C51 V5

IC103
R774

S301
C600
R19

C602
C811
C604 PL600
L12 L16 331C DNG

C307

C310
C305
C308
C50
C820 5V IC501

601LP
C311

R119 C118
C603
DNG

C601
C37

C605
R123
R775 C837
C53 35C V21

R118
C606

C122
R530 C110 V33

C828
C830
C111 313C 71L
V5.2

C831

IC902
C832

PL703
431C
D901

R120
IC647 IC648 IC545 C134 D180

C806
L904
D101 C114 C25
413C

R631
R603
C117 001X

C510
R502

R532
S1
C835

C475 574C

X100
L727
R136 R318
C805

C312
R137 C130 PL100 301C
L723
L724 IC600 C103
L105

L112

R122
L106 C119 R747
R747R746R745R744R312R311 L15 633R
C486 231C

C120
IC402
R128 684C 733R
C822

IC102
R657 C707 R319 R115
PL701 IC100 R110 S2 C132 TUOREGGIRT
L10 701L
C128 L113 841R NIREGGIRT
321C

R743
C452 R604 R662 C126

SDA C1
SDA C2
R127 301R 511C

R742
251R 303CI

R741

R114
R659 2.5V C305
BOTTOM (SOLDER) SIDE 5MT

C479

101LP
R661 R660 254C

C456

R740
601R

R510 R658
503R

C129
KCT

S401
TOP (COMPONENT) SIDE C124 674C 151R
001R 603R JOT

R500 Q600
9L
121C

R459
C509 R310 ODT

R112
513C

R113
R645 C601
C476 R146 R300 003C 303C
C822 PL741 SDA
R444
18AMP05-2 C485
R443 C608 C651 R652
11L TSRCATJ
R771

C437 784C
L610 TSRT

R159
403C
121205 3.3V C438 R108 103PT
R102 584C 211C 7L
L727
C714
LF L413 R160
C127 R144 603C 4203C
R777

R776

24

L109 L723 R466 C439 634C 654R


S7

L724 C422 103C

C252
Q120
L904 R161 IC300 534C 8L
R125
X400 C434

531R
201R
101R
C440
PL703 474C
C806 R222 Q121 814R 294C

R550
R569
R553
R771 L103 L102 IC201 334C
R105 C131 311C
D904 C470 844R

C295
C125
D901 C782 C469 C404 R139 744R

C473
C135

C488
C785 C786 C825 R468 C102 C255 001X
C491 IC401
L719

632C

C104
C116
C835 R772 C423 R467 R407 R400 Q403 R104 R338 R339 914R
C236 C212
L718

R307
R308
Q715

C218 034C
S514 R221 731C

C446
C421
C489

C408
R754 531C

C426

S402
C824

L101

L402
S736

C820 C402 212C


S739 C781 R231 L220
C780

C429 C428 C415 R409 L207 C137


C823
R773
R765

R775 C787 C815 L412 004L


L400 C445 Q401

C220
R232
S735

R411 C420 C414 R201 R290 L206 C205 C211 184C

C462
L411
C788 R408
C816

IC702

C472
274C
C771

C481
C783

L221
R413 R405

R450
C459
C791 D402

R410

R203
L404
Q603

R404 R452 R431 R432


C789 C202
S725

D400

R411
R774 484C

S406 C464

202LP
PL202
C790 C200 112C
C409
Q6

C405
Q402 L205

L222
C205 004Z
04

C416

R204
R746 C460 D401 C459 014C 354C

L623
C831
R403 Q400 R402 C203

C412
R428
R470
R745 R475 R415 C463

R205
Z400
R755 R754 C821 R451 R202

C411
C414
C794

C811 004UT
C410

R449
C461
C464
C793 C814

R401
L401
S515
C493

L216
L219
L208
L209
L210

L212
L213
L214
L218
L215
L211
C776
C801

L729 C813 S513 L204


S738 C491 C22 604C
C406 394C
C826

C207
C802

PL700 C834 C778


C779 TU400
L721

R742
C786
C795

L722

C792 L217 504L


L605 854C 084C 144R

C403

R263
C401 C457
C808 C255 IC101 302LP
PL702 R213 PL203
Q710 PL105
IC708 S733 D200 C148

R212
R206
S734 104C
C275 C254
S732 R214
R767 Q709 L726

C227
PL707 C807 L725 R223 Q122

R236 L826
C818 S737 C147
R766 C817 UA Q203 R224
IC703 R756

R260

C201
R295
C214

R217 C223
C213 C145

R241
R262 C109 C146

R206
R215
AMPLIFIER BOARD R238
D206 Q207 Q204 Q205
C204
402C

L203
R237
R239
R238 Q201 501LP
D202

R210

R216
R219
R225
R228
C225
R227
R230
C229
R220
R218
C221
002LP 102LP

PL201

DNG
DER
DNG
NEERG
DNG
EULB
DNG
TUOVT
S400 PL200

TOP (COMPONENT) SIDE BOTTOM (SOLDER) SIDE


IDTV BOARD

PL103 PL103
PL100 PL102 PL102 R108
PL100

17FAV15-2 PL101
PL102
PL101
R107
230805
PL105
PL104 R103 R102
32-37XX PL105 L110 S100 L103
R104 L116 R105 R106 L120 L114 C105 L112 R101 L109 R100 L107 S103 C100 L101
L118 L105 L100
C101
L115 C109 L119 L113 L111 L108 L106 L104 L102
JK100
JK101 D107 D108 D109 D106 C104 C103 D102 D100
C110 C106
C108 L117 D104 D103 C102
104 C107
D101
JK104

UA JK105 JK106 JK107 D105 JKI03 JK102 JK101 JK100

BOTTOM (SOLDER) SIDE

TOP (COMPONENT) SIDE FRONT AV BOARD

SM012 PCB LAYOUTS


71
FRONT AV BOARD
KEYPAD INFRARED BOARD
19.4. CONNECTOR DIAGRAM
PL100 PL101 PL102 PL1 PL1 PL203

PL201 PL1002 PL301 PL606 PL600 PL904 PL4 PL1

PL104 PL3

MAIN BOARD PL1 PL2

DAUGHTER BOARD

PL308 PL101

PL1001 PL903 PL900 PL902 PL103 PL901 PL1003 PL202

PL803 PL802 PL101 PL803 PL804 PL106

DAUGHTER
PL805 PL800 PL801 PL102 BOARD IDTV MODULE
BOARD

PL701 PL707 PL700 CN2 CN11 CN10


PANEL

POWER (SMPS)
AMPLIFIER BOARD
PL702 PL703
BOARD

CN61 CN69 CN64 CN23 CN26 CN42 ABUS-L


BOARD
LEFT RIGHT
SPEAKER SPEAKER PANEL DRIVER
CIRCUIT1
CN24
XSUS BOARD
AC INPUT PL100 PL101 ON-OFF PANEL
SWITCH CONTROL UNIT

FILTER BOARD
PANEL DRIVER
CN32
CIRCUIT2
YSUS BOARD

SM012 CONNECTOR DIAGRAM


72
THE UPDATED PARTS LIST

FOR THIS MODEL IS

AVAILABLE ON ESTA
Hitachi, Ltd. Tokyo, Japan
International Sales Division
THE HITACHI ATAGO BUILDING,
No. 15 –12 Nishi Shinbashi, 2 – Chome,
Minato – Ku, Tokyo 105-8430, Japan.
Tel: 03 35022111

HITACHI EUROPE LTD, HITACHI EUROPE S.A.


Whitebrook Park 364 Kifissias Ave. & 1, Delfon Str.
Lower Cookham Road 152 33 Chalandri
Maidenhead Athens
Berkshire GREECE
SL6 8YA Tel: 1-6837200
UNITED KINGDOM Fax: 1-6835964
Tel: 01628 643000 Email: service.hellas@hitachi-eu.com
Fax: 01628 643400
Email: consumer -service@hitachi-eu.com

HITACHI EUROPE GmbH HITACHI EUROPE S.A.


Munich Office Gran Via Carlos III, 86, planta 5
Dornacher Strasse 3 Edificios Trade - Torre Este
D-85622 Feldkirchen bei München 08028 Barcelona
GERMANY SPAIN
Tel: +49-89-991 80-0 Tel: +34 93 409 2550
Fax: +49- 89-991 80-224 Fax: +34 93 491 3513
Hotline: +49-180-551 25 51 (12ct/min) Email: atencion.cliente@hitachi-eu.com
Email: HSE- DUS.service@hitachi-eu.com

HITACHI EUROPE srl HITACHI Europe AB


Via Tommaso Gulli N.39, 20147 Box 77 S-164 94 Kista
Milano, Italia SWEDEN
ITALY Tel: +46 (0) 8 562 711 00
Tel: +39 02 487861 Fax: +46 (0) 8 562 711 13
Tel: +39 02 38073415 Servizio Clienti Email: csgswe@hitachi-eu.com
Fax: +39 02 48786381/2
Email: customerservice.italy@hitachi-eu.com

HITACHI EUROPE S.A.S HITACHI EUROPE LTD (Norway) AB


Lyon Office STRANDVEIEN 18
B.P. 45, 69671 BRON CEDEX 1366 Lysaker
FRANCE NORWAY
Tel: +33 04 72 14 29 70 Tel: 67 5190 30
Fax: +33 04 72 14 29 99 Fax: 67 5190 32
Email: france.consommateur@hitachi-eu.com Email: csgnor@hitachi-eu.com

HITACH EUROPE AB HITACHI EUROPE AB


Egebækgård Neopoli / Niemenkatu 73
Egebækvej 98 FIN-15140 Lahti
DK-2850 Nærum FINLAND
DENMARK Tel : +358 3 8858 271
Tel: +45 43 43 6050 Fax: +358 3 8858 272
Fax: +45 43 60 51 Email: csgnor@hitachi-eu.com
Email: csgnor@hitachi-eu.com

Hitachi Europe Ltd HITACHI EUROPE LTD


Bergensesteenweg 421 Na Sychrove 975/8
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BELGIUM CZECH REPUBLIC
Tel: +32 2 363 99 01 Tel: +420 267 212 383
Fax: +32 2 363 99 00 Fax: +420 267 212 385
Email: sofie.van.bom@hitachi-eu.com Email: csgnor@hitachi-eu.com

www.hitachidigitalmedia.com

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