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PCB Layout Consideration

PCB Units of Measurement

PCB

PCB Basics :

methodologies originated in the United States Units of measurement are therefore typically in Imperial units, not SI/metric units.
Board B d

dimensions di i are commonly l measured d in i inches. i h Dielectric thickness & conductor length and width typically measured in inches and mils. 1 mil = 0.001 inches 1 mil = .0254 mm Conductor thickness measured in ounces (oz). (oz) The weigh of conductor metal in a square foot(ft2) of material. Typical thickness
0.5oz = 17.5m 1.0oz = 35.0m 2.0oz = 70.0m 3.0oz = 105.0m

PCB Conductors : Traces

PCB Anatomy :

R=

L
A

L
h W

= Rs

Cu resistivity: =1.7E10-8m

L W
Source: http://circuitcalculator.com/wordpress/wp-content/uploads/2007/04/pcb-trace-geometry-1.png

Copper (Cu) is the most commonly used conductor in PCBs.

Trace Width (W) and Length (L) controlled by PCB layout engineer

Traces and/or connectors may be plated in nickel followed by gold to provide a corrosionresistant electrically conductive. Width and spacing between traces typically 5 mil in common fabrication processes Typically 0.5oz 3oz Trend towards 0.25oz

Trace Thickness (h) variable of fabrication process

Signal Integrity Tip: All of the above affect the resistance, capacitance and impedance of the trace and must be well understood for high-speed design.

PCB Basics :

PCB Conductors : Power Planes

Signal trace Power plane

Copper Foil Prepreg Core Prepreg Core Prepreg Core Prepreg

Power

Planes

A solid layer of copper used to provide power or ground. Typically use thicker copper layer than signal layers to reduce resistance resistance.
Why

are they needed?

Provide a stable, low-impedance path for power and ground signals to all devices on the PCB Shield signals between layers to minimize cross-talk
Signal

Integrity Tip: By placing power and ground on opposite sides p of thin core material, we can maximize the intra-plane capacitance. Also, this minimizes PCB warping.

PCB Layout y Parasitics

Calculation of Sheet resistance

(For Standard Copper PCB)
R= Z XY = RESISTIVITY R Z X Y

SHEET RESISTANCE CALCULATION FOR 1 OZ. COPPER CONDUCTOR: = 1.724 X 106 cm, Y = 0.0036cm R = 0.48 0 48 Z m X Z = NUMBER OF SQUARES X R = SHEET RESISTANCE OF 1 SQUARE (Z=X) = 0.48m /SQUARE
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Long Track Resistance Impact on ADC

5cm

SIGNAL SOURCE
0.25mm 0 25 (10 mils) il ) wide, id 1 oz. copper PCB trace Assume ground path resistance negligible

16 BIT ADC, 16-BIT RIN = 5k

OHM L OHMs Law predicts di t >1 LSB of f error due d to t drop d in i PCB conductor. d t
Consider a 16-bit ADC with a 5k input resistance, PCB track is 5cm of 0.25mm wide 1 oz. The track resistance of nearly 0.1. The resulting voltage drop is a gain error of 0.1/5k (~0.0019%), Over 1LSB (0.0015% for 16 bits).

Trace/Pad Capacitance
Example: Pad of SOIC L = 0.2cm W = 0.063cm A d K= 4.7 A = 0.126cm2 d = 0.073cm C = 0.072pF

kA C= 11.3d
K = relative dielectric constant A = area i in cm2 d = spacing between plates in cm

Reduce Capacitance p 1) Increase board thickness 2) Reduce trace/pad area 3) Remove ground plane

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Approximate Trace Inductance

All dimensions are in mm

Example L= 2.54cm =25.4mm W = .25mm H = .035mm ( (1oz copper) ) Strip Inductance = 28.8nH At 10MHz ZL = 1.86 a 3.6% error in a 50 system
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Minimize Inductance 1) Use Ground plane 2) Keep length short: Halving the length reduces i d inductance by b 44% 3) Doubling width only reduces inductance by 11%

Via Parasitics
Via Inductance
4h L = 2h ln + 1 nH d
L = inductance of the via, nH H = length of via, cm D = diameter of via via, cm Consider a power supply pin of an op amp that goes through a via to the power plane of an 0.157 cm thick board, p , the diameter of the via is 0.041 cm
4(0.157) L = 2(0.157) ln + 1 0 . 041

Via Capacitance
C= 0.55 rTD1 D2 D1

D2 = diameter of clearance hole in the ground plane, cm D1 = diameter of pad surrounding via, cm T = thickness of printed circuit board, cm r = relative electric permeability of circuit board material C = parasitic via capacitance, pF

Consider a signal coming from the back of the board to the top of the board through a via. Board thickness = 0.157cm, 0 157cm D1=0.071cm D2 = 0.127 C=0 0.51pf 51pf

L = 1.2nh
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Op-Amp Schematic Low Frequency versus High Frequency

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Is My Design Low Speed?

Im

measuring low frequency signals, why should I care about the speed?
Some

low speed circuits, actually have very fast switching edges E.g. ADCs, auto-zero amplifiers Period is long 10us

but edge is fast ~ 5ns

Current is moving at 200MHz! Design low inductive current return paths

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How to start with g good layout y

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Schematic
A

strong and reliable structure (including PCBs) requires a solid foundation, the SCHEMATIC is the PCBs foundation! A good layout starts with a good Schematic! Schematic flow and content are essential Include as much information as you can What should you include?
Good foundation

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Items to Include on a Schematic

Notes N t Component

tolerances and case sizes Part numbers ( (internal/external/alternative) ) Test information Power dissipation Controlled impedance and line matching Component de-rating Thermal requirements q Keep outs Mechanical considerations Critical component placement Board stack up

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Schematic
40 MHz S1 U1

+5V

C1 0.1uF 0 1uF

Place this cap right at pin 14 to digital ground R6 301 40 MHz OSC Out Run 40MHz traces on bottom of the board ensure signal trace is the same length 40 MHz OSC Out R4 210 R3 562 R5 562 U2 ADA48601 +5V

Put C4 and C7 on back of board right under the power supply pin. C4 2.2uF Must be right at op amp supply pins

C5 0.01uF R7 50 C6 0.01uF C7 2.2uF + -5V VOUT

R1 1K

VIN R2 50 C2 SAT C3 SAT

+5V

FREQUENCY ADJUST 1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW

Must be right at op amp supply pins See critical component placement drawing for location +5 V + C12 10uF Case size 1210 -5V -5V C16 + 10uF Case size 1210 +5 V +5V U4 Temperature Sensor AD590

ITEM 1 2 3 4 5 6 7 8

REF DES R1 R2 R3 C1 C2 C3 U1 U2

Derating Table
VALUE 1K RATING 62mW

D1 1N4148
ACTUAL 10mW +12V

U3 Linear Regulator ADP667

C8 + 10uF C Case size 1210 D2 1N4148

-12V

C9 0.01 uF

C11 0.1uF Linear Regulator U5

VOUT

R8 1K

C13 10uf Case size 1210

+ C14 0.1uF C15 0.1uF

NOTES: 1.0 All resistors and capacitors are 0603 case size unless noted otherwise. 2.0 All Resistors in ohms unless noted otherwise. 3.0 All capacitors in pF unless noted otherwise. 4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer 5 0 Remove ground plane on all layers under the mounting pins of U2 5.0 6.0 U1 SOIC-14, U2 SOT-23-6, U3, SOIC-8, U4 SOIC-8

BOARD STACK UP Signal 1 Analog Ground 1 Power plane Digital Ground Analog Ground 2 Signal 2

0.062"

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Location! Location! Location!

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Location, , Location, , Location Critical Component Placement and Routing

Signal

Power

Temp Sensor

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Not optimal placement

Location, , Location, , Location Critical Component Placement and Routing

Temp Sensor

Signal

Power

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Improved placement

Current Return Path

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AC + DC Current Return Path

DC C Current R Return P Path h~l least resistance i AC Current Return Path ~ least impedance(inductance)
i

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Ground Plane
I

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Ground Plane and Trace Routing

Wrong Way

Clock Circuitry

Analog Circuitry

Resistor

Digital Circuitry

Sensitive Analog Circuitry Disrupted by Digital Supply Noise

ID IA + VD VA GND REF + VIN IA + ID ANALOG CIRCUITS ID

INCORRECT
DIGITAL CIRCUITS

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Ground Plane and Trace Routing

Resistor

Analog Circuitry

Right Way
Sensitive Analog Circuitry Safe from Digital Supply Noise
Clock Circuitry

Digital Circuitry

ID IA + VD VA GND REF
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CORRECT
ANALOG CIRCUITS IA ID DIGITAL CIRCUITS

+ VIN

Example 1: Know where the current returns

+5V +5V
2 ib ib 2
ib

V
ib

ib ib AD8226 AD8226 (in-amp) (in-amp) 2.5V 2.5V ADR361 ADR361

ib ib

Saturates amplifier! 2 ib PNP Input Transistors Small bias current

Current In = Current Out Nowhere for current to go!

Example 2: Know where the current returns

100

100k

AD8610 1k V i1 i2

0.01 0.01 parasiticresistance in trace

If i1 = 10 mA V = 100uV Output Error = 100mV

Example 2: Be aware of currents during PCB Layout

For

Low Frequency Signals

100
100k 1 100 2 3 Signal GND 0.1uF P Power and d Load L d GND Only top microstrip and Ground shown Power from power plane 4

100k

connector From source connector

AD8610
-IN +IN -VS

0.1uF

+VS 7 OUT 6
5 1k

AD8610 1k

star g ground

Disturbance through parasitic Ground is separated under resistance is common to sensitive input area both inputs Large output current goes to power ground I Input t area ground d tied ti d to t power ground d at t one point i t

Grounding Consideration

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Grounding the Mixed Signal IC

Which One is Better?
VA VD VA VD

ANALOG CIRCUITS

VA VD MIXED SIGNAL DEVICE AGND DGND

DIGITAL CIRCUITS

STAR GROUND A A D D

ONE GROUND PLANE WITH GOOD LOCATIONS

ANALOG CIRCUITS

VA MIXED SIGNAL DEVICE AGND

VD DIGITAL CIRCUITS DGND

ANALOG GROUND PLANE

DIGITAL GROUND PLANE

A A

D
DIGITAL SUPPLY

ANALOG SUPPLY

DIGITAL SUPPLY

ANALOG SUPPLY

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Another Split p Ground Plane Idea Why every power pin need decoupling Caps?
VA VD A
FERRITE BEAD

VA
LP RP

VD
LP

C STRAY

RP

AIN/ OUT

ANALOG CIRCUITS A
RP LP

DIGITAL CIRCUITS DATA B C STRAY

RP LP

BUFFER GATE OR REGISTER

CIN 10pF

DATA BUS

IA

ID

AGND A
SHORT CONNECTIONS

DGND A

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VNOISE

A = ANALOG GROUND PLANE

D = DIGITAL GROUND PLANE

Power Supply pp y Bypassing yp g

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Power Supply Bypassing

Bypassing

is essential to high speed circuit performance Capacitors right at power supply pins Capacitors provide low p AC return impedance Provide local charge storage for fast rising/falling edges Keep trace lengths short Put Smaller Values Capacitor Closer to the Pin Close Cl t l to load d return t Helps minimize transient currents in the ground plane
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VDDint

PMOS NMOS

CGATE

VDD GND

VDD GND

High to low t transition iti

Bypassing yp g Capacitor p Layout y

VCC GND

C Correct

LQFP LFCSP

VCC VCC

Via C W Wrong

GND VCC GND

Wrong

Correct
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No long trace under IC Short trace then to bottom by via Short trace to GND or Power under IC. IC Short trace to decouple Capacitors

Wrong

Capacitor Choices

0603

0612

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Power Supply Bypassing

ESR

(Equivalent Series Resistance) Rs Capacitance C it XC = 1/2fC ESL ( (Equivalent q Series Inductance) XL=2fL
Effective

Impedance

At

Series resonance XL XL=XC XC Z = R

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Multiple Parallel Capacitors

330F

1F 0.1F 0.01F

1 x 330F T520, 1 x 1.0F 0603, 2 x 0.1F 0603, and 6 x 0.01F 0603 2 x (1 x 330F T520, 1 x 1.0F 0603, 2 x 0.1F 0603, and 6 x 0.01F 0603)
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*Courtesy of Lee Ritchey

Power Supply Bypassing Ferrite Beads

Ferrite

1LSB = cap 120V B Bypass Z = 0.32 0 32 Noise is equivalent to 7 LSBs Bead and noise bypass cap provide How much is

Beads Provide no DC drop Without Ferrite Bead Increase I 50mVpp@50MHz impedance i d =890V with ith With frequency Ferrite Bead increasing -35dB@50MHz 14-bit system withbead 2V FS At 50MHz Ferrite Z = 60

+VS L1

U1 AD8138AR
8

C1 10nF 5 OUT

Additional 45dB of attenuation present at the output of a AD8138 differential =5V 50mVpp@50MHz amplifier, with Noise is well below 50mVpp@50MHz the 1 LSB supply line Without a ferrite bead? With a ferrite bead?

2 V OCM 1 6 C1 10nF 4 OUT+

L2 VS

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IC Package and PCB Layout Issues for Thermal Performance

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Thermal Performance for Different Packages

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Thermal Performance for Different Layouts

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LQFP

LFCSP

Thermal Design Technique Layout Example

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