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Technische Universitt Mnchen

Chip Multicore Processors


Tutorial 7

S. Wallentowitz

Institute for Integrated Systems Theresienstr. 90 Building N1 www.lis.ei.tum.de

Technische Universitt Mnchen

Task 7.1: Memory Overhead of Cache Coherency


Given is the sketched system, which integrates processor cores and their caches. Each of the caches has size 1 . The cores share a last level cache of size 2 . All cache blocks are of size . A memory of size is connected to the system.

L1

L1

L1

Dir

L2
Mem

Cache coherency can either be snoopingbased or directory-based. Snooping adds 2 extra bits to the caches and the directory implementation requires 3 bits plus a bitvector.

Chip Multicore Processors Tutorial 7 2 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.1 a)

L1

L1

L1

Calculate the required memory bits for snooping- and directory-based coherency
Dir L2 Mem

Chip Multicore Processors Tutorial 7 3 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.1 b)

Calculate the extra memory of an embedded system with 32 MB memory, 32 kB L1 cache and 256 kB L2 cache. The cache blocks are of 4 words.

L1

L1

L1

Dir

L2 Mem

Chip Multicore Processors Tutorial 7 5 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.1 c)

Calculate the extra memory of a desktop system with 4096 MB memory, 512 kB L1 cache and 4 MB L2 cache. The cache blocks are of 8 words.

L1

L1

L1

Dir

L2 Mem

Chip Multicore Processors Tutorial 7 6 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

Task 7.2: Basics of Cache Coherency


Three caches use snooping-based cache coherency with a shared bus. Complete the states of the cache entries according to the MSI protocol for the given operations.
Invalidate Write Miss

Read Hit

Invalid
CPU Write Miss (Place write miss on bus) Write Miss (Write Miss)

CPU Read Miss (Place read miss on bus)

Shared

Read Miss

All actions on cache lines Write-back cache Processor triggered


Events Cache actions

Modified
Hit

Bus triggered
Events Cache actions

Chip Multicore Processors Tutorial 7 7 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.2 a)
t 0 (1) READ 1 (1) WRITE operation C0 I C1 I C2 I

Chip Multicore Processors Tutorial 7 8 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.2 a)
t 2 (0) READ 3 (2) WRITE operation C0 I C1 M C2 I

Chip Multicore Processors Tutorial 7 9 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.2 a)
t 4 (2) READ 5 (0) READ 6 (0) WRITE operation C0 I C1 I C2 M

Chip Multicore Processors Tutorial 7 10 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.2 b)
t 0

Do the same according to the MESI protocol

operation

C0 I

C1 I

C2 I

(1) READ 1 (1) WRITE

Chip Multicore Processors Tutorial 7 11 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.2 c)

According to you, what extensions does a bus need to support snooping-based cache coherency (write back caches)?

Chip Multicore Processors Tutorial 7 12 S. Wallentowitz

Institute for Integrated Systems

Technische Universitt Mnchen

7.2 d)

For MSI and MESI sketch the valid state combinations for one entry in two caches.

M M S I

M M E S I

Chip Multicore Processors Tutorial 7 16 S. Wallentowitz

Institute for Integrated Systems