MUNCHEN TECHNISCHE UNIVERSITAT Lehrstuhl f ur Integrierte Systeme

Chip Multicore Processors Tutorial 9

June 26, 2013

Task 9.1: Directory-based Cache Coherency

In this tutorial you will learn about directory-based cache coherency protocols. Given is the sketched system: A central directory is located near to the memory and each cache supports directory-based cache coherency. The communication is performed over a network (that is abstracted here). The directory implements the MSI protocol and stores the bitvector of all caches which share a cache line.

CPU 0 Cache 0

CPU 1 Cache 1 Interconnect

CPU 2 Cache 2

Directory Memory

a) In the following you nd the initial state of the caches. Determine the entries of the directory from the local entries.

0 1 2 3

P0 I S 408 54 04 M 410 20 01 I

0 1 2 3

P1 I M 428 00 20 I S 418 0a 00 Directory

0 1 2 3

P2 S 420 01 02 S 408 54 04 M 430 00 00 I

Memory 400 00 00 408 54 04 410 03 00 418 00 00 420 01 02 428 0c d0 430 00 ff 438 00 00

State

Bitvector

P2 P1 P0

b) Explicit messages are exchanged between the caches and the directory. The following table contains all messages that are exchanged. Develop a MSI state diagram for the coherency protocol. Beside processor events external messages lead to state transitions. Messages are sent as actions during state transitions.

2
Type Read Miss (RM) Write Miss (WM) Invalidate (IR) Invalidate (IN) Fetch (FE) Fetch/invalidate (FI) Data value (DA) Data write back (WB) Source Local Cache Local Cache Local Cache Directory Directory Directory Directory Remote Cache Destination Directory Directory Directory Remote Cache Remote Cache Remote Cache Local Cache Directory Content ID, Address ID, Address Address Address Address Address Data Address, Data Description

c) Complete the message sequence charts of the coherency protocol starting from the initial state. Start from the initial state for each of the sequences separately. Also update the new states of the local caches and the directory. i) Sequence 1 (P1) read 400 (P2) read 438 Local Entries Op CPU Index

State

Tag

Data

Directory Op State

Bit Vector

Cache 0

Cache 1

Cache 2

Directory

3 ii) Sequence 2

(P1) read 410 (P2) read 410 (P0) read 430

Local Entries Op CPU Index

State

Tag

Data

Directory Op State

Bit Vector

Cache 0

Cache 1

Cache 2

Directory

4 iii) Sequence 3

(P0) write 420, 42 (P2) read 424 (P2) write 424, 23

Local Entries Op CPU Index

State

Tag

Data

Directory Op State

Bit Vector

Cache 0

Cache 1

Cache 2

Directory

5 iv) Sequence 4 (P0) write 408, 7 (P2) read 408 (P0) write 408, 9 Local Entries Op CPU Index

State

Tag

Data

Directory Op State

Bit Vector

Cache 0

Cache 1

Cache 2

Directory

d) What do you think may a home directory be? How can this technique improve the performance of directory-based cache coherency.