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0 Architecture Overview
Bob Dunstan
Principal Engineer
Intel Corporation
USB 3.0 Technical Workgroup Chair
Agenda
What is USB 3.0
Connectors/cables
Physical Layer
Link Layer
Protocol Layer
Power Management
Summary
Power Efficient
Provides excellent power characteristics (especially for idle links)
Both on the device and the platform
Extensible
Protocol designed to efficiently scale up
3
SuperSpeed USB
Connector Interoperability
Summary
Receptacle
Plugs Accepted
USB3_RX
GND
USB3_TX
D-
VBUS
D+
GND
8
USB 3.0
Portion
Micro-B
Micro-AB/A
10
Cables
Unshielded twisted pair (UTP) cable used for USB 2.0
cannot be used for SuperSpeed USB
Shielded differential pair (SDP, twisted or twinax) is needed
for SuperSpeed USB
UTP Signal Pair
Filler,
optional
Braid
Power
Jacket
Ground
U-005
0
RLGC M
odel
M
easured
Diff IL, dB
-5
-10
-15
-20
0
5
6
Frequency, GHz
10
11
Symbols &
Sideband Signaling
12
Physical Layer
Support up to a 3 Meter cable
Based on existing specs
Signaling similar to mix of high-speed serial buses (PCIe/SATA)
2 differential pairs dual simplex
13
Packets &
Link Cmds
14
Link Layer
Robust & Reliable
Redundancy, advanced encoding techniques and retries
>10-20 undetectable error rate for link commands
Link Commands
Link flow control
Link power state change
Packets
Header Packets
Store and forward
Link level retries guarantee reliability
Contain information consumed by link or host or device
Data Packet
Compound packet contains header plus data payload
15
Headers &
Data
16
Protocol Layer
Preserved legacy SW stack
USB 2.0 transfer types (bulk, control, interrupt,
isochronous)
Packet Basics
Header & Data Packets
Move between host and device
Address triple: device address, endpoint number, direction
Route String describes path between host and device
Example IN Transaction
19
SuperSpeed USB
Application Layer
20
SuperSpeed USB
Power Management Primitives
Physical Layer
Lower power per bit
Dual simplex - dont need to turn around the bus
Low Frequency Periodic Signaling
Link Layer
Four Link States - trade lower power for increased latency
U0: operational, U1: link idle with fast exit (PLL remains on)
U2: link idle with slow exit (PLL may be off), U3: suspend
Protocol Layer
23
25
26
Host can perform other transfers while waiting for ping response
Device suspend
Device-wide state coupled to U3
Entered / exited intrinsically as a result of U3 entry / exit
SetPortFeature(PORT_LINK_STATE U3)
Summary
Physical layer is based on existing industry specs
Maintained backwards compatibility
Cabling/connector
Standard A receptacles backward compatible with USB 2.0
New B and Micro AB receptacles backward compatible with USB 2.0
Call to Action
Download & Review USB 3.0 Material
USB 3.0 Version 1.0 Specification
Referenced documents
Pipe Spec (www.developers.intel.com)
33
Backup
USB 3.0
Portion
USB 3.0
Portion
USB 3.0
Portion
37
38
0
X: 100
Y: -1.5
X: 1250
Y: -5
-5
X: 2500
Y: -7.5
-10
-15
-25
X: 7500
Y: -25
-30
0
1000
2000
3000
4000
5000
Frequency, MHz
6000
7000
X: 2.5e+009
Y: -6.871
-5
-10
-15
-20
-25
-30
-35
10
39
-10
-20
X: 3000
Y: -23
-25
X: 7500
Y: -23
X: 100
Y: -27
X: 2500
Y: -27
-30
-35
-40
0
Differential Crosstalk, dB
-15
X: 3000
Y: -15
X: 7500
Y: -15
-15
-20
X: 100
Y: -21
X: 2500
Y: -21
-25
1000
2000
3000
4000
5000
Frequency, MHz
6000
7000
-30
0
1000
2000
3000
4000
5000
Frequency, MHz
6000
7000
40
Unmating force
10N min initial, 8N min EOL
4-Axis continuity
Required for Micro connector family
225 mV
41
Attention Required
Great attention must be paid to electrical design details to
minimize TDR Impedance mismatch, crosstalk between
SuperSpeed USB pairs and crosstalk between SuperSpeed USB
and D+/D- pairs
The cable termination management is particularly important
42