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  • Chapter Thi

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    ghumansmsaa
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    DCS notes including VHDL coding for different digital circuits

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    DCS notes including VHDL coding for different digital circuits

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    322 просмотров119 страниц

    Chapter Thi

    Загружено:

    ghumansmsaa
    DCS notes including VHDL coding for different digital circuits

    Авторское право:

    Attribution Non-Commercial (BY-NC)
    Скачайте в формате PDF, TXT или читайте онлайн в Scribd
    Отметить как неприемлемый контент
    из 119

    Chapter Thi

    330
    process rca,Droc is triggered when a rising edge occurs on input ctk.
    a is copiedto output q'
    When thb procese is triggered, input

    Regarray
    bheset of regislers wilhin the cPU
    The roslrray entity is used to model
    valucs during instruction processing.
    that are used to slore intermediale
    lo during the execuLionof in'
    nt;t; .Lgi"t rc are read from and rvritten
    a RAM of eight 16-bit rvords.
    Ttle sef of registers is,modeled_as
    f.
    "*liorr"r.
    The svmbol for the r.sarrav entitylFshor@
    +i"fi;Gfu;settrrpurEcrffihe locationbobe
    rlt:
    and put a rising edge on
    written, input data with the data to be written'
    s€t input aet to the location
    i.rp,rt .it. io re"d a rocationfrom resarrav,
    data is output on port q'
    to be read and set input on to a'l'; the
    The registe, is modeledas two separateprocessesas shown in
    "*"y
    the following:

    I, llbrar:'fEEEl
    l.
    uac IEEC.r!d-1oglc-116{'4111
    t. all I
    {I utc IEE!. rt4::.ogtc-urllgroad'
    l) urc rork.cpu-llb'allI
    ll
    r,
    rt'
    tl cnultY rogarr:ry ls
    Porc( d'atr r ln blt'161
    ll
    |
    *{ gol r Ln t-rcgl
    6a r ln atsd-loglct
    4l
    c1k r ln ctdl-loglcl
    ' qtoubblbl6)'
    crld r.gltaty,

    qE !E!T
    Flgure l3-8
    EET IEEI
    I ."*
    RegArraySymbol.

    1..
    "
    DescriPtion
    CPU: SYnthesis
    of regarrdit
    ar c hlc e' c t u r o rcl v!
    o f b"^-
    ltr6;
    "'".;:";_;;:i"::,:""1:,;:,,
    \
    '\. I
    \:
    lq. ;
    ' "oot r l. """( c l k , g s l - ) . -
    t^It"tf"lr" . F 'r n :
    \, ramdaEa ! E-rar';
    i
    ot 1?c 1k , e v 6 n u 't ' . t n u t
    and clk '
    (ae1) ) : = daua;
    uo.^,
    ra:odatsat"o"l-lnttger
    ) a f t '6 r I ns'
    r: : l* g : : l i " <o r a : n d a t a ( c o n v - l n L e s o r ( s e l )

    6. 6nd P r o c e s s i
    a. -
    (ori' esmp-data )
    ,S
    Procoee
    begln e n
    r r1t then
    cerg-data afE€r I DBi
    q <=
    be
    1 n6!
    0n "t T . - *z '7 'Z z ? 'z 'z z z z z z \ 'Z z z i sl 'f E o r
    0n end l fl
    end' I) r oc e66'

    in
    ttre.garr H ::x';*;1"J
    moders
    il ;;; r'oess .:*:i ii:' :'1,:
    "-'1"-
    sff ::;:ffi*::i."ffi:h'"fi:;;'J,1ff
    uv
    1'Iffi'l*:t*:1i
    aeti' 'ld11:i,*1.,*-;;
    input t. pa$the:*: ?
    ;fi;;:v*rti,llil\Tf
    i#;;;"i."t"a
    the secondp:""11^r"ri"ut..
    -8?'and :T:[,#:*.#:*:::T,S]H ''' cannotbe
    i"* vrror' . "?1111':":H:'"iJ;".*i teeal-- uuthssothera1m':"'' : :
    '
    ttH;'btsharingvariablesbetweenprocL----- --
    ;*:::;:r$::ssis-useali:::i,:::;Iil.'ffi ;:l*S;:"#..
    j,i-"
    i,, "' :n""?:.; j:;l* ;" o *" l?lory data' -''
    nal ccqr-datsa rs pasc€u ru::::i!lT;;;
    : ;": :,"i,," t"ro_dara
    *if
    :.
    the oa srg i8 'lii
    thevalue'i:;;";i
    ^f 1i'Y:: "lt" .''o
    n"o."r,'*inufs
    Thesecond ":-'.
    orherwise,it putsil";"';; r.er:,'ar +" *t5;n'3 *::::ffi:
    i,ir t."";a;::1[.Ji,$il:]ilH*
    tYoFe
    il ;,rt"q*technologv
    t" and
    A smart a#tt * tit target
    entitv canbettni*:''liiJl;RAM
    provide thepropermapping lo'l,TffiT; *:*;t*rT,'::q:tJ$ ue'
    thatincruoei-il;:
    i;;;;pCd technolocv ,"0'"'a RAlvtdevice'
    map
    ;l;'i' toolcould. se\ -r
    u.r'Y'.
    the'rcc'ar:'1":::'.;;
    i nlo'n"n'andgates
    "" creates
    ;i;
    ffi ""tTn"I;:ifii:iltrffiil:'
    taswr rr'Prv'^'-'---'
    a smaller and

    .f
    3 32

    shifr

    f*jl:ili'*';"^,$i:lll,iiiiiil*,ffr"1'f"
    ahifr enrirynasa 16-bir ,:,il,r:ffi
    fr
    inpurbus, ro:tlr.;;;;ff:::J;:::r"ill:
    "
    npo,.nti*^i1""''
    :)::r:i::i';riln';,;l;t''r'iii rrris;' .i.;';; b1.'re
    'I'he typesof shift operations
    that ian bc pcrformedby the ghlfr
    bibyare shorvn,inFigures1J-10 en-
    and 13-11,
    As can be seenby the figures,tt"ro
    rr,ii. unritycan perform a
    sliifr rig't, rotate reft,and rotate shift left,
    right op*ution. on" op".utti.,
    trol sirorvnbv the figuresis a pass that is
    tfi.ougi op.."ti* in ;;;;il',
    inpurs
    ""'n" un1.t'
    H1il: ffi::i JiJ:::.1',,'.11 "nguanouo
    *'i"gi"i n tirv
    ".,
    lib r ary IE E E ,
    u 6 e IE E E . etd_1ogl c_116{.a1l 1
    u g a w ork.cpu_l l b.aLl l

    6ne 1 t f , . g h l f C 1 g
    port(a:Inblt16l
    . ee.I r ln t_ablftr
    y r out, blr,16),
    end s h i f t l

    ' ar oh L t e c t , u r e rbl of ohl.ft la


    begln
    ah f t p r o c : proc6r!B (a, es1)
    . bcgla
    caga gel le
    when ghf,tpaae r>
    y <r a a f ! . r 1 Ds,

    when ahl
    . y <F a ( 1->{ d , o v a t o 0 ) & . : {, . attcr 1 nal
    w hE n B hr g>

    M ENT &E FiqI


    Flgure t 3-9
    ShiftSymbol.

    ".i6da{l$ffi1
    s;'. 1i

    -.'...'.
    ! t.,, :.f r t : . ii, . r , : \ . t ! . . ...
    CPU: SynthesisDescri$tion 333
    l&l E tilRt utel
    Flgur e l3- t O
    5hift Operations.
    e

    is Shift Left
    ^A LS
    Lis vJ

    uts
    itv

    tz-i ..)
    1\:-i , 1), t1l l t l D ' 7 6 cc r
    o lo lo lo lo 0 0 0 0 o lo lr oll 0 t

    :N
    |
    \\\

    \\\
    0l 0l 0l 0l 0 0 U 0 0 01010 1t0 I 0

    Shift Rigbt

    <o '0' & a ( 15 do'rrD to l ) attcr 1 al ,

    vrbon rotl c>


    <o a ( l { dosnto o) & a(15) a!!.r 1 D .,

    vrhea l Otr s>


    t <e a(0) & a(15 do',mto 1) after 1 "n|,

    cad cagg,
    snd D rocesg,
    cnd rtl r

    The etrftpaga mode allorvsthe shifter to pass the input data to lhe o
    put without an)' shift operations.This mode is quite common because
    very fe\v
    of ttr" ALQ operabions florv through.the atrllc entity, and
    strrictions are actually performing a shift operation' ;.
    -.,,..;*.,.,.-.".,- ,qr d::;&"SMl&*6!-

    Chapter
    396
    E@l Btrr @ trEEl
    Flgur e l7' t
    High Dens ir yDes i9n

    ri
    ;l
    ,{
    rl
    t.

    ;l

    'i

    Post LaYoutTiming
    Simulation

    TheVITAL process in Figure1?'2'


    1' shc'''{n
    generate.two VlTALcomplisnt simulatr
    The placeand route tools
    that contsinsthe interconnectlor
    input files.The first i;; C;;;ttlist e
    the design'The secondis a timing
    of all of the entities*ta it "ttal into tl
    to input post'route'tlming
    curate SDF back'a""ti"'it" nfeused do the gimulati
    vlrAl, eimulation.;;;;; i; ; try9- iL?"t needed
    proceso. The third ;il;i';h; vriel tt3.t"rythat deecribegall of t
    thedesign'In the nextfew s
    behavlorof theentitiJ. t"ta to implement
    detail'
    tione, we examine each of thesein more

    ': ::-'i

    eruffi*;
    :{''' ' '
    :Vital Simulabion 397
    xtLiit tfjls: lil4'tdl !i'ii!?
    Flgure 17'2
    WIAL DAIAFIOW,

    VF IDL
    Nctli.r t

    VITAL LibrarY
    deve usethere were no gta,n'
    One of the reasons VITAL rvas
    dard me method of'
    %ndard
    timing,therewas als
    tffi i "iu'"'"
    ff.'.Ht.,"J *i" tion'wIDL.was"1'" tl"^1:'
    :::,i, :iuil;
    optimized for
    ffi;:"r}ffiH: ffi,.,lo*p"'.d rogarelevelsimulators
    ulatr t"F"[ii,i'J*Hr::';
    vrrAl v,.as neargarelevelsim'
    roauorv
    creared
    rctiot features
    accuralemodeis'Someof the
    hge ulation performancev;ith riming
    s:
    lto tl availabll with \TITAL are as f6llsr'
    ulati
    oft i ffiJ'"'
    ;J'H:';T'iil'"T'i"
    bwe
    occurrence of a condition'

    l
    . -' ***
    -,----, -*

    fu.'t"
    3 98
    a t oorr- Checksincl,de setupc'ecke,
    PHg Z.l:Fr4+,!rerls,+o hold
    checks,
    periodchecks,andaccurare
    liijlrl;ll,rewidrh slitclr
    N wy t" tp"tifuf""
    'ygyt -Functionaritycanbespecifred
    with truth tables,statetabies,
    boolean
    pnml'lves,
    d e s c ri pti on.
    or a behavioral
    i
    Al l o f these featul es gi ve the desi gner
    the abi ri ty co create ti ming
    a c c u ra te IIP GA or A S IC l i brari e
    s,

    ffiffi eaffi vrrAr, sirnulation pnocess


    Overview
    **Fi+*qg#s.
    :n:.
    tu:|:lrptur. T$,J/iT4!_cutglur,onupurrrug rt
    of uru nt"r. fne
    is the \IFIDL nafliqf- fhio io . r,
    first
    9-le
    nals,,and component-instanGti;rsrh;dnnect
    alr of the comDonsr I
    wr ro.formrhe,functionality
    of the deeign.
    i. '"rauvtl.ir,"*jiT",:
    titt'_nt" yTe:t, -' d;fiil:
    ]
    l
    nent connectivifJ,'in the dptpho*
    file is sn SDF (StandsrdDelayFormat)file that
    Ih_e_eecond
    tinfinaTortfdaa E
    containe SDF
    statements that describethedelaysand tiriring I
    checksfor the inetance.This
    irr-forrnationis used during simurationto model r{
    the timing uerrauii".
    To build the vITAr, sinulation database,the
    eimulatorneed,gto have
    vITAr library that-containscomponents for the target technorogyand r?
    i I
    the vrrDl netlist and sDF timing firufror the place L:
    and route toole.The u*
    eimulator uses the netliet to inslantiate the proper
    instancesfrom the
    virAl library in the internar darabase ilf"p
    ;iJrg to the
    instances rvith the sDF file. Each of the instances
    "na'tt.T "pply fl:e
    containsa number of
    generics that receivethe timing information, t-
    The timing data is used 1: :

    within the modelto providethe correctbehavior igc.


    of the underlyingdevice.

    W ffitr'ffi V{TAL Implementation


    y-rTAr descriptionsfoiiow a standardsryreand make use of
    /'unc'ronsand proceduresfrom trvo standard
    wrAL packages,The VITAL Timing
    @,-

    *l
    399
    CPU:Vital Simulation
    ures
    geconrainsproced
    packa ""uj:1:: :TJ:lril'ilT: :'"tt
    lJ"$i:Xff;
    errorreportlng'
    andtiming
    i*irr""n;.ks, i* simulatorperformance.
    ",
    """1'.t*ogtt-t"l^T,1:':;:\]|o[.6"Jrl'J11r.,.iJ*iri'n""packageintothc
    Most \4TAL-comPIrr
    :i*rf :#:'lH';il"'T:;i:::r:l*ff
    T,:""?::tt"J':',t;tl,
    i rortiminsi*:1'::
    onlY,Hht[H:i"T*xp:dT,]EtL::,t:
    to";i;;;;;t'
    i*",,,,,ses "7
    i,";',ro;]l;J."."$*'#;"""#1:Ti"J"".:,:::t".'iltl
    i:lnli*'gg":in'""'::ip:i'i*i::il1'"tL'";x
    ;i;^"'l;;"t o a""'lrtio-ns Y mavnotbebuill in'
    ^ljl',n,.n
    constructs w
    ;";;";s use ueitavloral

    VITAL Model
    effiSffiFsffifi SimPle
    howthewtALT''-'-lff
    rounderstand t:'1i"o;ilil""ffiil:T';i""ili"T"Tffii
    model examined''Ihe nigu'"rz-s'
    il;i; gate
    i-
    rortbeAND " 'il#,;, * "lt-T":li"*if
    -"*ri"-rr*or this devicenas
    p ' m;;i"J;dwrAl,'
    F
    i-
    D inl lnPutDelaY
    Er'4{
    e# E#t, r'rrig
    ' F igu re l 7 -3

    --t
    MTALAND Gate'
    [.o

    Io

    of
    ed
    .o

    OutPut DelaY
    int2 -> Y
    .a.t, 1s

    rn0

    F.
    ' p+, ll,,,:,,
    Chapter Ssvefiteen.

    from input loe


    lrlt to output v and
    pin-to-pin delays from input
    !n2, &rd
    to output v' the funcLionality of the
    is the --irAl
    V model that implements
    Following
    erroz device:
    CEIJIJ A!T D 2 -----
    ----- : ;
    1i6s6.ry IEEEI
    :
    uae IEEE'STD-LoGIC-116{'h1l;
    all ;
    i"". it"i' *r-nr'-rtrnlsg'
    iii'"* :
    uge
    ^1Y{!.}lo*.r."rr,'
    al€- v t l' 9U '

    declaratlon --
    - - ont s lc y
    AND2 16
    entsltsY
    generic ( B ool ean :r tfuel
    : - Falae'
    't-'19?::*1'
    1*:::::::*i'
    -a-arrElonqai
    Dee
    "lI.; r' '*"r-- t
    stnrHo
    ro:s*:al'qii' D€fProf)D€layo1'
    ire"ro"laytYec9l i Dc!Pro!,Dcla1|'o1t
    :*ffi-; i vriarocr'v*rP'01 1il' DolPronDclelolf
    :T- *; r vlcal.D!1a141?c0t t
    elPoJ:: r' DatProttDclrlol)
    I vltaroela!'ttrirc0l

    porc (
    T t otlg
    t t! s'rD-rpclc'
    eatitvk Tasrt
    iti
    .,:i.

    ':jil ; . ,
    l''""iH,i' #.*-'HtflTt^L"''
    :
    l ... : -.---.
    'i::
    ) Ys ' ' " o 4 ' n fO2
    !B:
    {rl

    .iir
    ii,
    ;"*llki*1ffi*'Y^"1u'n* r arcb'ltcogrrrc
    lr

    ii TRI'E'
    1 r r u 'l
    Eroltlr'
    ::::1*
    lN2-lp.o : 313:ffi1! tE \u"
    SIONAL

    bcgln

    -"'--:-
    wl"raDo).aY : blocx
    b cg i n , { n6 . g!r€'-INl) I
    l rcD or"V trl-.,r
    'l -i '-I' ctgd-rN 2) I
    vical fi
    t l nz-'v-'
    vlEa]-Wl reoal aY
    a n d bl ockl
    i\
    t
    li
    -. BEIIAVIOR

    vIT ALBotr aw l or
    SECTION

    : gtoc €as
    (rNl-tpd, r'ne-IPd)

    ii
    ii
    tt4.
    ,Ft ii"
    ,:Ij

    I
    I
    -<
    .-t

    @',\-
    a- ''----
    ')/l
    -t
    |t\
    Eft ----/
    ' 1" ctt
    la, 10
    { I n it , a r . s ' i/ . 1( )' . / l) t ' t t li \ I . 't ' t tt t it t
    l) t ' l l r r t l l r ( llI o{ l.lccir lt:. ] * r. -
    '\

    AI] Ii L-l-l D I- I) t'itttt t'

    Alllil, I)t'intct' Ctxtlcnls

    . L lt t t t odt t c lt ot t
    . 2. Bas ic s lluc t ur c o{ ' ; t t l r \ ll1: . 1.s o t r r c e l l l e
    . i. p- - e- q. lat i{ ig16 ( nr odulc , pin, r t od c , c o r l s t i t l l l s )
    . 4. ),lrrr_nbcrs
    . -5 .Dir c c liv c s
    . (r , Set s
    o a. ltldgl-lltg o!-i!!c!5!!rrg it L('!
    o b. Sqlpltq_rlttqrtr
    6.Qpstalqr.r
    o a. l, ogic al O pc r alor s
    o b. A-n!hl_c_tis_.stt_c1_tl(_e!
    r
    o c. Retatiqnal_sp!-iajq[s
    o d. A.rs:grute!1-spej4lslE
    .o e. Qperatgr-prio-riV
    8.LBeie-dssiBtier
    o a.Eqg4rllllt
    . Whea:Ib9n-Etr9-st4!e'nen!
    o b.Ir:utlilabl_e
    o c. S-B!,e-_Dq5_cI]p_!9x
    I State-diagram
    r lf-Then-Elsestatemertt
    r 'With statement
    r Case statenrent
    o d.D_S!-Qxlenslelg
    a 9. TeS! vectors
    a 10. Device Specific (Propery
    a I l. f,4r'sce[[aneore
    o a. A-alr_yq: Lqrv_-d.ec larallqlS
    a 1 2 . Ex a m p l e s
    o MoO_r_e_ ttrt ite ,StllteI''lachirte
    o Mgq.ly_Finjte Statef,tachjne
    o Syttc-luOttB tc.St atc lrlirclt tttc
    tLsM-c;tl)' [: i Lr,i
    C.oqm-on!!_tslakss.
    Refercnces
    Acknorvledgernent

    I Introduction
    Ag-&galgl.gg.&g!-c-ggpqua.tion La4guagc)allowsyouto enterbghavior-likc of a lggiccircuit.AIJEL is
    descriptions
    an industry-standard hardwaredescription (HDL) thatwasdeveloped
    languag_e by DataIiO Corporatlon for
    ' pgggltlmplJ.elogic{eyices(FLD).Thereareotherhardware description
    languagessuchasVHDL andVerilog.A.QEL-
    thanVHDI. whichis capable
    is a simplerlan'!-triige systems
    of-d.esE-ribing of largercomplexiry.
    #r!Fi
    4Epl"can-lerscdJodescribe.thebehaviorof a systemin a varietyof forms.includinglogic equations,
    truth tg"bl.er-ed
    The ABEL compilerallorvsdesigns
    statediagramsusingC-like satements. to be simulatedandimplemented intoPLDs
    subhTFPHf,i;CFtb;
    anonPcns.

    andsyntaxof ABEL.lt is notintended


    Followingis a briefoverviewof someof thefeatures to bea completediscussion
    primerwill getyousta(edwithwritingABELcode.In caseyouarefamiliarwithABEL,
    of all its.fpatutes..ItUgApEL
    thiswrite.up-qnserva'A;.a quickreferenceof thefQs! oft9ousedcommands.
    Formoreadvanged please
    features,
    consu[t ariAf gUinaniiilnilbelitinx-on:lng documentati

    h$,
    *c*$:i*li
    t.

    t.

    N
    .. A ,rl. l. { { } ln ' (' t ^ f ilt '
    ttl :lll /t ti
    2. lllr sic st t'rtr {itt't'
    c l c r r ': r t : r
    i' ; t ' ' l{ lt c ll! lt l) ' : ] lt 't
    r',rr AllL,l. s(r ur . c (ltl il"- r t t t

    tc.d i tr c tl ( ) t c i l :'( : 5( :l l r ' ri '


    ( ll r i ,c r t. tl ttttl tti '- c tc ')
    ,1.\(rilllll;lllrl'i
    f i'1rl0 ( l l r l 't l l I
    ,l i c el l l ;t:- s C tt:;i l i r l t
    ' ' r" t,\' 1 ' , ()l i l l , j .l ( - ;l \( ', l r r ti
    lr t ' t r r ' " , , 1" { 1 \\\1 1l ' 1 :i l l t,1 ,1,. , tt"'t.
    r lill( :r ) Lilll t} t :
    l \)\\'( l l.il:'f

    ,,,t,,' . I r r r tt ' { r ii
    ,,.'l i ;'i ',,,1 'i
    "
    L , i r 'L
    1, i1( . . , 1i ; lL, ' r

    qgPro'l;te,rn'$o*c" \ lrbel'e"^r
    r d'i!'e'y.at"'*
    .r'l'eAuJ,e

    frrble MN
    f,i,:.'rccil-' ' i '':;r rlcviceType;i
    :.1':"

    a:t
    sindrchrqfinnt
    : I
    $ ,''
    ii1 atl*xdeclvdidttg
    !.

    { l { tli- t;u n $

    ( . . - 1 7 ;;ir ":' ;

    t[€sle Vad@^*T
    . ,., /r )/ r
    i. . il

    l r \:itl t::tt
    c . i' t t i "

    E' \' a r n p le of a l ral l 'addcr:


    ' r ' 1 , , , , , . . r 1;1 1 r ,iL 'I, ) r .!iL .:c;:;' : i! a n

    , '.1-

    *r-J'*t*u'Y,'
    madu.l,q, ,, , .,,t'., I
    't it j' e' ' - ' iif r en c '''
    ' i' : ( ; : "' ir r ' : ,,
    i
    ;;lotxY 'lt{4so3g' ;
    d'cM{'G','lr
    :;:. I
    i l i rrl l { .i i :;
    , ii : '
    ' rl $i l i r. '
    t?i, ..
    t:a1i.:
    .yr1,,i i,
    ':l;., 'j.. i ::r ;:) ::
    . ,1. 1 ' ';'

    i,,, '
    " tnPut PlYl*
    At B',air'l'S' 5;

    . '' o ' - ' t::' ir i:' J ' :l t' 5 ;


    1t) q
    t 1
    rL'R i stype ' comt
    $ Ul' :, Cit:- r :r r c' u i: P: ll

    ' e(lr:e''r''irJn6 l' ,

    :&, i
    r ,,"s U r{= (A r !B ) $ (fe a B ) '
    "s ''- & Bi
    &;
    i4<.
    "'l''
    I
    t';i,

    . .:.
    ir t, ) ,) ,

    r lr clli r i( i r l l r 'r ( nl

    \vlliclr is c - lr i\ , r l- r i t r

    Hor i' e v e r,tl rerc l a ti o n aol p e ra to(==)


    r gives Qdy_prrg_b1_!,so tirat the restof theequati on
    eval uates
    al sot o one bit , and r lt e
    " 3" is tru n c a re dto ' 1" .. l ' h u s th e a b o vcequati oni s cqualto:

    -afrpe'ators
    'l'lrcrc or c ( bur bas ic t y pc s
    of ol) c r at or s Iogi cal ,ari tl rrrrct
    i c, rcl ati orraI
    andassi gnrncnt..

    a. Logical Opcrators

    Thetablebelorvgivesthe loSicalopcrators.
    Theyareperformcdbit by bit-wi'rlrthe@ALTERNATIVEdirective.one
    canusethealtematiVesetof ooeratorsasindicated
    in thctable.

    O pera to r (d e fa u l t) D e s c ri n ti on Alternate operator


    N O T (o n escompl enrent)
    & AND
    +

    exclusive
    lXn*OR: nor I

    b. Ar ithnr clic,op erators

    T he. t a b l eb e l o rvg i v e sti rea ri th n re tioc p erators.


    N ote tharthe lastfour operators arenot allorvedwith sets.The minussisn
    Canhaved i ffe rc n tn rc a n i n g su:s c db e tw eentrvo operands i t i ndi cates
    subrracti on
    (or addi ngthetw oscom plem ent ;*. hiie
    us edwi th o n e o l )e ra toirt i n d i c a teth s e r w oscomptcnrcnr.

    D cscri oti on
    s compl enrent
    (
    ubtracti on

    Thafollowing operalors are not used with sets:

    r
    ;t
    + ulus:remainder
    of A/3
    *'> ShiftA left by B bits
    a ShiftB rightby B bits

    ;.:siiri&biisdsdi+ l- -ra.rcr:t.i-1:t t:-'.il".'


    "",1 \
    ,.,"4' \-" '/ \
    ,f. \
    //Ilcl cxplir r lr t t t or tol' t lt e s t at c lllc llt s { ir llo r v . l : o r a r r r o r c<i c r ; r i l c d
    r l i s c : r r s s i osrrr}ct l ) c f o l k l r v i u i s c c t i o n so r c c n si .l l t
    ..",,.){tL-tll)l- rrr.rtt'rl'wlrcrru.si.gArr;i. rvitrr,i,. i;l;;;;i'n;;;,,",;;;,;,,,;;,,1;;li* niii,,.wiz,ercr
    :i fi
    "'f tclllpla tc o l' t lr c bas ic s lf uc t ur e and ir t s c r tso r r r c rvrrich rvirrrii',c;
    o f t h e k c y r v o r r i s .A l s o t l r e L a n g u a g eA s s i s t a n ri n t h c
    provides on-lincirelp' Go to theTool-s A B E L c d i to r
    -tr-nNcu,qcb nsstsrnNTnrenu.l'he Languagcrcrnprarcs
    of tttostABELconrrrrand-s' givca
    .:;:::I""" s'rrtax,
    hicrarchl,,
    crc,rvhilcrhcSl,nthc.sis
    rcrnplarc
    r:ivcs
    cxanrptcs
    of tvpical

    3 . D ccl :rt-:lti ons

    ttlicr ttrr:;ir ; r . l r r r r r lr r I it , r r r r t ir r r . :r,' r { ir


    r r r , .r r, , , , ; , i ; , , : . , . , ; ; ; , ; , ', , ', ; , . . " : . ; ; , ; . , , r r ( . r r((,:r.(r:.

    tr:rr()rr'(l l l -\ tlr , r r \ t'r r \Y( t.r r 'r r r :'l


    , r r 11 1r 11,.1lr ,r l r r ir .r r r ,J,, r ,,J ( 1,) ,
    'r r ( .r r ,r l r r r ,

    ,\'trittg: rs it s c r r L
    crrclo'sct1.bv-.s.qg]9,911t19:;
    Srrirrlis
    arcusccrlirr'r'l'il.t.,
    ot'l'toNSsrfrc,ucirs,
    trr p tt't,rrrt<lcalr < i;,r;liffii.:j,.i:;x;i:l;i; i,,r(r

    device; this declaration.is qnclassociates


    Qntional :jgvtqqidg(rrr9r{r{4r;4g,rlie-pl9gglllBu-e-Lo8ggylglThc
    3.u.trupnt-rnu*."'n.{ty^itrjlinxCADsystcmtocornpitethedesign,itis
    Defternot to put the devicestatement
    in thesourcefi'leto keett;u;'J"rig,, ;r,,i.!"ni*ilrii.
    r," -
    a""i*. whenyou crearea
    C",-r!"'i. i"
    ffiJJ,TffJ*J,i'J[,ld'+#tr9"?,",i:"#jg;"i**"4 p,o;"a
    o'. M;;", window,i,i"e
    dev ice _ i dd e v i c e ' re a l d e v i c e ,:

    E x am p l e :MY _ D E C OD ER d e v i c e ,XC 4003E ,;


    L

    ;'-''[lffi" a"1a.sqir;gsd"gurc
    ---'--:-:,i----:.--
    ((
    pin: pjgjgg!3glislsjell&e'cpmPikt$d{'h.sv.rnbqlig-Eaqer-a&-associarcdyjth
    piqs..Format:
    thqcetigs-!,slr'at
    l! J pin id pin tp i n * j Ii s ty p e ,attri butes,j
    ;
    One can ipecifo more than one pin per
    line:

    [!]pin_id, pin_id,pin_idpin Ipin#,[pin#,[pin#]ll[istype'anributes,];

    Example:

    -IN1. IN2, .A1 pin 2. 3, 4;

    O UT 1 pi n 9 i s ty p e . ' re g ,

    E NA B LE p i n ;

    ! Chip_s e l e c t pin 1 2 i s ty p e ' com' ;

    ! S 0. . ! S 6 p i n i s ty p e tco m t;

    effi:ct
    rift rigltt

    ll :i division
    G':signea
    -' N
    rF

    lll ( l

    :i l 1(l

    thenor equal

    le

    [ea
    i

    gic descriPtion
    way'
    describedin the followillg
    A logic dcsign can be

    r Equations
    . Truth Table
    r Statc DcscriPtion

    .a. Eqnations onsusingrhespjeigl:


    r ^^^'i ^ti nnc F hU Atl O ns Sp€ul r J r v 6''v - " r -
    '
    "
    'Usethekqlrwordequati'onstobegintrrlleicdescriptions.Equationsspecifylogicexpresst,
    ,.. statement'
    w.i describedabove,"' "*t:"-Gg;t: is usedIn Ine
    ia, to a rogicfunction'(Note:"lf -Then-Else"
    describe
    starement is usedin_equations
    The"when-Then_Erse, bt progression)'
    iagrat' i
    n"to"d-t'-t'
    State-d ""t'o ""tt
    siaiement is asfollotvs:
    The formatof the"When-Then-Else"
    r c : ';
    f i- lt ii ele r n e l : =e v 'p r e s s
    WHEN c ondit ior r

    . - equat ion;
    ELSE

    THEN e q u a t l o '';
    WH EN c o n d i ti ' o n

    ExamPlesof equations:

    SUM=(Ae lB) { (!A & B) ;


    .A0 := EN & l D l & D 3 & \D'l;

    = A 1i
    Dl -out
    IIHEN (A == B) THEN
    = A 0;
    = = C ) TH E N D l -out
    EtSE HHSN (A XZ I
    gHEN (A>B) ( X 1 ,= P 1; " = D 2;
    THEN

    i!',4' *Yh&61*iit ; *b*,t t:.;J!t1i,iils^^ r*+i


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    t crF- L"- \ A,r ^ ;' ]t

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    LE
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    [C"-
    \dilrr

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    b.7tt

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    Full addercircuit usinga macroof Half adder.

    libraryieee;
    useieee.std_logic_1 164.all;
    entityfa is
    port( xin,yin,zin : in std_logic;
    cout,sum : out std_logic
    );
    endfa;
    architecture fa_structof fa is
    component ha is
    port ( X, y 1in std_logic;
    s ,c :outs td_l o g ic ) ;
    endcomponent ha;
    signaltempO,templ,temp2 : std_logic;
    begin
    ha1: ha portmap(x=>xin,y=)yin,s=>temp0,c=>templ);
    ha2: ha portmap(x=>temp},y=>zin,s=)sUtTtrc=>temp2)i
    cout<= templ or temp2;
    end fa_struct;

    4-bit adderusinga macroof Fulladder

    libraryieee;
    useieee.std_logic_1 164.all;
    entityfa_4bitis
    port( a,b : in std_logic_vector
    (3 downto0);
    sum : out std_logic_vector(3 downto0);
    carry: out std_logic);
    endfa_4biU

    architecture
    fa_4bit_behave
    of fa_4bitis

    component
    fa is
    port( xin,yin,zin : in std_logic;
    cout,sum : out std_logic);
    endcomponent fa;
    sign
    beg

    c(0

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    u2:
    u3:
    u4 I

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    e
    (3 downto0);
    signalc : std_logic_vector
    begin

    c( 0 )<- '1';

    u1 fa portmap(xin=>a(0),yin= >b(0),zin= >c(0),sum= >sum(0),cout=>c(1));


    u2 fa portmap(xin= >a(1),yin= > b(1),zin= >c(l),sum= >sum(1),cout=>c(2));
    u3 fa portmap(xin=>a(2),yin= >b(2),zin->c(2),sum= >sum(2)rcout=>c(3));
    u4 fa portmap(xin= >a(3),yin= >b(3),zin= >c(3),sum= >sum(3)rcout=>carry);

    fa_4bit_behave;

    {/-a
    4 bit adder using GENERATE
    STATEMENT

    libraryieee;
    useieee.std_logic_1
    t64.all;

    entityfa_generate is
    port ( a,b : in std_logic_vector
    (3 downto0);
    cin : in std_logic;
    ': (3 downto0);
    sum out std_logic_vector
    carry: out std_logic);
    endfa_generate;

    architecture
    for_generate of fa_generate is
    componentfa is
    port( xin,yin,zin : in std_logic;
    cout,sum : out std_logic);
    endcomponent fa;

    (4 downto0);
    signalc : std_logic_vector
    begin

    c(0)<= 61n,

    gk : for k in 3 downto0 generate


    u1 : fa portmap(a(k),b(k),c(k),sum(k),c(k+1));
    endgenerategk;

    carry<= c(4),
    endfor_generate;
    Singlebit comparator
    libraryieee;
    L64.all;
    useieee.std_logic_1

    entitycompis
    port (a,b in std_logic;
    X out std_logic;-- a > b
    Y out std_logic;-- a < b
    z out std-logic;-- d = b
    en in std_logic);
    endcomp;

    comp_behave
    architecture of compis
    begin
    process(en)
    begin
    if (en = '1')then
    if (a>b)then
    t1t;
    x <=
    y (=' 0 ' ;
    z <= ' 0 ' ;
    elsif(a<b)then
    x <= ' 0 ' ;
    y (= ' 1 ' ;
    z <= ' 0 ' ;
    else
    x <= ' 0 ' ;
    y (= ' 0 ' ;
    z <= ' I ' ;
    end if;
    end if;
    end process;
    endcomp_behave;

    Comparatorwith EnableBit
    entityComparatorEnableis
    Port( a in std_logic_vector(1
    downto0);
    en in std_logic;
    Gr out std_logic;
    Le out std_logic;
    en

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    Eq : out std_logic);
    endComparatorEnable;

    architecture
    Behavioral
    of ComparatorEnable
    is

    begin
    process(en,A)
    begin
    if (en = '0')then
    Gr <= '0';
    Le <= '0';
    E q< = ' o ' ;
    else
    if (A(1)> A(0))then
    Gr<= '1';
    Le <= '0';
    E q< - ' o ' ;
    elsif(A(1) < A(0))then
    Gr <= '0';
    L e< = ' 1 ' ;
    E q< = ' o ' ;
    else
    Gr <= '0';
    Le <= '0';
    E q< = ' 1 ' ;
    end if;
    end if;
    end process;
    endBehavioral;

    4 Bit Comparator
    entityComparator4bit
    is
    Port( A in std_logic_vector(3
    downto0);
    B : in std_logic_vector(3
    downto0);
    en in std_logic;
    GT out std_logic;
    LE out std_logic;
    EQ out std_logic);
    endCompa
    rato14bit;

    architecture
    Behavioral
    of Comparator4bit
    is

    >)

    7
    1- r .
    r component ComparatorEnableis
    (
    Port a : in std_logic_vector(1
    downto0);
    en : in std_logic;
    Gr : out std_logic;
    Le : out std_logic;
    Eq : out std_logic);
    endcomponent ComparatorEnable;
    signaltemp:std_logic_vector(10 downto0);
    begin
    U1:ComparatorEnable portmap(a(1)=> A(3),a(0)=> B(3),€fl =) en, Gr =>
    temp(O),Le= >temP(1),Eq= >temp(2));

    portmap(a(1)=> A(2),a(0)=> B(2),€n =) temp(2),Gr


    U2:ComparatorEnable
    \ => temp(3),Le
    =>temp(4),Eq=>temp(S));

    U3:ComparatorEnable portmap(a(1)=> A(1),a(0)=> B(1),efl =) temp(S),Gr


    = > temp(6),Le= >temp(7),Eq=
    >temp(B));

    U4:ComparatorEnableportmap(a(1)=> A(0),a(0)=> B(0),en => temp(B),Gr


    = > temp(9),Le
    = >temp(10),Eq=
    >EQ);

    GT <= temp(O)or temp(3)or temp(6)or temp(9);


    -,t Lf 4= temp(l)or temp(4)or temp(7)or temp(10);
    \
    \_-.,
    <{ \ end Behavioral;
    '-t/'

    4xL Multiplexer
    libraryieee;
    useieee. std_log
    ic_1t64.all;

    entitymux4_l_ifis
    port(a: in std_logic_vector(3
    downto0);
    s: in std_logic_vector(1
    downto0);
    y: outstd_logic);
    endmux4_l_if;

    architecture
    mux_behave
    of mux4_1_if
    is
    begin
    process(s)
    begin

    t
    t
    ifs=" 0 0"then
    y <= a ( 0);
    e lsifs="01"then
    Y <= a (1);
    e lsifs="10"then
    Y <= a (2);
    else
    Y <= a ( 3);
    end if;
    end process;
    end mux_behave;

    4:1 Mux usingCasestatement


    libraryieee;
    useieee.std_logic_1
    164.all;

    entitymux4_1_case is
    poft (a: in std_logic_vector(3
    downto0);
    s: in std_logic_vecto(1
    downto0);
    y: out std_logic);
    end mux4_l_case;

    architecture mux_behave of mux4_l_case


    is
    begin
    process (s)
    begin
    cases is
    when"00"=> y<=a(0);
    w h e n" 0 1"=> y <= a(1)i
    w h e n " 10"=>y <_a(2),
    whenothers-> y <= a(3)i
    endcase;
    end process;
    end mux_behave;

    4=L Mux usingwhen statement


    libraryieee;
    useieee.std_logic_1
    t64.all;
    entitymux4_l_whenis
    port(a: in std_logic_vector(3
    downto0);
    s: in std_logic_vector(1
    downto0);
    y: out std_logic);
    end mux4_1_when;

    architecture
    mux_behave of mux4_l_whenis
    begin
    y (= a(0)whens = "00"else
    a(1)whens = "01"else
    a(2)whens = "10"else
    a(3);
    end mux_behave;

    4:1 mux usingwith-select


    libraryieee;
    useieee.std_logic_1
    t64.all;

    entitymux4_l_withis
    port(a: in std_logic_vector(3
    downto0);
    s: in std_logic_vector(1
    downto0);
    y: out std_logic);
    end mux4_1_with;

    architecturemux_behave
    of mux4_l_withis
    begin
    with s select
    y (= a(0)when"00",
    a(1)when"01",
    a(2)when"10",
    a(3)whenothers;
    end mux_behave;

    2=4DecoderusingWhen-else statement
    libraryieee;
    useieee. std_logic_l
    t64.all;

    entitydecoder2_4
    is
    I

    port ( a : in std_logic_vector(1
    downto0);
    y : out std_logic_vector(3
    downto0));
    enddecoder2_4;

    architecture
    decoderbehaveof decoder24 is
    begin

    y (= "1110"whena = "00"else
    "1101"w hena = " 0 1 "e ls e
    "1011"w hena = " 1 0 "e ls e
    "0111"w hena= " 1 1 " ;
    enddecoder_behave;

    3:8 DecoderusingWhen-else statement


    libraryieee;
    useieee.std_logic_1
    164.all;

    entitydecoder3_B is
    port ( a : in std_logic_vector(2
    downto0);
    y : out std_logic_vector(7
    downto0);
    en : in std_logic);
    enddecoder3_B;

    architecture
    decoder_behave of decoder3_B is
    signaltemp : std_logic_vector(7
    downto0);
    begin
    temp<= "11111110" w h e na = " 0 0 0 "e ls e
    "11111101"w h e na = " 0 0 1 "e ls e
    "11111011"w h e na = " 0 1 0 "e ls e
    "11110111"w h e na = " 0 1 1 "e ls e
    "11101111"w h e na = " 1 0 0 "e ls e
    "11011111"w h e na = " 1 0 1 "e ls e
    "10111111"w h e na = " 1 1 0 "e ls e
    "01111111"w h e na = " 1 1 1 " ;
    y (= =
    tempwhenen '0' else
    (others-> '1');
    enddecoder_behave;
    Parity Bit

    entityparitybitis
    Port( x : in std_logic_vector(4
    downto0);
    y : out std_logic);
    end paritybit;

    architectureBehavioral of paritybitis
    component xorl is
    Po rt(a:i ns td_l ogi c ;
    b : in std_logic;
    z : out std_logic);
    endcomponent xorl;
    signaltemp:std_logic_vector(3 downto0);
    begin
    uk: for i in 4 downto0 generate
    ukO:if i=4 generate
    a:xorl portmap(x(i), x(i-1),temp(i-l));
    endgenerateuk0;

    uk1:if i<3 generate


    b: xorl portmap(x(i),
    temp(i+1),temp(i));
    , endgenerate uk1;
    endgenerateuk;
    y<=temp(o);
    endBehavioral;

    BCDdecoder

    entityBCDdecoder is
    Port( x : in std_logic_vector(3
    downto0);
    y : out std_logic_vector(6
    downto0));
    end BCDdecoder;

    Behavioral
    architecture of BCDdecoder
    is

    begin
    y <= "0111111"
    w h e nx = " 0 0 0 0 e" ls e
    "0000110"
    whenx= "0001"else
    whenx= "0010"else
    "1011011"
    "1001111w"h e nx = " 0 0 1 1 e" ls e
    whenx= "0100"else
    "1100110"
    whenx= "0101"else
    "1101101"
    "1111101w"h e nx = " 0 1 1 0 e
    " ls e
    "0000111"
    whenx= "0111"else
    "1111111wh
    " e nx = " 1 0 0 0 e" ls e
    " e nx = " 1 0 0 1 e" ls e
    "1101111wh
    "0000000";
    endBehavioral;

    Adder usinggeneratestatement

    entityadder4_generate is
    Port( a : in std_logic_vector(3
    downto0);
    b : in std_logic_vector(3
    downto0);
    cin : in std_logic;
    sum : out std_logic_vector(3
    downto0);
    cout : out std_logic);
    endadder4_generate;

    architecture Behavioral is
    of adder4_generate
    component Adderis
    Po r t( x: i ns td_l ogi c ;
    y : in std_logic;
    ci : in std_logic;
    s : out std_logic;
    co : out std_logic);
    endcomponent Adder;
    signaltemp : std_logic_vector(3 downto0);
    begin
    ad: for i in 3 downto0 generate
    ad0:if i=0 generate
    addl: adderpoft map(a(i),b(i),cin,sum(i),temp(i));
    endgenerate ad0;

    ad1:if i>0 generate


    add2:adderportmap(a(i),b(i),temp(i-
    1),sum(i),temp(i));
    endgenerate ad1;
    endgenerate ad;
    cout<=temp(3);
    endBehavioral;
    BCDAdder

    entityBCDadder is
    ( downto0);
    Port bcdl : in std_logic_vector(3
    downto0);
    bcd2: in std_logic_vector(3
    carryin: in std_logic;
    bcd_sum: out std_logic_vector(3
    downto0);
    carryout: out std_logic);
    endBCDadder;

    architecture Behavioralof BCDadderis


    component adder4_generate is
    Port( a : in std_logic_vector(3
    downto0);
    b : in std_logic_vector(3
    downto0);
    cin : in std_logic;
    sum : out std_logic_vector(3
    downto0);
    cout : out std_logic);
    endcomponent adder4_generate;
    signalB,x:std_logic_vector(3
    downto0);
    signalc,k:std_logic;
    begin
    bcdaddl:adder4_generate portmap(a(3downto0)=>bcd1(3downto0),b(3
    downto0)=> bcd2(3downto0),cin=>carryin,cout= downto0)=>313
    > k,Sum(3
    downto0));

    c (= k or (B(1)andB(2))or (B(2)andB(3));
    x(= "0110"whenc='1'else"0000";

    bcdadd2: portmap(a(3downto0)=>B(3downto0),b(3
    adder4_generate
    >carryout,sum(3
    downto0)=>x(3downto0),cin=)'O',cout= downto
    0)=>bcd_sum(3downto0));

    endBehavioral;

    LookaheadCarry4-bit Adder

    entitylookaheadcarryis
    (
    Port A : in std_logic_vector(3
    downto0);
    B : in std_logic_vector(3
    downto0);
    Cin: in std_logic;
    lq b o^,
    i I r'l-
    end
    i o-'r^)J
    arc
    s) 9v
    -'
    f,h l \ 4 Lr ! cr-
    t ,lr-r Jl - ) Yv 0-
    <-l -l'
    v 9:,

    IJU rI t '

    Lo L--

    en
    r(i

    at)

    r^(2
    ('t L

    3l'li

    cl

    C1

    eI
    ('<t Sum: out std_logic_vector(3
    downto0);
    - Cout: out std_logic);
    =T end lookaheadcarry;

    I architecture
    Behavioralof lookaheadcarry is

    r begin
    signalc: std_logic_vector(4

    91: for i in 3 downto0 generate


    downto0);
    signalp,g: std_logic_vector(3

    P(i)<= A(i)xor B(i); 'z


    g(i) <= A(i)andB(i); "/
    downto0);

    Sum(i)<= p(i)xor c(i); .--


    endgenerate;
    c(0)<= ern;
    c(1)<= (Cinandp(0))or g(0);
    c(2)<= ((Cinandp(0)andp(1))or(p(t) andg(0)))or g(1);
    c(3)<= 1(Cinandp(0)andp(1)andp(2))or (p(2)and p(1)andg(0)))or g(2);
    c(4)<= ((Cinandp(0)andp(1)andp(2)andp(3))or (p(3)andp(2)andp(1)
    andg(0)))or g(3);

    Cout<= c(4)i
    endBehavioral;

    +ve edge triggeredAsynchronousD flip Flop


    entityDFFis
    Port( reset,D: in std_logic;
    clk : in std_logic;
    Q : out std_logic);
    end DFF;

    architecture
    Behavioral
    of DFFis

    begin
    process(clk,reset) V
    begin
    if(reset='0') then \/
    Q <='0'; v /
    elsif(clk'eventandclk ='1')then.
    Q <=D ; \/
    end if;
    end process;
    endBehavioral;
    enti
    r
    i .,^ .M - . r, -\ i-))
    end
    e^..,Ah^*l
    ; ard

    q-\e,L*+o-.-L=J-*--\*'t- t---l ' 4 beg


    Y o)
    : kV\- fud .- -*'"*-(-u^-fr -a+'"r'^'(o
    .l.,'^^,..-f
    3f*
    b^"".
    cJk,*y)
    F-""uu* t
    L"4,"""1
    '-'\ (
    rl \' hst-^k en
    u
    (=tb.oo7;
    T \-1'<'\
    [ *J' cJk
    "!-afl '[]+-L'^""^t- -'u')
    = ) - t"^1( >- - +*"""ft1;
    *1,, et

    e"^"'LF-."
    "f_,
    1, <>"*, e
    ""A t J"^; a

    b
    -ve edgetriggeredFlip FloP

    entityDFFis
    Poft( reset,D: in std_logic;
    clk : in std_logic;
    Q : out std_logic);
    endDFF;

    of DFFis
    Behavioral
    architecture

    begin
    process(clk,reset)
    begin
    if(reset='0') then
    Q <='0';
    elsif(clk'eventandclk ='0')then
    Q <= D ;
    end if;
    end process;
    endBehavioral;

    4 bit Shift Right

    entityShiftRight4bitis
    ( downto0);
    Port datain: in std_logic_vector(3
    downto0);
    dataout: out std-logic-vector(3
    clk : in std_logic;
    newdata: in std_logic;
    reset: in std_logic);
    endShiftRight4bit;

    Behavioral
    architecture is
    of ShiftRight4bit

    begin
    process(cl
    k,reset,newdata)
    begin
    then
    if(reset='1')
    dataout<= "0000"i
    andclk='0')then
    elsif(clk'event
    dataout<= newdata& datain(3downto1);
    3-
    I
    I

    D*-c*J*= Cs<""^.(s.
    I
    l.r. r
    A/,."/fld*4 d<r1_
    rI
    \A
    v

    lirr-.-k- [ r{.\z\
    MJ-k7u (= *"^'-#" 9,
    *vR-{,,!-,sr
    1
    "[ : end
    (!.k ,.
    \r/* Arcd^ {*?.j
    qr
    w e""rt A-1-.\- [B?'. - v€e4€{ C3 a^n ru$.'e " ) t
    ,)

    Ix^^,t : '6^ ,b.U*\*?-c );


    Itr
    ent
    5v-o\ d^-<- .) I
    /

    *rr.€il+e-<Jk^r-\€- Ltt ='1 &o ta


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    erx
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    ue,.!s( "lk 1A""^t )
    f* bet
    L^T'^"
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    \)
    o' ) +'.'v
    I

    I""^"{" <= +*-'.4.1 l en

    v* <
    \4 \

    h
    s t a
    \t &r
    \

    W {==- &

    4"i&
    {*^^\

    q4" ' , el

    *)
    al

    €^^^
    **[\"

    tr
    ] h

    @'7/

    e"^A f."rl^;
    endprocess;
    endBehavioral;

    4 bit Shift Left


    entityShiftLeft4bitis
    Port( datain: in std-logic-vector(3
    downto0);
    clk : in std_logic;
    reset: in std_logic;
    newdata: in std_logic;
    dataout: out std_logic_vector(3downto0));
    endShiftLeft4bit;

    architecture
    Behavioral is
    of ShiftLeft4bit

    begin
    process(cl
    k,reset,newdata )
    begin
    if(reset='1')then
    dataout<= "0000"i
    elsif(clk'event andclk='0')then
    dataout<= datain(2downto0) & newdata;
    end if;
    end process;
    endBehavioral;

    SynchronousD flip flop


    entitySync_DFF is
    Port( reset: in std_logic;
    D : in std_logic;
    clk : in std_logic;
    Q : out std_logic);
    endSync_DFF;

    Behavioral
    architecture is
    of Sync_DFF
    begin
    process(clk,reset)
    g"4;*\ )^^ \ P o."*-tl.p-La \"+-

    a/-a- [*-6,i. -v"*-xoz-t= *,

    ["qa.
    ol
    ti-t( ,Wq
    flracP'-5 \
    h9)tA
    "7"t! |
    (h^""t- =' | ) JLa"4
    t 0\ . 1
    d^,t-- "-\ts '-
    \ tl.kt<^^^-a^tsL-
    c'tf< '-\' ) +t*-
    \
    ;^b t
    #1.,
    b"" LP^AL(9
    t c-(k *to' ) +ut
    v L e-0-Jrf
    e^,-a/*-q'.

    fr,r
    '.}.tf,- *bo\t'
    ^1" t ' \ \ ^ ' e ' ")
    " c-2 -t1,- '
    J4""^ hL )
    1 < i %t . o'
    *"*d;
    '^ - - t
    .^Jil- )
    uJf*e-u\^ )
    e€l,'
    ( +*19
    W
    *ffi
    h^ar
    ) +^"-
    b"4pL
    +"^,-{fl}-\.^--u^0=*-
    "o' ,i l

    L)
    begin
    if (clk'event and clk = '0') then
    if (reset= '0') then
    Q <='0';

    end if;
    endif;
    end process;
    endBehavioral;
    EDATools
    1, DesignEntry
    .ViewLogic
    .MentorGraphics
    (Renoir)
    .CadenceDesignSystem
    .OTCAD
    .ALDEC(ActiveHDL)
    .SimuCAD(Silos-3)

    EDAToo|s
    2.DesignSimulation
    .ModelTechnology (Modelsim)
    .Synopsy
    .Cadence
    .SimulCAD (Silos-3)
    .Quickturn DesignSystems(PowerSuite)
    .ViewLogic(VHDSimulator)

    EDATools
    3. LogicSynthesis
    l.Synopsis
    .FPGAExpressway
    .FPGA Compiler
    (Synplicity)
    2. Synplify
    3. Exempler Logic(Leonardo Spectrum)
    4, ViewLogic (Intelliflow)
    5. Cadence DesignSystem
    6. Aldec(ActiveSynthesis)

    EDAToo|s
    4. ProgrammableLogic(Vendors)
    .Xilinx- XilinxFoundation
    Series
    .Altera- MaxPlus II
    .Altera- QuartusII Ver.4.0
    .Lattice- isp ExpertCompiler
    .Lucent- ORCAFoundary Development

    il
    .Actel- FPGAOeeopmern gen
    'Cypress-Warp2
    .Atmel- FPGAOeeoprnent Sl/*nt
    .QuickLogic- Qr[* works
    .GateField- ASICMaster

    OtherHDLs

    1) ISPS(InstructionSet Processor
    Specification)
    -Behavioral
    Language
    -Usedto designsoftwarebasedon speciflchardware
    -Statementleveltimingcontrol,but no gatelevelcontrol

    2. TI-HDL
    .TI-HDL(TexasInstructionHardware
    DescriptionLanguage)
    {reated a TexasInstruments
    -Hierarchical
    -ModelsSynchronous andasynchronous
    circuits
    -Non-extendable
    fixeddataWpes

    3. ZEUS
    - Createdat GeneralElectric
    - Hierarchical
    - FunctionalDescriptions
    - StructuralDescriptions
    - ClockTiming,but no gatedelays
    - No asynchronous circuits

    4. TEGAS
    .TEGAS (TestGeneration AndSimulation)
    -Structuralwith behavioral
    extension
    -Hierarchical
    -Allowsdetailedtimingspecification

    5. Verilog
    .Verilog
    -Essentially
    identicalin functionin VHDL
    -Simplerand syntactical ly different
    -GatewayDesignAutomation Co. 1983
    -Earlyde factostandardfor ASICprogramming
    -OpenVerilogInternational Standard
    -Programming Language Intefaceto allowconnection
    to non-Verilog
    code
    6. ABEL
    .ABEL
    -SimplifiedHDL
    -+LD Language
    -Dataflowprimitives
    e.g. registers
    {an useto ProgramXilinxFPGA

    7. AHPL
    .AHPL(A HardwareProgrammingLanguage)
    -Dataflowlanguage
    -ImplicitClock
    -Doesnot supportasynchronous
    circuits
    -Fixeddatatypes
    -Non-hierarchical

    B. CONLAN
    .CONLAN (CONsensusl-ANguage)
    -Familyof Language
    for describing
    variouslevelsof abstraction
    {oncurrent
    -Hierarchical

    9. ALTERA
    .ALTERA
    {reated by AlteraCorporation
    -Simplifieddialectof HDL
    .(AHDL:AlteraHDL)

    10.CDL
    .CDL(Computer DesignLanguage)
    -AcademicLanguagefor teachingdigitalsystems
    -DataflowLanguage
    -Non-hierarchical
    {ontai ns conditiona
    I statements

    1 1 .ID L
    .IDL (InteractiveDesignLanguage)
    -InternalIBMLanguage
    -Originallyfor automaticgenerationof PLAStructures
    -Generalized to coverothercircuits
    {oncurrent
    -Hierarchical

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    D3 entitv e n c8 x3 i s
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    architecture beh of enc8x3 i s
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    e n d if;
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    en d pr o ce ss;
    en d be h ;

    Page 1
    B C U to Ex-c.'e-a-3

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    \1
    w1
    4o
    q*-
    r7A
    t<d{tr" .\ i--n G.t j
    ":u I'
    *
    :t
    **@a
    t!
    aq
    ,
    B:-
    Xg

    6!
    a
    &fo

    #"t
    *r &*r$o \f ,$,

    l-x'&
    4 Bn+ e*.'t e\

    ;c l
    o
    Lor

    *rrrQJ>
    1eM

    t!
    I xt- izzv\if
    \Pl

    \"'L*

    v 7f 2- l,4t o;', ' \

    Bl
    Ar
    +1, fl5 ( 44Ao
    h rb t /t-r tj-o t) L-
    LL al 1
    b&^J<_- C€.^"^-[e4

    (l<- D fs--B C- D D4 4 D. DD
    4
    ce-'-e---e-'e e>-e-=-< I ootoI
    &o c , - 1 t O@tt:
    oo( 9
    I
    00t i
    ,o o t o , @ c9t
    ol0o
    Oce t1 o{oo
    o lo o o1()( o, l I
    al
    o 1o t o 1t o o |
    I
    o
    1 |
    O t(o o tl a tl n
    t t o oo
    o t"L r: 0
    'l"oi 0
    o o 10 c1 1
    to tonl
    c> O oo
    La o I Dva

    L- 4.\
    .---l
    R{ X g -X-\
    vl /n""'1
    z
    V-l
    n x
    \Jrr:

    (y \l
    -l b4?
    [ ', ,

    '*_ h
    I ")WU
    \\
    y-\
    co*d,- d/
    a*
    Ut^

    Ct^1

    lS /a'* e
    3 A'e.-to o
    4t (!_N-
    \ 4Ljxs b <<

    2( ..1
    >

    v f-A-L
    7
    s ea
    &h I I\\/\/A
    sa-
    Jo 3 r
    g--e
    ,--@
    |

    5-
    5,
    5v
    _t
    :_.-.--(jr,l tTrtn \\r)
    D c ,){ - !.

    - i i-llJL:!lt*:s
    I QL"llll l!,_.\rillgg Ks
    .,,nj , , ' rn ; r pa,n < J %
    313
    I U nct:)n s rC adf r O f n
    ryfL 4 t^b rr
    rod b_.si a rr;ng wit h ilfl
    rFfl
    EA.*j
    counr,errtG;@"p*
    (t2_1) A' = D, so.theD
    inputmapis idenricat
    I::"-,:]":fj:fl
    map.Thercforc. rhc,.:r1r.*irn w,itht h e : x t - s t a t e
    [or /.)cirnlr. ooli';rfi;H:l;l: -
    lhc c.untcror i.rg.ll..'l..rirc 0 : a p .F o r
    cs, lhel foltr*,,rg.qultion, can be
    mlrpsshownrn i.'rg.il 4{il)j readf.romthe . xt - st at e
    (t2-2)
    l ),, l ,= lJ Ii ,, ll'
    -,,1 + I1("
    ti , ('' l (" , lit (' ,1/ i lt\
    ' fh is
    (t2*3) lca d r to l l rc nr:{r,,1).h \i j ()w t.l
    rrr l .' i rt l J i i ri si ngclockcd
    l) ilip-f),

    {12 4) ,', I
    !,'
    i
    .L
    -""---'
    ll f""a."
    (l 2-5) I II;FI
    t)
    ,,1
    I
    | ii
    l iiri h I
    yF.*_-J ',
    I
    Yj
    (t2-d1 L/--\
    tt\
    tt!
    i t!
    I ttl

    ttl
    -*l),fetrint0=0 ; 'r--;
    rinaring Q Equa_ i (
    ,,^\
    rP for Simitarly, j
    -r.
    lll of the (, * rnap rl i
    i\
    I F_ - .=\

    :drcared bi (t2_5).
    - - +- - - _
    F r g r r i.: l2 ,li
    forflip-flcpQby co u r tr r o l F r g l,t r ' 1itlq a) |l{ i ;i ( l l j J

    :
    I
    r: :e. / an d K a r e
    #|
    ittl
    l2.z
    Design ot it C*rtlc COnvel't.,er
    i o op i h c l l r o n
    j,ll:,;::;'i.:i::jjr ltri'ri'.'iif'r c.rr'rt:,'t:,ini,r:arrpri
    llf t \ ' / of k J..l:'','1
    whic it h ;rs ir ,,rlr.ijij irt lse
    tcrJto
    unl scr.ll , t i; t
    i n F r t r l f 1 3l i r i l
    t, : op irc i /l r on cxterriat
    inpirs.i.,,,..,,,,ir.i,,',.,,^r,.i,ll',i,i:,,.,i,;ili:r]::': her
    i,il('c.nir:rrcr rrr:i,ri
    :njit:: ::l "" ..,;- .l
    t,,,,, '' tir,j,'
    i i l ' :r,,f.'l:,
    r ( ) L ) sl i l l l ,."tr'l:',;;tl,;tj;]"tt,l.i;;;j_l:,llJ:
    l l l l l - i '. r t t l r f : h c ] - t t " 'l f -., 9 r s
    s t r - lr c d, ,. r, tr1,
    , , !. ,/itiri,lr' , ,r r" 1
    , ',i 3, ,,', , \ j 'r i 1 digits t) ihrou

    ;:[:; ;*: ll'+j:i:;i,:,,ii*i,'.


    i r i r r i l c t i . r ; l i . " f l t l l j llr:
    :i ( rler Ii tC sl ,an_
    .i:ilsary.{?) The
    i;I;;;[;;l:fi:";:l;,ffi:[:'i;:
    yertcris giv.e'briTairjc-t.t
    i";:;,,;; l'r'il,t
    :if'::,,
    t : thc
    t l t c ne*r,ork,
    n e l r , , , ^ r l . the
    r h o ,correspc
    . : : : ^ *. jr ng
    rl Il -
    rtr e Jq a n d Ko inpr:r
    eoriarions, and
    ir.,...,,,,i,,'i;;,r;;i' i- K
    the l-li r(l r;!lrr,r, 'i irc ,:ircui,,t'
    ir:.:;l;:;l';1.1i."fXli;
    1,1f o
    lerile i,; irrrri;rltr,
    i,r.,.i,^^,r.^ rr..n
    llL)

    iEsr-E-

    ary
    t

    I
    I l
    ,}
    ri
    :J
    iI
    .g
    ,f
    I

    -;::.. fOr :be

    coUn'ELs--
    3 r{ trIT 12 --

    - a a e '2 -8
    5b:e -id€ for Cod€ Converter
    trz_
    shift l
    0000 0 A sh lt reg
    0001 U
    TlrisnumLr-
    0010 0 t tl u l -
    .h :i '
    0 t) I I 0
    0 l tl 0 U type, orts
    0l0l i lllust r at esi
    0 rr0 I init ii I cont
    () i I I I il sc(on(l p
    lOuu I ,'cgisrr t()
    r i.:rrint
    l0ul I
    , hc r 'r put t
    lr y t l c shr f t .
    'lt Jl- 1i. . r 1, , ; r r i: nPu:
    ,l cloclcd I i. . e st t le
    ,ftd.
    'l'o
    lr ssu-
    i.

    AB JA ,. X't gl ()l ll l0
    g) 0'ill l0 ,r f st at c of t
    Jt, I I x I
    t-{) 0 0 x I * 'j'_ V l S C . 5!v C l r
    Ui 0 u I 0 nt o t nc illP: : :
    {rl 0 I x I K 'D r he
    0 x , lclr ', . . , \ ilcr
    !'_ 0
    71 I
    tl
    : tL x x
    JD IU x x
    I
    I
    li-- I

    r0 0 1l x
    DN
    A rril

    Jo = t.l)
    J6 = I)
    Alr :' (

    A, ' i) '
    , I)
    r D*
    K ,r= o

    '
    A i ," I
    m
    tl
    ii_ S' di'115.
    : : - oblem

    _l _
    l]_ ou t put
    h r r hich
    .\l rrl t r ns r rr t d
    ,. I K t ltttlri. : ) c st . it c
    A. J\

    1ucr r l; ai

    I
    L__,

    I -
    ***1
    S hrl .
    Convcrt p ul rc r
    pulsc tpure 12-l3
    trgure12-'l2 CFIKRight.!lrtt Ilcr.;i:tcrr
    g:D to €xces'3 CodeConvertet
    n/__J 0t' sTA'rll(;lt\PIls,,\ND
    DBRIVAT|0ll T\nl,lls 359. I
    I

    'ms for the

    ffif l1.l
    d f, Design of a SequtnccDet,ect,or
    T ' o i l l u s tra tc th c dcl grt of .i .l ' .rc!.cdi rl trrl y scqtreti ti l rlnetrvork,w e \\i l l dcstgna
    'lhe
    dctecior. nr'lwtirl'hrs-1iTffiil-iil;;rn f,S'la-f .
    scquencc
    Ilu $Tt:lrs--
    '---.--

    r-__l
    12,
    r-l f- - ,'
    L__.. I

    ihifr 1 ( i ,rl

    F(lure14-1
    sh ft reg
    Detcrtorto b" Dt-,'grcd
    Sequerrce
    Lis numLr.-
    , t(' | ,r,,r-

    pe, oits
    The networkwill examinea stringof 0'sand I's appliedto thc X input ind gen-
    u s t i"at e si
    eratean output Z:1 only v,,lten a prescribed input seo.uenceoccurs.It will bc
    it i ; I c onl pulses. we
    assumed that the input X can only change betrvcenclock Specifically,
    sc(dnd p produce
    in-!-0!will an
    willdcsignthe netrvorkso th{rtirn)'inPtrtscqucnccending
    b'.' ! ' t \'
    t rirr.r tzr
    I lcmn g output Z = I coincidcnt*'ith the last l. The nctworkdocsnot re-sct when a I
    E i . t p ut 5
    outputoccurs.A typicalinput scquencc 3nd thc corrcspondingOutputscquencc
    ' ti c shifr
    . th. .^^!,r flrc
    P ' li( )l )\;l t " "Yul
    tl tr c I L',1I'
    tt c s t at e X: 0 0 I I 0 lr0 0 i0 l0 l0 0
    a'
    | () ils \ l l
    ' n ^?
    Z.= 0 0 0 0 o ro 0 0 o 0 l0 l0 0 (1 4 -l)
    rta t c of t (rime: 0123 4 5 6 7 8 9 l0 n t 2 t 3 1415)
    i'C. 5!. \'Ct-il
    Iniiially',*'e do not know horvmany flip-ffopsrvill be rcquilcd'so wc will dcs-
    ii thc t lip ,,
    <e t he ignaterhenetworkstatcsas .tn,S,, etc.,and latcrassignflipflop stalesto corre-
    a ; . . , \ ll cr
    spondto thcnctworkstatcs. Wc,villconsiructI statcgraphto shOwthesequence
    oI statesar:J c:utfuts\\!ric]roccrrrin responsc to diflerentinputs.Initially,we
    will sfarf ihc net\\'L)rk in :t rcsctstatcdcsignlrtcd S6..ll a 0 input is rcceived,
    q we arc lookingfor docsnot
    thc nctworkcanstat'in.\..stnccthe input scqtrcnce
    start \\'ith 0 Hou,evcr. if r I is rrceived wc must go to a ncw state(Sr).to
    "remember"that l.:e irrsi input in the desiredsequence has been received
    Fig. la-21.The labelson i:.cgrapharcof thefc,rmX lZ, wherethesi mbolbcforc
    6 1 . 1 1 ) f tl t,
    ,rhc.,lash is thc input ,rnCll'.: s',r::rolaitcrthc sllsh is thecorresponding output.
    :robiem
    ourput
    h rvhich
    rl ts rrr. t d
    l c sl i tt e
    ;u crrt i al
    Figur e14- 2
    i ---
    l"_

    (rJ r9t (]f!


    300 Il N fl t4
    um-
    W h c n i n s l l tc .!,, lork
    i f i l c rcccrvc nol
    (.1 ' r)to rc l rrr:rn l -* r
    tl rl rt nrusl changc to a rtw new $rare
    rcicived.
    tl re f i
    ';:::,;::,'::''.i:::: ll,,l,,ll.Iliork
    l l Jrl t(r 0[ l l rc w ;rtdtt
    Jver,
    rr ; ; i; n statc S\_-
    tl csi rr:d scquencc
    . - r - - " ! e (l
    1 rt))
    'r 7 have
    t t a v E been
    ', tttl
    h cad
    Ae^-:,,
    s i r e d,
    o cen c:ln
    rheourpurshollJ d
    bc -
    seguence (l0l) is com- input
    slJ:",:rg
    nould
    \tl .tc (,r I'J.,.:,T',,nu
    th c n g < >l o ;1 y 1 ,;11. iir.,
    1 Trre ^.,^^.:
    Jr,l,il
    ., .si,rcc :;"Jfi ;:l
    s u p p o s e dIo rc .i (.t jl;::1.:" ,,r.!,
    i r h c n :rr r r]sl i \rrl ;;;';;.,;:,1,",,,";:l
    l:,
    stttcc lltc l;r :,i
    i r lr .r \r ,lr t( .r i . '':.,;u:- go hack,,,.s,,r.i,*"r.,.
    \. (.u! ;].,:,
    r1.,,, ,.,,1,,1,,,
    1.,.lJrr.lrrrl I ,,,',,
    r e ttl1 1 ) { ( ) ,\, ;t.r
    r tr ,lr e ;ti,r l r ;r i tr. ,,.* r;:;,;jr,:.t;.J,|l
    ij

    ''z^.
    . / - 'r
    '., / ..r/-\,

    -{ '' ')
    z--t
    i 1 'r/,, 5r.
    \--l' I'
    tigure l4-3 r .il

    3t e
    her
    Thegraph t'*
    is:rit incomprere.rf a r inputoccurs
    fablFrg.
    we canstayin"'s' since
    ,lr ,', whenin states1,
    rhe'sequenc. ir-ri.nply. nes
    state.9,we havereceivccJ *r,"r,"a. i" 0""0",
    ,*,, 6,rin o',n* occunin :n
    mustresctrhcnetworkto
    i:llT#_i',Hi 1:,::t,r.," .r",i.i'iniul'Iou.nce,.and
    "nO rtate
    going
    tooneorrhe
    c,rher
    iffi
    li.l"i*Tirilfl*{f;ix
    ,f.J,J"*l,ily,{.!ili:i;:ff
    j;;;
    rin.,,r.p,n i,;;;*i"Ji,n
    ;;',;',j;i:#li:Jil:?;1,;j,,, r,*,ofcnrry

    Figurel4-4 rl
    Mealy State Graph.for EN
    SequenceDetedor
    tcs
    ph
    StateSu is thc sti ls
    tras
    oeeri thata scquence
    ;;il'illiffj';,,]j;ili,;l',j'1''o''r enciinginr r ll
    'e"..i'.,,,
    rcccrvcd.
    An arrornariu. ,t sc(tucncc
    cntting
    in r0 rras"ucci .re
    ,u,,u',j:;;::';;::::;ll

    *L+",+
    labeiedl/1. Thismeunli
    tru;::fr
    l*t#:T,i[i:ii*p{'3i'"'T"fi:
    o'i;;.,; ,;;:,:.^::'n't'
    thc arc berween
    sr .na-i,'i, vo
    outputis l. This , ot*'no'whenthe prcsent srateis s. andxl r
    thepresent,
    .r,,,,o,."i,';;;;;:1:;.::'::::il:i',.,:]:"asxu"com.,.I,,hu.,isbe[orc
    Att th
    A this
    is p
    p.rint,
    ()i 1 1 t,w in tl
    j -t: Iri rcco tn tlrc.9.,
    tc.9.,row
    row of thc
    thc'table. :
    wc c .rc
    irrc rc,rrv tabl i .
    aes
    .
    c,inea rt:;rrtv;:'
    t r',il.',*,,.T; ;.,"rtir..'.",,r,::,rn.;_.
    ,{a..r....
    lltrtced
    fi;.i#,;;,ili'i:, l ".*, r*,t: I
    I

    ________

    ri.
    :, ;$
    \ \
    \
    t DBHMTION 0F STATIiCR{I'I|S Arr*l)TAltl,tlS 361 ' . 1

    Tabre14- I
    f-;tate
    ' )een
    orn- il
    N,:ttSt.tc
    It rcrcn I
    ()urput
    l,rcsjnt fi
    lork Sr ar c l l . \ *0
    - ----*-*it- --
    . Y =l X-0 X *l
    not so so sl 00
    Ii
    s, ll s, s,
    lverr
    can .s:
    '
    So .sr I 00
    0l

    llip'l)opr,rrt ;r,r',lt',1
    l() rcl)l()scnltlretlrrccstrrlcs.
    I)csip,natc
    thc lwo flip.flopstrs
    ,'1rrndlJ. Lcr lirp-l)rr1rstatsszl .- ()./J 0 corrcsglld to nctwork$ntc Ss;,{ : 0,
    *
    B = I correspontl to,S,.;rndA = l,/l = 0corrtspondtonelworkstatcSr.Each
    network state rs th!rr reprcsented by a uniquecombinationof flip0op statcs.
    Substituting the llri'.flopstatesfor.l,,, S, and S, in thc statetrblc yieldsthe

    T able14 -2
    C
    "l)
    sin |-, ! r- \ : J
    late :t) trl 00
    tl l 00
    Iabl€ig. ,: 0l
    ncs
    .rt
    Frcr:r
    for t hc

    \X (l
    A8\

    {t } 0 0

    0l 0 0

    X il x
    n
    rl
    cn
    U ll) 0
    U
    /1 ' - ,\"Ji 7.= X A
    :es
    ph 'l
    l tt' l l rp -l l o 1 ri ttl l rti si u ('l l tr' r) rl eri reri l rtr111 111..'ncxl \tl l tc l nl rpstrsi ngl hc sl rnrt:
    ls tn c l l i o tl l l l l rl rr' ,rr l ,,rl l ,l (,)r,rl l (' r., i l i ur,' l r,,ril )t)J l l l ) l l i gl -l l ol l sl trc usc(1,
    nt D ^ : A ' : .t* l J a rrtl 1 ),, l l ' . .r. + hi ch l c;rtl s[o t]rc netw ork show n i n Fi g.
    re l 4 5 . l n rtta l l ), \!c \\i i l re - rt l rotl i l l rt-r-l l trJrs 1u l l tc /cro sl at0 B y traci ng si gnal s
    th rtrtrg hth c t' tc t' ,v o rl )' . ()i r, i n) r' r' l i i t' l i trrl l ur ()tl l pul /. = | w i l l occur w hcl t l rn
    or i n l l trl s c tl ttt' rttt' r' tt,l ttt,, ttt l 1 )l occttts. Io l tvrti tl rel rrl trrlfii rl sc6utputs,i tl w aysl el rtl
    ro Ih c v :tl ttco f' Z ;r{ ' tc itl rr: i n I ut l rl rs' -' l l rrrft:dl rrri j bcft' rrcthe cl ci ck pul se.
    362 urm t4

    ('lg L

    Frgurel4-
    Moore Sta
    Fg ure l4-5

    ls similart0
    The proccdurcfor finJingttlc slrle grirphfof a Moore nl:rchtne
    that usei for a.Mealy machincexceptthal the ou put ls writtenwrth the state
    slatcs Wc will reworkthe irrcviouser'
    insteadof with thc tritnsitit)nl)elweerr
    ample as a fv{oorcm;tcIinc to ilittstrittclhe nroecdure.'Ihenetworkshouid
    tt:curred
    p ro d u c e a n o u l p t)t r.rl i 1 } nl f i l l rn i rtpr:t 5i :(l Ll cncfcndi ng i n l { \l hi rs
    cri l l rnl tchi rreup thrt;ugi i l he poi nt w hcre
    T h e d c s i g r:i s s i n trl a r' l c rth a l i or ti rc l r' 1
    w i tl i
    th e i n p u t s e q u e n c (1l 0 h ;rs gccurreri c\ccpt that 0 output i s associ atcd
    s ta te sSo , S , a n d 5 ' r:

    ,,eG)--q
    l"
    O
    musl
    N o w , w h c n u t i n p trt ()c crl rsto c:ottti rl cl cthc l 0l scqucl l cc,the output
    a new S l ate
    b e c o me l ; th e re fo rc ,w e c a n not go back l i ; state S , and must crcate
    5 3 w i th a l o u tp u t: Tablel4*z

    We now completethegiaphas shownIn I;';9.l4-6. Note t:tesequence 100rescts


    the networkto So A sequence l0l0 takesthe network back to S, sinceanother
    I input shouldcattscZ t o b c c o n t c I l t i ', ; t t r t
    ___5
    pgR|l'ATtON
    0]'ilul_q&lr,ils ,,r\t)| \ril,rjs 363

    figure1a-6
    lfoo.eStateG.apt,:._

    Thu .:., r)('t\,()rlis givcnby Tablc l4-3. Notc


    tha I li. . - - I .c r;,. .)tliprrits detcrntiitcd
    by tir:
    n_,..
    . ., - ' '.
    ..
    l . c [ ] i . r . r n t i r r r c x a , n p l e t h e ] {O O r c
    .ri;.riI ntachrne which detects the same
    I .-....:
    rr')put
    gure l4-
    bore Sta'
    Tablet4-3

    l :rnt

    ar
    rJ

    _t
    ;
    bie 1 4 -

    Si n c c ti ,i rc .-: :--.,:r re\j * :i ed to real i zethe netw ork.


    Us i n g th e Sti l l e ;S .' i 3:01 forS ,, ,B : i l forS r,and
    A B : l } i e rS.' - ..r: ' r rhe r)rp-fl opsresul ts(Tabl e 1.1_4):

    Table14-4

    *e 14-t

    The outpurfunc(i.. $ z :,rlJ'. Nt-rrerh,rt/. riepends


    only on theflip-flopsrates
    and is independenr of .x, whirefor rherc.rrespondingMialy machine, z wasa
    functionof x Deriv.ticnoi rhe flip-flopinpurcquarions
    is irraightforwardand
    will not bc givenhcrc.

    d
    II

    364 tjNil' t.t

    tr4.',e
    More (lornplex Ilesign Problenrs
    r . \ f sor nce
    i. -: \ ign! 'd a!
    lrr tlrissccli.,tttvcrVill,lt:tive;r sl:rlt'plr:rplt : : : ; , lt seque
    firr:t sct;ttcttti;tl
    nctwrtrktrf s.mcwhirl
    conrIlt.rrivllt;rrr1.lre : r l em pt ing
    Srcrttcr r)l!.\.1(,usc.tlrruplrs..l.lrc
    trclrlorl to b*dcslgncd
    hasthc fornr aguirr r l \ cquencc
    'h,rw'riirr [iig. r-r r.-fl,erutput Z shourdbc l if theinput scquence : r t cnt . We r
    cndsin cithcrillil ,r r(x)r,;tnd /. sh,rrrrrt bc 0 orhe^vire.Bcforcartemptingr. t rD' i^4.
    r lr r r ir t lr r ' r r ' r ' r . lit lr ' , " * i i l , , , . r i . i , r r i . , {}r n L r, v p t c ; t r I'' ree'

    urptrr-r)urr)u[ \dqucncc\ l(;


    t t t ii\ i. lt r t ir , . , . i ir : t , , ! . : i Ll i . . . t i r : r , l i . t . i . 1 r r r l r i l l lo l
    t l t e J l r , , b l c t t r . , i i t t e l u u t i t . Wc , , r i l
    t ic t c ilr r r r r c I lr r
    ' lr ". r r , . ' , !r ir ir pi i l . ( . ( i r i ( . n (r . l i r r t l l c l i r l t o w i t t l l i n p t t t s r , q r r c r t c c : i , J u rr' I,

    \-ortI{ij(rrr I 0 0 t CI 0 t |, 0I
    .1 I
    I
    + +
    I I
    uh ( _.:r,.elooki
    e f
    /.,00 0I 0 |0 I |0 0 0II o I 0 0 I .,1JsoZ=
    At point n, lhf irrlltltsc(lucttcc a :rnentdo
    crrtJ::
    irr t)10,onc <lfthc scc;uencr::i
    we are looLrrrg ..'. At poi
    for, scrthe .ufJruris 1, l. At pr.ri'rrr, thc input
    -. agai'cnds in 010 so 2,, L .: ._rI outp
    Note thilt ()\'sri'rppnE scqucnccs urc rilowcd rina t-h,,problcmsraremcntdo*
    not say anythingabout resertrrrg the networkwhen a t output occurs.At poinr r scquenc
    c, the input scqucnce endsin r00r, so Z is againt. why ao we havea r ourpur -: and Stat
    at pointsd, a, andf? ', 'r start o
    we will srarrconsrrucrion of rhcsraregraphby workingwith therwosequenecs s \\'hgn.tt
    which lead to a I outpur.'fhcrr we will lutcr add addirional : ar Weaf t
    arrowsand starcs
    as rcquircdto nrakesure that the output is correctfor othcr
    cases.Wc start off i: r r-eceive
    with a rescrstateso which corrcspondsto havingreceivedno , : rlput
    inpurs.whenevcr f or
    an input is rcccivcdwhich corrcspon<Js to part of onc of the s€quences we arc . , : cQ U€t lC
    looking[or, the networkshouldgo to a new statelo ..rcmembcr-
    havingreceivcd l: , g in 010.
    this input. Figure l4-7 showsa partial stategraph which gives,a , : . r r r ling
    r ourput lor in
    the sequcncc010. In rhis graph s, corrcspondsto havingieceivedu ,.q,,,,n,.. \ \ c CAngO
    cndirrgirr 0,.t,, ro il sequcnccc,ding in 0r, an<Js, to a rqu"nr. cndingin Ortr | \ e{luence
    Now, if a I input is receivedin statesr, we again have a scqu€oce
    endingin i /o11{ p111.
    01, which is parr of the inpur sequencewe are looking for. Tbcicfor. ,".
    ."igo
    backto starcs, (arrowc) sinces, corrcsponds ro hivingrceived *qu.oi,
    ending in 01,'l'lrcnif wegctanother
    0 in statcs1,w0go io s3 wirha" I outpur.
    Thisis correcr sincethesequenceagainendsin OtO.
    ll3j: scquence
    roccvcd
    So rcrct
    5r0
    sr 0t
    sr 010

    |-_-o--,-'
    (/;*-
    Figure14-7 Ll Fgun l4-9
    r

    tllltrllirl strU | (;i l \t,l ts-l \tr


    'oi _!lt
    r\1i l ,t.:s 3{; il

    I xqlgrlrr i|ll5ln
    sa rc$at
    -tr 0
    .s. 0l
    r.l I somcwhar tll0 or I()
    .:,..igncd I
    again t. 100
    :'::,,t sequence
    'i
    : :r:tcmptjng tr. --
    tO l \ '': , '\
    ll rt ' Q U C D C C S rrdl 1'
    '/Y
    l0
    c: lrnt. We will l --'

    l, ?' ice: Fiqure

    Ncxt r'c uill c.rrsrructthc pirrt o[ trrcgraprrcorrcsponding


    to thc sequence
    lfi)1. Ag'in w'c.strrrtin rlc rcsctstatcs,,,and whcnwc rcceive a I input,we go
    t. so (Fig. l4 8,,rrow b) t'rcmcmbcr thrt wc havereccivcd
    the first I in thc
    scqucnce 100l. Thc nextinnut in the scqrrcncc is 0, and shcn thi-s0 is rcceil,cd
    ,_..r,-elookjng
    shouldask thc questior:Should\\,ccreareil ne\\.staie
    )ilso Z*1. .we to coir.cspond to l
    sequence cndingir; 10,ur ciiil \r'cgo to one o[ thc previousstates
    a :rnent does on the state
    graph?sincc.5,corresponds to a sequence endrngin 10,ne can go io s, (arrorv
    :'-'. At point
    c).The lact that rvc dirin'rhavean initial0 rhis time doe.s
    ,: e I output not rnarrersincel0
    startsoff the sequence wc are rookingfor. If we get a 0 input when in sr,
    the
    input sequcnce received wiil cnd in r00 regardlcss
    r ,scquences of ttrepaitrwe took to get to
    s.' Sincethercis no srateso far corresponoing ro the sequence
    rs and states 100.\\,ecreatea
    nervs,.iteS, to in<Jiclrtc huvinqreceivetl a sequence endingili 100
    Uc start off
    If rvcgcta I inpur*'henin sr;r{cs,, th;scompretcs thesequence
    5 \\:hgngyst r("ilrandgives
    a I otrtputas irrdicutccl by urrorvc. Ag:rinwi: trskthc qucslion,can \\,cgo
    ir ra5we are back
    lo onc of the prcviousstt\t(.\. or tlo wc iraYcto createa newstate.Sinccthe end
    Ir c rcceived
    of thc sequcncc r&)1 is 0t, and s, corresponds to a sequence
    .)ulputfor endingin 01, we
    cirngo back r. st (Fig. l4 g). rt wc gcr'nothcr
    ir s uQ L l € f l C € 00r, wc haveagaincompretecr
    tlrcsuqrrcncc l00l lrndgcI irrtrlthcrloutout
    l; ,g in 010.
    Wc havcnow t;rkcncarcr,f pu(tingorrt:r I rvheneither
    : .:rrrling
    in tic sequcnce 010or
    liX)l is eomplctccl. Ncrt. rvt,rrillgo blck ;rnrlc()mDlerc
    \{c can gc) the stategr.rphto take
    ' r s c if UC l l C C
    t / orr1 p 1 1 1 . \rlt-c sgyfTg:4rl
    So rcsct
    S r0
    sl 0l
    .f, 010or l 0
    tl
    .,a I

    J. I (i .)

    F r q r r r f 1 ,1 .- lr

    l 4- 9

    -
    306 |r\-l't'I I
    Jlf',"'"tod lro
    r.c:tre in .t
    ca r c of t lic ot hc r S- ' t iile t e i : r r ', l l t i i r . r c i t a v e n 't a l r c a d y
    o S,, we ha
    accountcd fof. In r( sequenc
    Sl at e. \ r , , \ c haiu rcrl foi .r I rrrl;1.,bLrt not a 0 rnput. lf
    wc are irr S, and
    ge t ll l) lnpui, t ( ) : :;h.rl ri ,j!\U !.rr: l l ' I 0 i nput occursi n S (arrow
    , nc have a ft
    se LUUnCCCt ) dlr l. : .: (- X r.'
    -i n,' l g irr t),and
    i ).i i t tr! ci ther of the i nput s,:qucn(csfor
    wht eir ilc t r c 1, , , , , Il ;i l |i ,r. l l ,.,.ri r;i () i tn(l sti t.). i n .S , c () i,1prl1 ca
    {l rrror, / ) N ,,
    Il l l lll( ' t li,r r r lil;|, ) ( ,( i ,' 1,, tr |\ !' i .t :,crj U en!.c e trtl i ttg tn (). Js rrr I l. Sir
    g.
    Sta) ' t n. l , r lr r t r l "1;i i l il statewhi
    I .' !rir\r t:rkcnclrreof thc 0 inJ,p1 gx.ra,
    btr t nc ' l t lt r : I r r r ; : , r Lil\ r , ll . t I r : r , a , . a i , , . , i
    . ilic lnput sequcncc . J()rresllon
    cnd.srn I l. Since
    I I is r r , ll l- r ir r (, ; i i. r r lr , . : r ir . , i. ( ltt r . j . . , , r r . , :
    'r l r X ) 1 . \ r , , . r l l r ) ( ) l l t e c ( l : l s t a t a , . v h i c h
    nds to havi
    C () ll,.t5l) \r n.j. i,, , ,ltl,' l 'l s . . r ', r r r 5 , r i r t c c . \ .
    f :9lr r, ' orrcspond
    r r r iltt, . : i l r r . _ 's i r , r n d ,
    t() ,J \( :illlcn!c r .j, :,r [1 lti i] I lfCl . t,,r',
    . ,, :'i, ,, .\u.r:t,,-i,
    .,,rr..-llr,,;,,ir',,,'
    ii ,r,'.j ., -\. lhe inp
    Itc c t ir ' t i il \ ( ' ( lu( il\ r . t . t t r llir i, r , t I t , r l ( r \ r , .,rr..)\yA) s:;r
    t l i . \ , r l t r . . r t l i l r ; t s ; t r r r r w , sa , , r r a r 1 r , r , , a l , r , !
    (O 0; r r r t i I \ { } \ ! e J \ i' . t i r r . \ " t *. t 8el I (
    tic.t. ll lr I rs reeurvCdin 54, th. Input l', u, "
    ' t Pr r i\ ,
    sequencc crd:; tr: ii. Wc rJri st,ryrrr.!o ;rnd lgnorethc cxtra I (arrow,Jr) ''t t lr J00
    sincc ,,) '
    I I is rrlt part ()' cirhcrscquc'ccror whrih we arc looking.In ,''. , , , lt ot cendin
    sr, if we gst s 0 "' lr ; r saf f ows
    input,thc scqur.n(:.: ettds.tt(itX).Srrrrr:
    LX,xl
    is rrr:tcontainccj
    in eithcr0t0,rr 1001,
    we c :l n g o l r;re kl i r ' \, r1 1 1 ' '.' ,r,r, r:' .,1r,r11.r. tri i r.rvi rrgreccj vcrJi i scqri cl cccrl {rng fc lrasftXn4
    ir '' sur c
    in rl l i e (o l trt,rrel t,: I' i l ri rr()n i l )l cl r'ti\ rc , l :ri r:grapl r si rrccrvury t hat a
    sLi ttehas :rrrow r
    lc a Yi rrgi l x ' l ri c i rrro i l u \[)(]n (ll 0 l ri l ti r () rrrrrji l l )puts.W c sl roul tl '"' ir j : hal a I
    now g,0b.rcl und !i" :l,

    c hc c k th c s ti l i c !,ri tl )h i l u rl r):;ttlrc,rr' i gi l l ri !n[]ut se{ i uenccsl o make surr i hat


    a . rl l (l
    r ',.ril1One
    I o u tp u t i s a i w a y s o b ta i n c d rb r a scquerrecendi ng i n 010 br l 00l and rhat a I t r s r r xr
    out p u t d o c s n o t o c .r' u rfo r a rl y ol l ;er suct of lt
    i r:l l cc.
    N c x t w c w i l l d eri v c th c s tl te graph for a r\' l oorcscqucnti alnetw (l rk ri i th
    4 rypica
    onc U5,
    inp u t x a n ti o n e u u tp u r 7 -.' l ' h e outpur / i s r.r bc I i f the toral numbcr of
    I' s
    r ec e l l ' c di s o d d i rrr(ii ,I l c rts {tw t..r,r()nsuci rl i t]' ves havc becn rcC C i V ed. A tV pi C al ^ r i r.
    inp u t.U td rru tp rrtrt.tl ttc n rci : :,1f l

    .\., i0ll00tt \ { il I

    i 1 lll (i)[]:

    u b cde ir \lgesg
    z:t}) 0 0 0 0 0 I 0 | I t r cr nl s 6r y,
    , 'eecr t t dwit h
    we huvc shifted rhc Z scqu*ncero the right to cmphasizcthat for a Moorc
    *c r cr , lf l'. s
    r,etworkan input changedoesnot affec't z immediatety,bulz can chsngeonl, . . _ c r , Ulpul
    afterthe next clockpulse.'fhc initiul 0 in p.rrenllreses
    is lhe outputassociated wirb rcCs. . hiye
    the resetslatc.At points d ald b in thc aboveseguenft,an odd numbcrof l!
    has bsenreceived, Lrut[wo consecutive 0's havenot beenrcccived,so the output
    r3set
    rcmuins0. At poinrr,c and r, ln odtl nulribcrof I's and two consecutive 0'shavc ' '.'ler
    '
    beenrer:eivccl,so 7.= L At pi,rintI, z '. ii becaus,g th* numberof I's is rvel.
    \vt st;rrt':onsirucliorrr,.frhc r1,.rorIsi..r.,)
    graphiFig. la-10) with th,: reset
    s t atr.:5 ,,, l i ti ti rv ,.:l :,s r.,C i ;rli cr 0 (-),.tti -i 1l i ,,' i ; i i rj " r S !;ttr. Fi rS t. W e V ttl l C OnS i dgf
    k ecp ri i gtrl tc l i o l ' x ' i rr;tl .tcir.
    i rc i l L ri l i i rt:ir! i " . ;r i .vri rto!' $rJrj ,l l R ' cgct u I i npuf i n
    56, w r: w tl l g o i o rl ;ttr.:.' i , l t, ti i tl i crtl i :urr ri l i rl ;nrl rrbsruf I' s rccui vcrj .' l ' hcoul put

    Ii,cscl
    '' -1 l l l Ooui s
    E.vrir i
    Fig ure14 -10 Fk3ure14- 12
    _f
    t
    _---.--- I

    )
    r_-..------ DfiRryATloN ,I
    ' oF sTArlLcR^rtr.s ,rABr,ES I

    aNp
    ll f* 'rr,1 1 . 6 f or . f n 3 67
    )c lre in J,
    and
    n ,tr, we have :!19 rgrrrs rqived
    a
    t( sequences So rcsctor ecn I,r
    for
    (rtrrow,f). Jr odd I's
    ..lo Sr cvcrr l.c rnd 0
    rg rrrt), and
    we Sl cvcn l,s and 00
    c () r,rpulcasc, S{ 00 and odd I's
    ctsirr ll. Sine
    statewhich
    ,,1 fQure
    I -orfCstr,Onds
    ncl.sto having
    for S, is 0 sinccI
    'lrr.rpondjng filo conscculilc0's

    ";iilT
    reccrved, ha' no{ b€cnrcceived'
    sh.u*J
    , J., the inpur unnccc.s.sary,o,,,ll-u,t
    lcr.t rr.r ,,,,;.','tt *l:n,,second I is
    , .. rr()\yA) s:acc
    u,.r,'t
    , r, ,
    t*t gct a o
    t"(' tl r lool' il,:; t+it$:jtil:,j,iil;:r
    rfl{i:k*:i1#iii,
    e n ding
    ! , , ,,Jc'tl ce
    '"'i gotos,"10'offj;1,' i,.]:,,,1,1,,,.
    h ;rsa f r ows
    go b6sft and c On s e c u ti v e
    0 ,Sre c The
    i:il;.l,'H,:l::;,.;:;.,.,,:,;;.,y;l;,:",;;
    ccive<J;";;,*.,:rved o . rp rr is s rrlt . ,i; r
    , , ' . , ; ; ; . ; " , ; : l, u ru . , . , f
    . su rc that a lJ lvc8ct;r I input, .s
    I h at go we ft,11,g rer"iuJ un'",, nurnl.,cr re -
    :,,,1"u a I lld
    osan',r.;;j
    'ts..'r*i.l
    ;,:li,;.:J,,:,1:,*1,,,;l,j,Jl,';,,i;,1; ;;;;;';;.:l; of l,s
    ,-lur.receii.c
    ,woco;rsecurjve
    :l:"ti one ;i I in .5o, ,,,,r;,:,;
    t r \ h t t t',,irh
    r
    t. A typiul
    of I's
    rn. ,.s , s o \ t e c an

    ;;;,i* :il:ll
    iI :
    1;. r,:,
    ri j
    r c { Ua

    i:: ;:
    ,,
    :,ri:Ifil,.";::,
    ,l;""
    iir
    il:
    "rl
    t) s.
    c^
    nnoeo
    tos,,,,
    ;;i::,':
    il::lll *."J: i
    itn()
    cttrrcsPrrr)tls
    t, rrr,,,ltl ,r,rrrl,ci,,,",
    ,,,,r1 lt':':.t.
    # :i,"fi::.ff J.ru;',n'
    (Fig. l4 12,
    arro*,/,,, hich
    i '(i rrsccti l r\c 0 'sa rd ru ..,,,, ;y0. ' ,,;;;
    , lliilt' t"tl11Ar r .{ hcr
    0 r csu1s,,,

    tlr \loorc
    )::::ii;ti:lri"txtrilli:#,i
    ,,,,
    tti " i v t' ti ;rrr
    ;iqru;';jT f,,"' ,,,,ri,,ir
    :;;r1,,..,,,,,,,
    rrrrr,l ,t.r ,i i r" ;;;;,:' ' i ;: Jr, a I i npur
    means rhal * e
    l lrerl n l s 6 n1, r+ ' cmu s I re ttrrn ' rtrl ,j ,"t' ' ' l l .l r(' (ri v(' (l have
    l o .\.. t" i l w { } col l ' \ccl l l i i c
    ierri tl j q ri 1f i r+ e re c c i re a ,.,,,r," ,' 1' r;.
    *c f tcr ,rf l i recc
    rc,,, " s,:, I i n ,!.. .f:l "t' ' u
    o;n,Ii,,i.Ii,.n.l);,*i;i
    )jjl,ljHJfTj1yri,i,i
    " ' ,.i

    _ , .ts,,Utp U l
    r cC uti 0 'i h tt'e
    :
    j
    ! I^r.att_ r::': -lls!s$nr*
    l.1r rCSCI re\c( of cvCn I'S
    :,
    c,rrsider .) , o<IdI's
    r;trut in cveoI's rud 0
    :,
    Jr pvcnl,c rud 00
    : c:t(pul
    odd r! and00
    :1.
    ir o<JdI'c and0

    tigure14-12
    Ev en l' s

    i
    L
    r
    T
    L
    814 A P P ENDIX A VHDL Rnrnnsxcr

    LIBRARY ieee ;
    USE ieee.stdlogic-l I 64.all ;
    USE ieee.std-logic-unsigned.all;

    ENTITY count4IS
    PORT(Resetn : IN STD_LOGIC;
    E, Clock : IN S TD _LOGIC ;
    a :OU TSTD_LOGTC_YECTOR(3 DOWNTO 0) ) ;
    END count4;

    ARCHITECTURE Behavior OF count4IS


    SIGNAL Count: STD-LOGIC-VECTOR (3 DOWNTO 0) ;
    BEGIN
    PROCESS( Clock, Resetn)
    BEGIN
    iF'Resetn: '0' THEbi
    Count <: "0000- i
    ELSIF (Clock'EVENT AND Clock: '1') TTIEN
    IF E :' l ' T I{ E N
    Count <: Count* I ;
    E N D IF ;
    E N D IF ;
    ENDPROCESS;
    Q <: Count;
    END Behavior ;
    FigureA.

    FigureA.40 An exompleof o counfer.

    register. The register has an asynchronousreset input" Resetn. It also has an enable input, representsthe ,
    E, which is controlled by a four-bit counter. The counter has an asynchronousclear input on the register
    and a count enable input. The circuit operatesby first clearing all bits in the register and The staten
    counter to 0. Then in each clock cycle, the counter is incremented, and the sum ouq)uts keywords are r
    from the addenare stored in the register. When the counter reaches the value 1111, the (n :> k) sets
    enable inputs on both the register and counter are set to 0 by the NAND gate. Hence the the adder,but i
    circuit remainsin this stateuntil it is reset again. The final vziluestored in the registeris the code,is use
    equalto l5X. a constantvalu
    We can represent the accumulator circuit using several subcircuits described in this defined for thi_.
    appendix: addern (Figure A.15), NANDz (Figure A.28\, regne, and count4. We piaced register, which
    the component declaration statementsfor all of these subcircuits in one package, named carry-out, whic
    components,which is shown in Figure A.42. The regne
    Completecodefor tlte accumulatoris givenin FigureA.43. It usesthegenericparameter usedto setthe r
    .i
    t to representthe number of bits in the input X. Using this parameterin the code makes it Sarnoutput fror
    i
    easyto changethe bit-width at a later time if desired. The architecturedefinesthe signal Surz output of the ac
    to representthe outputsof the adder;for simplicity, we ignore the possibility of arithmetic is required in tt
    overflow and assumethat the sum can be representedusing /c bits. The four-bit signal C component.
    ?:'l
    F.,
    sii.

    l .'0 S S et
    ":rrtrc.,,,r,..
    f:,
    "
    t l.lBRAIt-r-iree ;
    .,
    USE ieee.std_logic_l
    l64.all ; $.'.
    F:
    3 ENTITY shifi4IS
    4 PORT( w. Clock : iN ST}-I.OG]C:
    Cr : 0i; i' sl;)_' i-ilic-vE{,t'ii.lj.ii 1 -i{} _l)
    ; E),il] shill ! :

    {t
    7 ARCHITECTURE Behavior oF Shjft4iS F"
    g
    a B EGIN F
    o
    PROCESS( Clock )
    t0 VARIABLE Sreg : STD_LOGIC_VTCTOR(
    v
    I

    1 TO4); t:
    lt BECIN F
    a?
    1: iF Clocli'EVE\*TAliD Clock: ,1, THEN !_

    I3 Sre_s(-l) :: rv ;
    Sreg13):: Sre-e(4) ;
    15 S re g (2 ):: Sreg,3);
    to S re g (l ):: Sreg(2);
    tl END IF:
    t8 Q <: Sre-q;
    i9 END PROCESS;
    20 END Behavior;

    FigureA.39 Jhecodefrom FigureA.3g, usingo vorioble.

    ent
    ip- A.10.8 CounsrnRs
    ite
    FigureA.40 showsihe codefor a four-bit counter
    with an asynchronous resetinput. The
    .As counteralso has an enabreinput. on the positive
    crock edge,ir rhe e'aL,r*d is r. rhe
    tm count is incrernented.If g : 0, the counteih.ids its cuffentvalue.
    coirlmoniyneededin logic circuits"mostcAD B..uur. countersare
    in systemsprr:videa selectionof counters
    can be instantiated
    in a desien. that
    :es
    )9,
    t6
    ifr A'10.9 usrxc suncrncurrswrrrr GENER{CpaReurreRs
    \1'ehaveshownseveralexamplesof VHDL
    )\ entitiesthat include
    thesesubcircuitsare usedas componentsi'other ltr:lmeters. When
    -gei-rei:,:
    code, the genericparameterscan bc
    nt set to whateverva-ruesare needed.To give an exampreof corJponent
    ot generics,considerthe circuit shownin instantiationusing
    Rgure A.41. The circuit ,oo" J"-uinury
    td representedby thefr-bitinputx to itselfa numberoftiines. number
    Sucha circuit is often called
    an accuntulator'To storethe resultof each
    additionoperation.thecir-cuirinefr1fls5
    a ft-si1
    A P PENDIX A VHDL Rrrnnexcr

    I LIBRARY ieee ; I
    Z USE ieee.stdlogic-l164.all; 2

    J ENTITY Shift4IS 3
    4 PORT ( w, Clock : IN STD_LOGIC; 4
    5 a : OUT STD_LOGIC_VECTOR(1TO 4) ) ; 5
    6 END shift4; 6

    l ARCHffECTURE Behavior OF shift4IS 1


    8 SIGNAL Sreg : STD_LOGIC_VECTOR(ITO 4) ; 8
    9 BEGTN 9
    10 PROCESS( Clock ) 10
    ll BEGIN 11
    t2 IF Clock'EVENT AND Clock: '1, TIIEN
    . { .t ?
    i1.-:! rc
    Sreg(4)<: w; i;
    Sreg(3) <: Sreg(4); , t4
    15 Sreg(2)<: Sreg(3); 15
    t6 Sreg(l) <: Sreg(2); l6
    t7 EN D IF ; l7
    18 END PROCESS; l8
    l9 Q < : S re g ; 19
    20 END Behavior; 20 1

    A.SA Codefor o bur-bil shifrregisrer. Figure


    ;l{*

    statementsin fines 13 to Henceall flip- 4.10.8 Cr


    flops changetheir at the same time, as required in the shift register. We could write
    the statementsin lines 13 to 16 in any order without changingthe meaningof the code. FigureA.40 st
    In sectionA.9.7 we introducedvariablesand showedhow they differ from signals.As counteralso h
    anotherexampleof the semanticsinvolved usingvariables,FigureA.3g gives the codefrom count is incren
    Figure A;38 but with Sreg declaredas a variable,insteadof is a signal. The statementin commonly nee
    line 13 assignsthe value of rryto Sreg(!). Since Sreg-j can be instantir
    gffectrrrursuidltrry.
    _L'Lrr immediately.In rine r+
    ril true 14the
    tne value
    value or sr"g (ZfrffihGffidy
    of Jreg (4), wrucn nas aready be--
    been changed to lf.
    is assignEdTo'TrQ(3).Henceline 14 resultsin Sreg(3): w. Simiiarly,lines 15 and 16
    set ^Sreg(2) and Sreg(l) to the value of ry. The code doesnot describethe desiredshifi A.10.9 U s
    regis.lgr,but ratherloads all fli with the val
    Fo1the codein Figure$Jp_1o_.-c..g the ordering of lines We have showl
    l3 to 16hasto bereversed.ThenthenritiiiignmenGersffit6 to thevalueof sreg(z), thesesubcircui
    the secondsetssreg (2) to the value of sreg (3), and so on, Each successiveassignment set to whatevel
    is not affectedbv the one that precedesit; hencethe semanticsofusing variablesdoesnot generics,consi
    causea problem. As we said in sectionA.9.7, it can be confusingto use bottr signalsand representedby
    variablesat the sametime becausethey imply different semantics. an accumulcitot
    A. !+ !gr_ri'g1'pl.r,1_lli*rc:-'t rs il'! 'r

    LlilRAR'i ie*e :
    USE ieee.stdiogic-116-1.aII
    :

    ENTITY regneiS
    GENEIiIC { n : I\TT:CER :: -i ) :
    f'r.li{T i D : 1-\ :''i}-}.tltliC,\r--:.-i-tl,ii:i- i i .r n )' ail il ,
    li':.etii : lN STii-L.OGii ; r: :'

    ff
    E. Clock : i]{ STD,LOGIC ;
    a : OUT STD LOGIC-VECI'OR(n-1 DO\\iNTO 0) ):
    END regne:
    l:r.
    ARCI{ITECTUREBehaviorOF regneIS E.:'i
    ffi*
    BEGIN
    PF.OCESS ( Resetn.Clock ) ffi
    BECI}J
    IF R.esetn: '0' THEN
    Q < : (O T H ER S:> ' 0' );
    #
    : sri

    ELSIF Clc,ck'EVENTAND Clock : '1' THEN


    IF E: ' 1 ' T H E N *t
    Q < :D ;
    END IF;
    ffi
    END IF;
    END FROCESS;
    END Behavior;

    FigureA.37 with cJnenobleinput.


    VHDLcodefor on u-bitregister

    change their stored values if the enableE is 0. If f :


    clock edge in the normal wa_v.
    I. the register responds to the active

    ff
    ff
    A.10.7 SnrrrRncrs"rBRs
    An exampleof crxlethatdefinesa tbur-bitshift registeris .shownin FigureA.-18.The lines
    of code are numbrredtor easeof reference.The shift registerhasii seririiinput, u,. and
    paralleloutputs,Q. The right-mostbit in the registeris Q(4). andthe left-mostbit is Qi I jr' iffi
    shiftingis perfornred in theright-to-leftdirection.The architecture declaresthesignalSreg, ,ffi
    which is usedto describethe shift operation.All assignnrents
    the clock edgeby the IF condition;henceSregrepresents
    to,tres are svnchronizedto
    the outputsof flip-flops. The
    iffi
    statementin line 13 specifiestrratSreg(4)is assignedthe valueof rt. -As weg1plailgd.
    preliog{y*{is as;+ign_ment doesnot take effect immedia'relvbut is scheduledto occur at
    the end of theprocess.In.lin614tn" luo.nt u"i,r. nisr"jt+i. riefoieif is ihiiietl asa result
    6f li"i, i:, liiriiSti"it to Srng{3).Lines l5 and 16completetheshiftoperation.They assign
    the currentvaluesof sreg(3)lncl Sru,,{(2). hetbrctheyurechangeti as a rcslrltof lines l4
    and f -i. to Sre.q(l)andSn,,*{ FInall'v.
    ii. resgrci:tivcl-v.,. S,z,gis li:;sigrl*d
    to thr'f] o'.rtputs.
    -----:-*r_

    810 A P P ENDIX A VHDL R.nrsnpxcn

    LIBRARY ieee; LIBRARY I


    USE ieee.std-logic-1
    164.ail; USE ieee.st,

    ENTITY reg4 IS ENTITY rer


    POR T ( D : IN STD_LOGIC_VECTOR(3DOWNTO O): GENE:
    Resetn,Clock : IN STD_LOGIC: PCRT
    o ouT STD_LOGTC_VECTCR(3DO$/NTO 0) ) ;
    END reg4 ;

    ARCHITECTURE Behavior OF reg4IS END regne


    BEGIN
    PROCESS( Resetn,Clock ) ARCHITE{
    BEGIN BEGIN
    IF Resetn: '0' THEN PROCI
    Q <: "0000"; BEGIi.
    ELSIF Clock'EVENT AND Clock : '1' TIIEN li

    Q< :D ;
    END IF;
    END PROCESS;
    END Behavior;

    E
    FigureA.35 Codefor o four-bil registerwith osynchronous
    cleor.
    END F
    END Behar
    LIBRARY ieee ;
    USE ieee.stdlogic-l164.all;
    FigureA.37
    ENTITY regnIS
    GENERIC( n: INTEGER:: 4 ) :
    PORT ( D :IN STD-LOGIC-VECTOR(n-1 DOWNTOO);
    chan,eetheir store
    Resetn,Clock : IN STD_LOGIC;
    clock ed_ee
    in the
    a : OUT STD-LOGIC-VECTOR(n-l DOWNTOO));
    END regn ;

    ARCHITECTURE Behavior OF resn IS A.10.7 Ssrr


    BEGIN
    An exampleof co
    PROCESS( Resetn,Clock )
    of code are numt
    BEGNi
    paralleloutputs,(
    IF Resetn: 'O' THEN
    shifting is perforr
    Q < : (O T I{ E R S :> ' 0' ); which is usedto r
    ELSIF Clock'EVENT AND Clock : 'l' THEN
    the clock edge b.
    Q.:D : statementin line
    E N D IF ;
    previously,this a
    END PROCESS;
    the end of the pro
    END Behavior;
    6frii"*iriioi'is
    the currentvalue,
    FigureA.36 Codefor on ,r-bitregisierwilh osynchronous
    cleor. and l -5,to Srr,g(2
    w

    A.tO 5r1r-rxrr,rr-Clnr:llr!

    LIBRARY ieee;
    USE ieee.stdlogic-i164.a11
    ;
    D
    ENTITY flipflopIS
    ne PORI(D, Resetn,Clc'ck : Il{ STD [-OG]C :
    a : OU f ST-i-\L{; .:' -" :
    l:iriD Itipflcp;

    ARCHITECTURE Behavior OF flipfloplS


    BEGIN
    nc PROCESS( Resetn,Clock )
    NL BEGIN
    iF Clock'EVENT AND Clock : '1' THEN
    t,
    iF Resern: 'q' THEN
    I

    t" Q < :' 0' ;


    li. ELSE
    es. Q < :D ;
    i;
    he END IF .
    D Ei.{DIF;
    END PROCESS;
    TE END Behavior;
    le

    FigureA.33 D flip-flopwith synchronor.rs


    reset,usingon |F stotement.
    bf-'t';l:t"
    of
    LIBRARY ieee;
    USE ieee.stdlogic-ll64.all ;

    ENTITY fliptlopIS
    PORT( D, Resetn,Clock : IN STD-I-OGIC;
    a : OUT STD-LOGTC );
    END flipflop;

    ARCHITECTURE BehaviorOF fl iptlop IS


    BEGIN
    PROCESS
    BEGIN
    WAIT UNTIL CIock'EVENT AND Ciock : '1' :
    .O'
    IF Resetn: THEN
    j Q< :' 0 ' :
    ELSE
    ( Q< :D r
    'I END IF ;
    END PROCESS:
    END Behaviar:

    FigureA.34 O flip-flopwith synchronous


    resei,usingo WAITUNTILstoiement.
    \

    808 A P P E NDIX A o VHDL RersneNcr

    4.10.4 A Fr-rp-Fr-opwrrHAsvNcnnoNous Rnsnr


    Figure A.32 gives a processthat is similar to the one in Figure A.30. It describesa D
    flip-flop with an asynchronousreset,or clear, input. The resetsignal has the nameResern.
    When Resef,a: 0, the flip-flop output Q is setto 0. Appendingthe letter n to a signalname
    is a widely usedconr.entionto denotean active-lowsignal.

    A.lO.5 SvlrcunoxousRESET
    FigureA.33 showshow a flip-flop with a synchronousresetinput can be describedby using
    the IF statement.FigureA.34 presentsa specificationbasedon theWAIT IJNTIL statement.

    A.10.6 Recrsrens
    One possibleapproachfor describinga multibit registeris to createan entity that instantiates
    multiple flip-flops. A more convenientmethod is illustrated in Figure A.35. It gives the
    same code shown in Figure A.32 but using the four-bit STD-LOGIC-VECTOR input D
    and the four-bit output Q. The codedescribesa four-bit registerwith asynchronousclear.
    Figure l{..36 gives the code for an entity namedregn. It shows how the code in Figure
    A.35 can be extendedto representan n-bit register. The numberof ffip-flops is setby the
    genericparameterr?.
    The code in Figure A.37 showshow an enableinput can be addedto the n-birregister
    from Figure 4.36. When the active clock edge occurs,the flip-flops in the registercannot
    Li
    LII
    LIBRARY ieee ;
    USE ieee.stdlogic-ll64.all ; E}

    ENTITY flipfloplS
    PORT ( D, Resetn,Clock : IN STD-LOGIC; EI.
    a : OUT STD-LOGIC );
    END flipflop; AT
    BI
    ARCHITECTURE Behavior OF flipflopls
    BEGIN
    PROCESS( Resetn,Clock )
    BEGIN
    IF Resetn: 'O' THEN
    Q < :' ,O' ;
    ELSIF Clock'EVENT AND Clock: '1' TlmN
    Q < :D :
    END IF;
    END PROCESS;
    END Behavior;

    FiEureA"32 reset
    D flip-flopwith osynchronous
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