good morning all of you 1. My project is "MODULE BASED M!LEME"#A# O" O$ !A%# AL %E&O"$ 'U%A# O" " $!

'As $O% &OU"#E%S" (. n day)to)day life* most of t+e &s fa,ricated contain counter. #+ere are so many types of counter suc+ as -o+nson counter* ring counter used Depending upon circuit functionality* &ounter is main ,uilding ,loc. in $!'A also . $!'A/ $!'As are programma,le logic de0ices 1+ic+ allo1 t+e implementation of digital systems. #+ey pro0ide an array of logic cells t+at can ,e configured to perform a gi0en functionality ,y means of a configuration ,it stream. f a ne1 reconfiguration is re2uired* t+en it is necessary to stop system e3ecution and reconfigure t+e de0ice it o0er again. 4+en counter is programmed in $!'A its ta.e randomly LU#5s * due to t+is si6e of 1+ole c.t * po1er consumption timing access increses. 4+ic+ affect t+e 1+ole processing of c.t. #+at5s 1+y it5s a necessary to reduce t+e po1er consumption* ,itstream si6e. Some $!'As allo1 performing partial reconfiguration* 1+ere a reduced ,it reconfigures only a gi0en su,set of internal components. !artial reconfiguration dynamically modify +ard1are portion of t+e de0ice ,y do1nloading configuration ,it files. #+is result in increase in speed and functionality of $!'A ,ased system. And ,y using floorplanning and different met+od 1e decreses t+e po1er consumption. 7/ L #E%A#U%E %E8 E4 #+ese are t+e pre0ious paper on dynamic partial reconfiguration. #+e first paper gi0e t+e o0er0ie1 a,out t+e partial reconfiguration* and design gray counter and -o+nson counter in 1+ic+ t+e ,itstream si6e in decreses an t+at5s 1+y less space re2uired in $!'A n t+e second paper* introduce t+e implement t+e difference),ased partial reconfiguration in adder su,tracter* and up9do1n counter. #+ey found increasing speed in operation.

:/ OB-E&# 8E/ n t+e pre0ious papers* t+e ddn5t s+o1 t+e data a,out +o1 muc+ percent data si6e reduces or speed increase. And in ,ot+ paper t+e didn5t discuss a,out po1er consumption. My main o,jecti0e is to design different type of counter 1+ic+ mostly used in $!'As* reduce t+e si6e of counters using module ,ased partial reconfiguratiojn. Along 1it+ decrease t+e timing re2uired to e3ecute. And analyse all counters data after partial reconfiguration suc+ as po1er consumption* ,it ;stream si6e. </ INTRODUCTION TO PARTIAL RECONFIGURATION: !artial %econfiguration =:> is t+e modification of an operating $!'A design ,y loading a partial configuration file. ?ilin3 partial reconfiguration e3tends t+e in+erent fle3i,ility of t+e $!'A ,y allo1ing specific regions of t+e $!'A to ,e reprogrammed 1it+ ne1 functionality 1+ile applications continue to run in t+e remainder of t+e de0ice $rom t+e functionality of t+e design* partial reconfiguration can ,e di0ided into t1o groups/ dynamic partial reconfiguration @D!%A and static partial reconfiguration #+e static logic remains functioning and is completely unaffected ,y t+e loading of a partial ,it file .#+e reconfigura,le logic is replaced ,y t+e contents of t+e partial ,it file. #+e gray area of t+e $!'A ,loc. represents static logic and t+e ,loc. portion la,eled %econfig Bloc. BAC represents reconfigura,le logic As s+o1n* t+e function implemented in %econfig. Bloc. A is modified ,y do1nloading one of se0eral partial B # files* A1.,it* A(.,it* A7.,it* or A:.,it After a full ,it file configures t+e $!'A* partial B # files can ,e do1nloaded to modify reconfigura,le regions in t+e $!'A

D/ DYNAMIC PARTIAL RECONFIGURATION:

?ilin3 inc. suggests in =(> t1o ,asic styles of dynamic reconfiguration on a single $!'A/ t+e Difference),ased partial reconfiguration and t+e module),ased partial reconfiguration. Difference),ased partial reconfiguration / can ,e used 1+en a small c+ange is made to t+e design. t is especially useful in case of c+anging Loo.)Up #a,le @LU#A e2uations or dedicated memory ,loc.s content. #+e partial ,itstream contains only information a,out differences ,et1een t+e current design structure @t+at resides in t+e $!'AA and t+e ne1 content of an $!'A Module),ased partial reconfiguration/ uses modular design concepts to reconfigure large ,loc.s of logic. #+e distinct portions of t+e design to ,e reconfigured are .no1n as reconfigura,le modules !artial reconfiguration sa0es t+e silicon area ,y allo1ing multiple configurations to ,e s1apped in or out of t+e de0ice and pro0ide fle3i,ility to selecti0ely replace t+e one configuration ,y t+e ot+er. n my project am implement 0arious counters. #o implement t+is counters module ,ased partial reconfiguration style is used

E. #+e follo1ing met+odology used to design partial reconfiguration. $irstly* t+e code 1ritten in 8erilog language* and ,y using ?ilin3* generates netlist to perform partial reconfiguration in ?ilin3 !lanA+ead soft1are. F. &reate t+e project* c+ec. synta3* simulation. 'enerate t+e netlist ,y synt+esi6ing project and finally implement project. G/ PLANAHEAD SOFTWARE: #+e module),ased partial reconfigurations re2uire !lanAna+ead soft1are. #+e netlist generated ,y ?ilin3 soft1are used to recei0e information a,out project. !lanA+eadH offers an %#L to ,it stream design flo1

!lanA+ead soft1are pro0ides a compre+ensi0e coc.pit for creating and 0erifying %#L designs in eit+er 8erilog or 8IDL* !lanA+ead is integrated 1it+ SE Simulator to perform ,e+a0ioral and functional 0erification of IDL code and ! at 0arious states of t+e design !lanA+ead +as e3tensi0e capa,ilities to +elp designers ac+ie0e design closure. #+is includes a 'U 1it+ compre+ensi0e cross)pro,ing to analyi6e your designs and trac. issues suc+ as timing 0iolations and D%&s and t+en trace t+em ,ac. to sc+ematics* netlists and constraints. #+is allo1s designers to e3periment 1it+ p+ysical constraints suc+ as p,loc.s @area groupsA and location constraints for cell instances. !lanA+ead includes a fle3i,le* integrated timing analy6er allo1ing you to estimate route delays ,efore running place and route. #+is capa,ility can ,e used in 0arious modes during different stages of design completion. F/ SUMMARY Design of different types of counter is done. #+e figure s+o1n in slide is t+e simulation of -o+nson counter and ring counter. $or ac+ie0ing remaining o,jecti0e * am trying to access t+e license file partial reconfiguration using in plana+ead soft1are t+roug+ ?ilin3 nc.