COURSE OUTLINE

Course Computer Architecture (2013-2014) Code / Version EECE74100 (100) Total Hours Credits
60 4

PreRequisite(s) EECE2415 (100) Engineering Project IV

or EECE72540 (100) Engineering Project IV and EECE2000 (100) Digital Design or EECE72000 (100) Digital Design

CoRequisite(s) Course Description

This course is a study of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics include: instruction set design, processor micro-architecture and pipelining, cache and virtual memory organizations, protection and sharing, in-order and out-of-order superscalar architectures, vector supercomputers, multithreaded architectures, symmetric multiprocessors, memory models and synchronization, parallel computers, and reconfigurable systems.

Course Outcomes
Successful completion of this course will enable the student to: 1. 2. 3. 4. 5. 6. 7. 8. 9. Identify various classes of computers. Classify instruction set architectures. Apply techniques of advanced optimization of cache memory performance. Apply instruction-level parallelism techniques. Explain how thread-level parallelism improves processor performance. Analyze the performance and resource allocation of a reconfigurable realization of a microcontroller. Select an appropriate architecture for a given application. Design, build, and test an 8-bit and a 32-bit microcontroller system. Design, build, and test a 32-bit multiprocessor system.

10. Design a universal asynchronous receiver/transmitter and interface it with an 8-bit microcontroller. 11. Simulate, synthesize, map, place, route and do timing analyzes of custom computer designs using high-level CAD tools.

Unit Outcomes
Successful completion of the following units will enable the student to: 1.0 Introduction to Computer Architecture 1.1 1.2 1.3 1.4 2.0 Use Flynn taxonomy to identify classes of computers. Identify the seven dimensions of an instruction set architecture. Calculate the energy and power within a microprocessor. Analyze the trends in cost, performance (Amdahls law) and dependability of computers.

Memory Hierarchy Design 2.1 2.2 2.3 2.4 2.5 Use the proper nomenclature when describing memory hierarchy. Evaluate cache performance using hit time and miss rate. Explain the methods used for basic cache optimization. Analyze how virtual memory manages the two levels of memory hierarchy. Describe protecting and sharing processes.

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COURSE OUTLINE
Course Computer Architecture (2013-2014) Code / Version EECE74100 (100)
2.6 3.0 Describe the current memory technologies such as SRAM, DRAM, and Flash.

Instruction-Level Parallelism 3.1 3.2 3.3 3.4 Explain how pipelining increases the processor instruction throughput. Identify pipeline structural, data, and control hazards. Analyze static and dynamic branch prediction to reduce branch hazards. Describe the challenges of implementing pipelining.

4.0

Thread-Level Parallelism 4.1 4.2 4.3 4.4 4.5 Describe the basic structure of a centralized shared-memory multicore processor. Define multiprocessor cache coherence. Analyze the performance of symmetric shared-memory multiprocessors. Explain distributed shared-memory and directory-based coherence. Describe the basic concepts of synchronization mechanisms.

5.0

Reconfigurable Systems 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 Describe the basic slice resources and explain the structure of an output macrocell of an field programmable gate array (FPGA). Synthesize a microcontroller in HDL. Generate a set of instructions for a microcontroller. Optimize the performance of a microcontroller. Instantiate a digital clock manager into a microcontroller design. Design and implement a basic memory system, consisting of several memory devices, an address and a data bus, and address decoding circuitry. Synthesize a processor in HDL using specific tools. Integrate on-chip and external peripherals into a basic processor design and add an instruction set. Create Intellectual Property (IP) and add it to the design. Address peripherals using system specific software. Implement interrupt service routines using system specific software.

Required Student Resources

J. Hennessy and D. Patterson. Computer Architecture A Quantitative Approach (Fifth). Morgan Kaufmann 2012. For lab purposes the Xilinx suite will be used: Integrated Software Environment (ISE), Embedded Development Kit (EDK), Software Development Kit (EDK) Course notes

Optional Student Resources Evaluation

The minimum passing grade for this course is 60 (C). In order to successfully complete this course, the student is required to meet the following evaluation criteria: Assignments Labs 10.00 10.00

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COURSE OUTLINE
Course Computer Architecture (2013-2014) Code / Version EECE74100 (100)
Project Exams (2) 20.00 60.00 100.00 %

Other
Conestoga College is committed to providing academic accommodations for students with documented disabilities. Please contact the Accessibility Services Office.

Prepared By School Date

Alex Tugulea Engineering Technology 2013-10-15 Conestoga ITAL

2014-01-05

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18:53