Write a verilog code to swap contents of two registers with and without a temporary register?

With temp reg ; always @ (posedge clock) begin temp=b; b=a; a=temp; end Without temp reg; always @ (posedge clock) begin a <= b; b <= a; end Difference between blocking and non-blocking?(Verilog interview questions that is most commonly asked) he Verilog language has two !orms o! the procedural assignment statement" blocking and non#blocking$ he two are distinguished by the = and <= assignment operators$ he blocking assignment statement (= operator) acts much like in traditional programming languages$ he whole statement is done be!ore control passes on to the ne%t statement$ he non#blocking (<= operator) evaluates all the right#hand sides !or the current time unit and assigns the le!t#hand sides at the end o! the time unit$ &or e%ample' the !ollowing Verilog program (( testing blocking and non#blocking assignment module blocking; reg )*"+, -' .; initial begin" init/ - = 0; 1/ - = - 2 /; (( blocking procedural assignment . = - 2 /;

3display(4.locking" -= 5b .= 5b4' -' . ); - = 0; 1/ - <= - 2 /; (( non#blocking procedural assignment . <= - 2 /; 1/ 3display(46on#blocking" -= 5b .= 5b4' -' . ); end endmodule produces the !ollowing output" .locking" -= *****/** .= *****/*/ 6on#blocking" -= *****/** .= *****/** he e!!ect is !or all the non#blocking assignments to use the old values o! the variables at the beginning o! the current time unit and to assign the registers new values at the end o! the current time unit$ his re!lects how register trans!ers occur in some hardware systems$ blocking procedural assignment is used !or combinational logic and non#blocking procedural assignment !or sequential Tell me about verilog file I/O? 7896 - &:;9 integer !ile; !ile = 3!openr(4!ilename4); !ile = 3!openw(4!ilename4); !ile = 3!opena(4!ilename4); he !unction 3!openr opens an e%isting !ile !or reading$ 3!openw opens a new !ile !or writing' and 3!opena opens a new !ile !or writing where any data will be appended to the end o! the !ile$ he !ile name can be either a quoted string or a reg holding the !ile name$ :! the !ile was success!ully opened' it returns an integer containing the !ile number (/$$<-=>&:;9?) or 6@;; (*) i! there was an error$ 6ote that these !unctions are not the same as the built#in system !unction 3!open which opens a !ile !or writing by 3!display$ he !iles are opened in A with BrbB' BwbB' and BabB which allows reading and writing binary data on the 8A$ he BbB is ignored on @ni%$ A;7?9 - &:;9 integer !ile' r;

r = 3!closer(!ile); r = 3!closew(!ile); he !unction 3!closer closes a !ile !or input$ 3!closew closes a !ile !or output$ :t returns 97& i! there was an error' otherwise *$ 6ote that these are not the same as 3!close which closes !iles !or writing$ ! Difference between task and function?

&unction" - !unction is unable to enable a task however !unctions can enable other !unctions$ - !unction will carry out its required duty in Cero simulation time$ ( he program time will not be incremented during the !unction routine) Within a !unction' no event' delay or timing control statements are permitted :n the invocation o! a !unction their must be at least one argument to be passed$ &unctions will only return a single value and can not use either output or inout statements$

asks" asks are capable o! enabling a !unction as well as enabling other versions o! a ask asks also run with a Cero simulation however they can i! required be e%ecuted in a non Cero simulation time$ asks are allowed to contain any o! these statements$ - task is allowed to use Cero or more arguments which are o! type output' input or inout$ - ask is unable to return a value but has the !acility to pass multiple values via the output and inout statements $ "! Difference between inter statement and intra statement delay? ((de!ine register variables reg a' b' c; ((intra assignment delays initial begin

a = *; c = *; b = 1D a 2 c; (( ake value o! a and c at the time=*' evaluate ((a 2 c and then wait D time units to assign value ((to b$ end ((9quivalent method with temporary variables and regular delay control initial begin a = *; c = *; temp>ac = a 2 c; 1D b = temp>ac; (( ake value o! a 2 c at the current time and ((store it in a temporary variable$ 9ven though a and c ((might change between * and D' ((the value assigned to b at time D is una!!ected$ end

#! What is delta simulation time? $! Difference between %monitor&%display ' %strobe? hese commands have the same synta%' and display te%t on the screen during simulation$ hey are much less convenient than wave!orm display tools like cwavesE$ 3display and 3strobe display once every time they are e%ecuted' whereas 3monitor displays every time one o! its parameters changes$ he di!!erence between 3display and 3strobe is that 3strobe displays the parameters at the very end o! the current simulation time unit rather than e%actly where it is e%ecuted$ he !ormat string is like that in A(A22' and may contain !ormat characters$ &ormat characters include 5d (decimal)' 5h (he%adecimal)' 5b (binary)' 5c (character)' 5s (string) and 5t (time)' 5m (hierarchy level)$ 5Dd' 5Db etc$ would give e%actly D spaces !or the number instead o! the space needed$ -ppend b' h' o to the task name to change de!ault !ormat to binary' octal or he%adecimal$ ?ynta%" 3display (F!ormat>stringG' par>/' par>H' $$$ ); 3strobe (F!ormat>stringG' par>/' par>H' $$$ ); 3monitor (F!ormat>stringG' par>/' par>H' $$$ );

(! What is difference between )erilog full case and parallel case? - 4!ull4 case statement is a case statement in which all possible case#e%pression binary patterns can be matched to a case item or to a case de!ault$ :! a case statement does not include a case de!ault and i! it is possible to !ind a binary case e%pression that does not match any o! the de!ined case items' the case statement is not 4!ull$4 - 4parallel4 case statement is a case statement in which it is only possible to match a case e%pression to one and only one case item$ :! it is possible to !ind a case e%pression that would match more than one case item' the matching case items are called 4overlapping4 case items and the case statement is not 4parallel$4 *! What is meant by inferring latches&how to avoid it? Aonsider the !ollowing " always @(s/ or s* or i* or i/ or iH or i0) case (Is/' s*J) HBd* " out = i*; HBd/ " out = i/; HBdH " out = iH; endcase in a case statement i! all the possible combinations are not compared and de!ault is also not speci!ied like in e%ample above a latch will be in!erred 'a latch is in!erred because to reproduce the previous value when unknown branch is speci!ied$ &or e%ample in above case i! Is/'s*J=0 ' the previous stored value is reproduced !or this storing a latch is in!erred$ he same may be observed in :& statement in case an 9;?9 :& is not speci!ied$ o avoid in!erring latches make sure that all the cases are mentioned i! not de!ault condition is provided$ +! Tell me how blocking and non blocking statements get e,ecuted? 9%ecution o! blocking assignments can be viewed as a one#step process" /$ 9valuate the KL? (right#hand side equation) and update the ;L? (le!t#hand side e%pression) o! the blocking assignment without interruption !rom any other Verilog statement$ - blocking assignment 4blocks4 trailing assignments in the same always block !rom occurring until a!ter the current assignment has been completed

9%ecution o! nonblocking assignments can be viewed as a two#step process" /$ 9valuate the KL? o! nonblocking statements at the beginning o! the time step$ H$ @pdate the ;L? o! nonblocking statements at the end o! the time step$ -.! )ariable and signal which will be /pdated first? ?ignals --! What is sensitivity list? he sensitivity list indicates that when a change occurs to any one o! elements in the list change' beginMend statement inside that always block will get e%ecuted$ -0! In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? i! yes' whyE Nes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk other wise it will result in pre and post synthesis mismatch$ - ! Tell me structure of )erilog code you follow? - good template !or your Verilog !ile is shown below$ (( timescale directive tells the simulator the base units and precision o! the simulation Otimescale / ns ( /* ps module name (input and outputs); (( parameter declarations parameter parameter>name = parameter value; (( :nput output declarations input in/; input inH; (( single bit inputs output )msb"lsb, out; (( a bus output (( internal signal register type declaration # register types (only assigned within always statements)$ reg register variable /; reg )msb"lsb, register variable H; (( internal signal$ net type declaration # (only assigned outside always statements) wire net variable /; (( hierarchy # instantiating another module re!erence name instance name (

$pin/ (net/)' $pinH (netH)' $ $pinn (netn) ); (( synchronous procedures always @ (posedge clock) begin $ end (( combinatinal procedures always @ (signal/ or signalH or signal0) begin $ end assign net variable = combinational logic; endmodule -"! Difference between )erilog and vhdl? Aompilation VLP;$ <ultiple design#units (entity(architecture pairs)' that reside in the same system !ile' may be separately compiled i! so desired$ Lowever' it is good design practice to keep each design unit in itBs own system !ile in which case separate compilation should not be an issue$

Verilog$ he Verilog language is still rooted in itBs native interpretative mode$ Aompilation is a means o! speeding up simulation' but has not changed the original nature o! the language$ -s a result care must be taken with both the compilation order o! code written in a single !ile and the compilation order o! multiple !iles$ ?imulation results can change by simply changing the order o! compilation$

Pata types VLP;$ - multitude o! language or user de!ined data types can be used$ his may mean dedicated conversion !unctions are needed to convert obQects !rom one type to another$ he choice o! which data types to use should be considered wisely' especially enumerated (abstract) data types$ his will make models easier to write'

clearer to read and avoid unnecessary conversion !unctions that can clutter the code$ VLP; may be pre!erred because it allows a multitude o! language or user de!ined data types to be used$ Verilog$ Aompared to VLP;' Verilog data types a re very simple' easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling$ @nlike VLP;' all data types used in a Verilog model are de!ined by the Verilog language and not by the user$ here are net data types' !or e%ample wire' and a register data type called reg$ - model with a signal whose type is one o! the net data types has a corresponding electrical wire in the implied modeled circuit$ 7bQects' that is signals' o! type reg hold their value over simulation delta cycles and should not be con!used with the modeling o! a hardware register$ Verilog may be pre!erred because o! itBs simplicity$ Pesign reusability VLP;$ 8rocedures and !unctions may be placed in a package so that they are avail able to any design#unit that wishes to use them$ Verilog$ here is no concept o! packages in Verilog$ &unctions and procedures used within a model must be de!ined in the module$ o make !unctions and procedures generally accessible !rom di!!erent module statements the !unctions and procedures must be placed in a separate system !ile and included using the Oinclude compiler directive$ -#! What are different styles of )erilog coding I mean gate-level&continuous level and others e,plain in detail? -$! 1an you tell me some of system tasks and their purpose? 3display' 3displayb' 3displayh' 3displayo' 3write' 3writeb' 3writeh' 3writeo$ he most use!ul o! these is 3display$ his can be used !or displaying strings' e%pression or values o! variables$ Lere are some e%amples o! usage$ 3display(4Lello oni4); ### output" Lello oni 3display(3time) (( current simulation time$ ### output" RS* counter = RBb/*; 3display(4 he count is 5b4' counter);

### output" he count is **/* 3reset resets the simulation back to time *; 3stop halts the simulator and puts it in interactive mode where the user can enter commands; 3!inish e%its the simulator back to the operating system

-(! 1an you list out some of enhancements in )erilog 0..-? :n earlier version o! Verilog 'we use BorB to speci!y more than one element in sensitivity list $ :n Verilog H**/' we can use comma as shown in the e%ample below$ (( Verilog Hk e%ample !or usage o! comma always @ (i/'iH'i0'iR) Verilog H**/ allows us to use star in sensitive list instead o! listing all the variables in KL? o! combo logics $ his removes typo mistakes and thus avoids simulation and synthesis mismatches' Verilog H**/ allows port direction and data type in the port list o! modules as shown in the e%ample below module memory ( input r' input wr' input )+"*, data>in' input )0"*, addr' output )+"*, data>out );

-*!Write a )erilog code for synchronous and asynchronous reset? ?ynchronous reset' synchronous means clock dependent so reset must not be present in sensitivity disk eg" always @ (posedge clk ) begin i! (reset) $ $ $ end -synchronous means clock independent so reset must be present in sensitivity list$ 9g -lways @(posedge clock or posedge reset) begin

i! (reset) $ $ $ end -+! What is pli?why is it used? 8rogramming ;anguage :nter!ace (8;:) o! Verilog LP; is a mechanism to inter!ace Verilog programs with programs written in A language$ :t also provides mechanism to access internal databases o! the simulator !rom the A program$ 8;: is used !or implementing system calls which would have been hard to do otherwise (or impossible) using Verilog synta%$ 7r' in other words' you can take advantage o! both the paradigms # parallel and hardware related !eatures o! Verilog and sequential !low o! A # using 8;:$ 0.! There is a triangle and on it there are ants one on each corner and are free to move along sides of triangle what is probability that they will collide? -nts can move only along edges o! triangle in either o! direction' letTs say one is represented by / and another by *' since there are 0 sides eight combinations are possible' when all ants are going in same direction they wonTt collide that is /// or *** so probability o! not collision is H(U=/(R or collision probability is S(U=0(R Verilog interview Vuestions 2ow to write 345 is verilog? there r mainly R ways H write !sm code /) using / process where all input decoder' present state' and output decoder r combine in one process$ H) using H process where all comb ckt and sequential ckt separated in di!!erent process 0) using H process where input decoder and persent state r combine and output decoder seperated in other process R) using 0 process where all three' input decoder' present state and output decoder r separated in 0 process$ Verilog interview Vuestions 0-!What is difference between free6e deposit and force? 3deposit(variable' value); his system task sets a Verilog register or net to the speci!ied value$ variable is the register or net to be changed; value is the new value !or the register or net$ he

value remains until there is a subsequent driver transaction or another 3deposit task !or the same register or net$ his system task operates identically to the <odel?im !orce #deposit command$ he !orce command has #!reeCe' #drive' and #deposit options$ When none o! these is speci!ied' then #!reeCe is assumed !or unresolved signals and #drive is assumed !or resolved signals$ his is designed to provide compatibility with !orce !iles$ .ut i! you pre!er #!reeCe as the de!ault !or both resolved and unresolved signals$ Verilog interview Vuestions 00!Will case infer priority register if yes how give an e,ample? yes case can in!er priority register depending on coding style reg r; (( 8riority encoded mu%' always @ (a or b or c or selectH) begin r = c; case (selectH) HBb**" r = a; HBb*/" r = b; endcase end Verilog interview Vuestions 0 !1ase,&6 difference&which is preferable&why? A-?9W " ?pecial version o! the case statement which uses a W logic value to represent donBt# care bits$ A-?9= " ?pecial version o! the case statement which uses W or = logic values to represent donBt#care bits$ A-?9W should be used !or case statements with wildcard donTt cares' otherwise use o! A-?9 is required; A-?9= should never be used$

his is because" PonTt cares are not allowed in the 4case4 statement$ here!ore case% or caseC are required$ Aase% will automatically match any % or C with anything in the case statement$ AaseC will only match CTs ## %Ts require an absolute match$ Verilog interview Vuestions 0"!7iven the following )erilog code& what value of 8a8 is displayed? always @(clk) begin a = *; a <= /; 3display(a); end his is a tricky oneX Verilog scheduling semantics basically imply a !our#level deep queue !or the current simulation time" /" -ctive 9vents (blocking statements) H" :nactive 9vents (1* delays' etc) 0" 6on#.locking -ssign @pdates (non#blocking statements) R" <onitor 9vents (3display' 3monitor' etc)$ ?ince the 4a = *4 is an active event' it is scheduled into the /st 4queue4$ he 4a <= /4 is a non#blocking event' so itBs placed into the 0rd queue$ &inally' the display statement is placed into the Rth queue$ 7nly events in the active queue are completed this sim cycle' so the 4a = *4 happens' and then the display shows a = *$ :! we were to look at the value o! a in the ne%t sim cycle' it would show /$ 0#! What is the difference between the following two lines of )erilog code? 1D a = b; a = 1D b; 1D a = b; Wait !ive time units be!ore doing the action !or 4a = b;4$ a = 1D b; he value o! b is calculated and stored in an internal temp register'-!ter !ive time units' assign this stored value to a$ 0$!What is the difference between9 c : foo ? a 9 b; and

if <foo! c : a; else c : b; he E merges answers i! the condition is 4%4' so !or instance i! !oo = /Bb%' a = Bb/*' and b = Bb//' youBd get c = Bb/%$ 7n the other hand' i! treats =s or Ws as &-;?9' so youBd always get c = b$ 0(!What are Intertial and Transport Delays ?? 0*!What does =timescale - ns/ - ps signify in a verilog code? Btimescale directive is a compiler directive$:t is used to measure simulation time or delay time$ @sage " Otimescale ( re!erence>time>unit " ?peci!ies the unit o! measurement !or times and delays$ time>precision" speci!ies the precision to which the delays are rounded o!!$ 0+! What is the difference between ::: and :: ? output o! 4==4 can be /' * or =$ output o! 4===4 can only be * or /$ When you are comparing H nos using 4==4 and i! one(both the numbers have one or more bits as 4%4 then the output would be 4=4 $ .ut i! use 4===4 outpout would be * or /$ e$g - = 0Bb/%* . = 0Bb/*% - == . will give = as output$ - === . will give * as output$ 4==4 is used !or comparison o! only /Bs and *Bs $:t canBt compare =s$ :! any bit o! the input is = output will be = 4===4 is used !or comparison o! = also$ .!2ow to generate sine wav using verilog coding style? -" he easiest and e!!icient way to generate sine wave is using A7KP:A -lgorithm$ -! What is the difference between wire and reg? 6et types" (wire'tri)8hysical connection between structural elements$ Value assigned by a continuous assignment or a gate output$ Kegister type" (reg' integer' time' real'

real time) represents abstract data storage element$ -ssigned values only within an always statement or an initial statement$ he main di!!erence between wire and reg is wire cannot hold (store) the value when there no connection between a and b like a#Yb' i! there is no connection in a and b' wire loose value$ .ut reg can hold the value even i! there in no connection$ Pe!ault values"wire is W'reg is %$ 0 !2ow do you implement the bi-directional ports in )erilog 2D>? module bidirec (oe' clk' inp' outp' bidir); (( 8ort Peclaration input oe; input clk; input )+"*, inp; output )+"*, outp; inout )+"*, bidir; reg )+"*, a; reg )+"*, b; assign bidir = oe E a " UBbW ; assign outp = b; (( -lways Aonstruct always @ (posedge clk) begin b <= bidir; a <= inp; end endmodule

"!what is verilog case <-! ? wire )0"*, %; always @($$$) begin case (/Bb/) %)*," ?7<9 L:6Z/; %)/," ?7<9 L:6ZH; %)H," ?7<9 L:6Z0; %)0," ?7<9 L:6ZR;

endcase end he case statement walks down the list o! cases and e%ecutes the !irst one that matches$ ?o here' i! the lowest /#bit o! % is bit H' then something0 is the statement that will get e%ecuted (or selected by the logic)$ #! Why is it that 8if <0?b.- ' 0?b-.!@@@8 doesn?t run the true case? his is a popular coding error$ Nou used the bit wise -6P operator ([) where you meant to use the logical -6P operator ([[)$ $!What are Different types of )erilog 4imulators ? here are mainly two types o! simulators available$ 9vent Priven Aycle .ased 9vent#based ?imulator" his Pigital ;ogic ?imulation method sacri!ices per!ormance !or rich !unctionality" every active signal is calculated !or every device it propagates through during a clock cycle$ &ull 9vent#based simulators support R#HU states; simulation o! .ehavioral LP;' K ; LP;' gate' and transistor representations; !ull timing calculations !or all devices; and the !ull LP; standard$ 9vent#based simulators are like a ?wiss -rmy kni!e with many di!!erent !eatures but none are particularly !ast$ Aycle .ased ?imulator" his is a Pigital ;ogic ?imulation method that eliminates unnecessary calculations to achieve huge per!ormance gains in veri!ying .oolean logic" /$) Kesults are only e%amined at the end o! every clock cycle; and H$) he digital logic is the only part o! the design simulated (no timing calculations)$ .y limiting the calculations' Aycle based ?imulators can provide huge increases in per!ormance over conventional 9vent#based simulators$ Aycle based simulators are more like a high speed electric carving kni!e in comparison because they !ocus on a subset o! the biggest problem" logic veri!ication$

Aycle based simulators are almost invariably used along with ?tatic iming veri!ier to compensate !or the lost timing in!ormation coverage$ (!What is 1onstrained-Aandom )erification ? :ntroduction -s -?:A and system#on#chip (?oA) designs continue to increase in siCe and comple%ity' there is an equal or greater increase in the siCe o! the veri!ication e!!ort required to achieve !unctional coverage goals$ his has created a trend in K ; veri!ication techniques to employ constrained#random veri!ication' which shi!ts the emphasis !rom hand#authored tests to utiliCation o! compute resources$ With the corresponding emergence o! !aster' more comple% bus standards to handle the massive volume o! data tra!!ic there has also been a renewed signi!icance !or veri!ication :8 to speed the time taken to develop advanced testbench environments that include randomiCation o! bus tra!!ic$ Pirected# est <ethodology .uilding a directed veri!ication environment with a comprehensive set o! directed tests is e%tremely time#consuming and di!!icult$ ?ince directed tests only cover conditions that have been anticipated by the veri!ication team' they do a poor Qob o! covering corner cases$ his can lead to costly re#spins or' worse still' missed market windows$ raditionally veri!ication :8 works in a directed#test environment by acting on speci!ic testbench commands such as read' write or burst to generate transactions !or whichever protocol is being tested$ his directed tra!!ic is used to veri!y that an inter!ace behaves as e%pected in response to valid transactions and error conditions$ he drawback is that' in this directed methodology' the task o! writing the command code and checking the responses across the !ull breadth o! a protocol is an overwhelming task$ he veri!ication team !requently runs out o! time be!ore a mandated tape#out date' leading to poorly tested inter!aces$ Lowever' the bigger issue is that directed tests only test !or predicted behavior and it is typically the un!oreseen that trips up design teams and leads to e%tremely costly bugs !ound in silicon$ Aonstrained#Kandom Veri!ication <ethodology

he advent o! constrained#random veri!ication gives veri!ication engineers an e!!ective method to achieve coverage goals !aster and also help !ind corner#case problems$ :t shi!ts the emphasis !rom writing an enormous number o! directed tests to writing a smaller set o! constrained#random scenarios that let the computer resources do the work$ Aoverage goals are achieved not by the sheer weight o! manual labor required to hand#write directed tests but by the number o! processors that can be utiliCed to run random seeds$ his signi!icantly reduces the time required to achieve the coverage goals$ ?coreboards are used to veri!y that data has success!ully reached its destination' while monitors snoop the inter!aces to provide coverage in!ormation$ 6ew or revised constraints !ocus veri!ication on the uncovered parts o! the design under test$ -s veri!ication progresses' the simulation tool identi!ies the best seeds' which are then retained as regression tests to create a set o! scenarios' constraints' and seeds that provide high coverage o! the design