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2, FEBRUARY 2006

347

A Self-Normalizing Symbol Synchronization Lock Detector for QPSK and BPSK

Yair Linn, Member, IEEE
Abstract This paper presents a new lock detector structure for symbol timing recovery PLLs (Phase Lock Loops), which operate in QPSK (Quaternary Phase Shift Keying) and BPSK (Binary Phase Shift Keying) receivers in AWGN (Additive White Gaussian Noise) channels. The lock detector requires only 2 samples/symbol, which coincide with those required for the Gardner timing error detector. Simulation results are used to characterize the detectors behavior quantitatively. Both rectangular and square-root raised-cosine baseband data pulses are treated. It emerges that the lock detector has two very useful qualities. First, it is self-normalizing, and, secondly, the channel ES /N0 ratio can be easily determined from its value when the receiver is locked. Finally, a simple hardware structure is found for the lock metric computation process, which allows for its efcient implementation within an FPGA (Field Programmable Gate Array) or ASIC (Application Specic Integrated Circuit). Index Terms BPSK, detector, lock, M-PSK, MPSK, phase locked loop, phase shift keying, PLL, PSK, QPSK, signal to noise ratio, SNR, synchronization, timing.

I. I NTRODUCTION HEN constructing a BPSK or QPSK receiver a symbol synchronization circuit must be incorporated into its design ([4],[5]). That circuit, which usually takes the form of a PLL, is entrusted with the task of nding the best sampling instances of the I and Q channels, so that, ultimately, the Symbol Error Rate (SER) is minimized. The symbol synchronization PLL attempts to produce a phase-coherent replica of the symbol clock of the transmitted signal. This is carried out using a Timing Error Detector (TED), which supplies the error estimate upon which the PLL operates. A TED suggested by Gardner in [1] has come to be very popular, due mainly to the fact that it provides good performance while requiring only two samples per symbol. An essential complement to any PLL, including the one under discussion, is a lock detector. Lock detectors operate by producing a lock metric which is compared to a threshold; when that threshold is surpassed, the PLL is considered to be locked. In terms of lock detectors which work in conjunction with the Gardner TED, two lock detectors have been proposed by Karam et al. in reference [2], one which requires four samples per symbol (called Detector A in that paper), and another which requires two samples per symbol (which they called Detector B). In fact, the lock detector suggested here
Manuscript received January 1, 2003; revised October 24, 2003 and January 1, 2004; accepted December 30, 2004. The associate editor coordinating the review of this paper and approving it for publication was L. Hanzo. This work was supported by the National Sciences and Engineering Research Council of Canada (NSERC). The author is with the University of British Columbia, 2111 Lower Mall, Vancouver BC, Canada V6T-1Z4 (e-mail: ylinn@ece.ubc.ca). Digital Object Identier 10.1109/TWC.2006.02014.

is related to Detector B in [2], and it can be said that this papers purpose is the denition and exploration of a modied version of that detector. Though similar to the detector in [2], the proposed detector will be shown to possess several advantages, which will now be outlined. First, the suggested lock detector will be shown to be selfnormalizing, or, put another way, signal-level1 independent. What this means is that the proposed lock detector will be highly resistant to imperfect AGC (Automatic Gain Control) circuit behaviour, a quality which is particularly important when demodulating fading signals whereupon the AGCs operation is often quite nonideal. Secondly, it shall be seen that there is a very simple way to estimate the ES /N0 ratio from the lock metric. Thirdly, it shall be shown that the detector has a particularly compact hardware structure that is ideal for implementation within an ASIC or FPGA, and hence provides a method by which lock detection can be done on chip and in real time. The layout of this article proceeds as follows. First, in Section II we outline the signal and receiver models upon which the discussion applies. In Section III we dene the detector and discuss its hardware implementation. Then, Section IV investigates the detectors probability distribution, and a method is developed for deciding on the appropriate lock thresholds according to the desired lock probabilities and false alarm rates. Finally, Section V is devoted to formulating conclusions. II. S IGNAL AND R ECEIVER M ODELS

denote the data pulse and 1/T for the symbol rate. For are mutually independent data QPSK ar , br {1, 1} and streams. For BPSK, ar 2, 2 and r, br = 0. In this paper, we shall deal with the important cases of rectangular 1/T T /2 t T /2 baseband pulses, i.e. p(t) = , 0 otherwise as well as SRRC (Square-Root Raised-Cosine) pulses ([10]
4t/T . Using i to eq. 68.15) p(t) = 4 T (1162 t2 /T 2 ) signify the signals propagation delay, the modulated signal at the entrance of the I-Q demodulator is [4] sm (t) = Re[m(t i )eji t+ji ] and that signal is corrupted by an

r =

Let us denote the baseband signal as m(t) = ar / 2 + j br / 2 p(t rT ), where we use p(t) to

cos((1+)t/T )+ sin((1)t/T )

1 The term signal level as it is employed in this paper should not be confused with the term ES /N0 ratio. The former refers to the total signal+noise power at the inputs of the samplers in Fig. 1, while the latter refers to the signalto-noise ratio of that signal. This shall be elaborated upon shortly.

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AWGN channel. The receiver has the general structure of Fig. 1, where: 1. 1/TS = 2/T is the sample rate. 2. n(t) N (0, N0 W ) where W is the width of the IF (Intermediate Frequency) lter (not shown). 3. K represents the equivalent physical gain associated with the circuit. Generally, K is a slow function of time that is controlled by the AGC, which regulates its value in order to attain desired signal amplitude levels at the inputs of the I and Q samplers (ideally, the nominal signal level is such that the samplers never saturate yet their entire dynamic range is exploited). It can be shown (see [14] chap. 9) that, as well as being a function of the AGCs parameters, K is also a function of the ES /N0 . For simplicity, K is assumed the same in the I and Q arms, though this is not a necessary condition for the analysis in this paper to be valid and in fact the I and Q arms may have arbitrarily different K s. 4. is the frequency difference between the local and received carriers, and o is the phase of the local carrier. We shall assume, unless otherwise indicated, that the carrier synchronization loop is ideally locked, i.e. = 0 and i = o . However it is declared without proof that the proposed detector works quite well in the presence of small2 carrier frequency errors. 5. The matched lter h(t) = p(t) is assumed ideal. When in this paper the terms signal-level dependence or AGC-dependence are cited, this alludes to a dependence on the AGC-controlled gain K . Since K is arbitrary and multiplies both the signal and noise terms in each of the I and Q arms, it is clear that such a dependence of the lock detector characteristics or threshold is a mathematical and practical liability, it brings in K s dynamic range as a quantity that needs to be taken into account as part of the lock detection circuits parameters. Even more troubling, since K is not a constant but is rather a function of time controlled by the AGC, any dependence on K implies a dependence of the lock detector on the AGCs behavior, often through a distinctly nonlinear relationship. The independence of the suggested lock detector vis-` a-vis K is one of its primary advantages with respect to the detectors in [2], because it decouples the lock detectors threshold and value from the AGCs operating point and performance. This aspect of the detectors characteristics is elaborated upon throughout the ensuing sections. III. D ETECTOR D EFINITION AND I MPLEMENTATION A. Basic Denitions and Equations We use the notation i to refer to the receivers estimate of i . We dene the symbol synchronization timing error3 as i ) mod T , with the modulo operations destination = (i
2 Dened as /2 << (N T )1 , with N dened in (4)-(5). For the case of unlocked carrier, the lock detectors behavior and threshold computations differ from those presented in the paper, though the lock detector can still be used quite reliably with an unlocked carrier. However, quantitative treatment of this issue is beyond the scope of this paper. 3 Generally, both i and are functions of time that are updated with each sampling clock, i.e. they should be written as i (kTS ) and (kTS ). However this relationship is assumed to be understood, and the notations i and are used.

set being [T/2, T/2]. The even samples of the channels are then: Ie (n) = I (t)|t=2nTs + i and the odd samples are: Qo (n) = Q(t)|t=(2n+1)Ts + i (2) Under perfect symbol synchronization conditions (i.e. i = i ), the even samples correspond to the peaks of the symbols, and the odd samples correspond to the transitions between symbols. It is worthy to note that it is precisely these sets of samples that are required for the Gardner TED [1]. Let us dene (strictly for notational convenience): yI (n) = yQ (n) =
2 2 Re[(Ie (n) + j Io (n))2 ] Ie (n) Io (n) = , 2 (n) + I 2 (n)) 2 (n) + I 2 (n) (Ie I o e o

Qe (n) = Q(t)|t=2nTs + i

(1)

Io (n) = I (t)|t=(2n+1)Ts + i

2 Q2 Re[(Qe (n) + j Qo (n))2 ] e (n) Qo (n) = . 2 2 (Q2 Q2 e (n) + Qo (n)) e (n) + Qo (n) (3) Using the above notations, we dene:

sI,N =

1 2N

yI (n),
n=N +1

sQ,N =

1 2N

yQ (n).
n=N +1

(4)

The lock detector for QPSK is then: sN =

1 2N

(yI (n) + yQ (n)) = sI,N + sQ,N

n=N +1

(5)

which is a nite approximation of s = erator dened as x(n) =

yI (n) + yQ (n) , where represents the time average opalso immediately clear from the preceding denitions that s = sI, + sQ, , with sI, = lim sI,N = yI (n) and sQ, = lim sQ,N = yQ (n) . N As for the case of BPSK, in the absence of carrier synchronization4 the signal alternates between the I and Q arms, and therefore sN must be used. After the carrier is acquired, the Q channel contains only noise and therefore sI,N is the appropriate detector. As noted earlier, for the analysis of this paper we assume a locked carrier loop; hence the detector for BPSK alluded to henceforth refers to sI,N . The reasoning behind the lock detector is apparent when one realizes that if the denominator terms are omitted in (3), we arrive at Detector B that is suggested in [2]. Roughly speaking, it can be said that the denominator terms perform adaptive normalization, an action that has a profound effect upon the detectors statistics and structure and that transforms the proposed detector into a detector that is quite different from Detector B, despite the notational similarity. One effect that is immediately apparent is that this normalization eliminates any dependence of the lock detector on K , a fact which is trivial to demonstrate if one substitutes the expressions for I (t) and Q(t) (found in Fig. 1) into (1) through (3). For brevity
4 See

lim sN = It is

N 1 x(n). 2 N N n=N +1

lim

footnote 2.

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Fig. 1.

Simplied structure of a BPSK/QPSK receiver.

Fig. 2.

Efcient hardware implementation for sN and sI,N .

and due to its straightforward nature, that derivation is omitted in this paper. The advantages of independence from K , as it relates to independence from the AGC, have been discussed at the end of Section II. Further benets are also achieved regarding the hardware implementation of a circuit employing the detector, and this is the subject of the following subsection. B. Hardware Realization sN and sI,N can be computed via an extremely economical hardware structure. This can be easily seen by looking at (3) and (5): the terms yI (n) and yQ (n) can be computed by xedpoint LUTs (Lookup Tables) as shown in Fig. 2, adding the results (in the case of sN ), and inputting that to a single digital IAD (integrate-and-dump) module (the need to divide by 2N is avoided if 2N is chosen to be a power of 2, in which case the division is approximated by discarding the least signicant log2 2N bits at the output of the IAD). Thus, summation is the only mathematical operation required. Now, as it is seen from inspection that |yI (n)| < 1 and |yQ (n)| < 1

(ignoring the innitesimally probable case in which one of these terms is unity, which can always be approximated to any desired tolerance by a close enough fraction for that term), this implies that the LUTs in Fig. 2 need only to facilitate the representation of fractional numbers, consequently rendering their implementation quite practical in xed-point hardware. In contrast, implementation of the detectors in [2] through LUTs would mean that they and the ensuing datapaths would have to accommodate the dynamic range of K 2 , which can be uneconomical to implement in xed-point hardware and implies a nonlinear dependence upon the AGC-controlled gain K . Returning to Fig. 2, we see that the lookup tables are identical, i.e. their outputs are the same function of their inputs. Thus, through a slightly more complicated time-sharing arrangement only a single lookup table can be used, with which yI (n) and yQ (n) would be computed in sequence rather than in parallel. IV. D ETECTOR C HARACTERISTICS A. Lock Detector Expected Value When the symbol synchronization loop is unlocked, it is easy to surmise (from symmetry considerations alone) that the lock detectors expectation is zero. A justication of this conclusion using a graphical method is presented in [11] and is omitted here. It can be shown [11], in a semi-analytical derivation, that for the case of rectangular data pulses S (ES /N0 ) = E [ sN | locked] = s =

where p1 () is a Rician phase distribution ([3],[4],[7]), given by

cos(2)p1 ()d()

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B. Variance and Distribution of sN and sI,N To allow for the lock detection and false alarm probabilities to be computed, the variance and distribution of the lock metric needs to be evaluated. Recalling (3)-(5), and recalling further that for any input signal condition we have |yI (n)| 1 and |yQ (n)| 1, we consequently arrive at the bound: var (yI (n) + yQ (n))

= E (yI (n) + yQ (n))

E 2 [yI (n) + yQ (n)]

2

(sup (|yI (n) + yQ (n)|)) 2 (sup (|yI (n)|) + sup (|yQ (n)|)) = (1 + 1)2 = 4

(6)

Fig. 3. Graph of S (ES /N0 ) = E [ sN | locked] (for QPSK) and B (ES /N0 ) = E [ sI,N locked] (for BPSK) as a function of the ES /N0 ratio.

Let us look at two different symbol indexes n1 , n2 (n1 = n2 ), with and their coordinate pairs on the I channel, (Ie (n1 ), Io (n1 )) and (Ie (n2 ), Io (n2 )). Although those coordinate pairs are not necessarily independent, we assume for the moment that yI (n1 ) and yI (n2 ) are nonetheless uncorrelated. A similar assumption is made regarding the Q channel. Using those postulations, we deduce from (5) and (6) that: var (sN ) =
1 2 2N N n=N +1 2 N

p1 () = 1+
cos()

1 2 ES N0

ES exp 2 N0

var (yI (n) + yQ (n))

ES N0

cos () exp e x
2

ES 2N0

cos2 ()

1 2 2N

(7)

2N 4 =

/2 dx .

Similarly, for BPSK we have B (ES /N0 ) = E [ sI,N | locked] = sI, = with p2 () = 1+
cos() 1 2 2ES
0

1 2

cos(2)p2 ()d()

Though made under unproven assumptions, computer simulations conducted by the author (to be discussed shortly) have shown that the bound in eq. (7), though not always tight, is still a valid upper bound on the variance at both locked and unlocked states, for both rectangular and SRRC pulses. The distribution of sN has also been shown, through simulations, to be Gaussian. Thus, to a good if perhaps conser vative approximation (see footnote 7), dening S (ES /N0 ) = E [ sN | locked] (see Fig. 3) we have sN |locked N (S (ES /N0 ) , 2/N ) sN |unlocked or noise only input N (0, 2/N ) (8)

exp

E S N0 ES N0

2ES N0

cos () exp e x
2

cos2 ()

/2

dx .

For BPSK and sI,N , dening B (ES /N0 ) = E [ sI,N | locked] (see Fig. 3) and using a similar procedure we have sI,N |locked N (B (ES /N0 ) , 1/2N ) sI,N |unlocked or noise only input N (0, 1/2N )

Due to their innite duration, it is not possible to adopt the same analysis method employed in [11] to SRRC pulses. Instead, computer simulations results, derived from using (4) and (5) upon simulated inputs, are presented in Fig. 3. Note that the expected value is identical for rectangular pulses and for SRRC pulses with = 1. Further utility is revealed when we realize that since the lock-detector expected value (when locked) is a one-to-one function of the ES /N0 (see Fig. 3), so we can estimate the latter from sN (for QPSK) or sI,N (for BPSK) using the inverse relation. A quantitative investigation of this estimation procedure can easily be done in a manner very similar to the analysis in [12]. Such is done in [13], where it is shown that the estimation method discussed here provides quantitative and qualitative advantages similar to those achieved by the method discussed in [12].

(9) Simulation results at ES /N0 = 0dB and ES /N0 = 40dB for QPSK are given in Fig. 4. In that gure, results are presented for the unlocked state for two symbol synchronization frequency errors, f = 5.7/T and f = 8 103 /T , which are also those that were treated in [2]. An interesting phenomenon for N = 32 can be seen in Fig. 4: for the unlocked state at f = 8 103 /T the variances for ES /N0 = 40dB appear to be larger than those for ES /N0 = 0dB (and they are also larger than the bound 2/N ). This is easily explained by the fact that with such a small frequency error, a lock detector operating on only 2N = 64 symbol intervals will not be able to average the lock metric over the whole timing error range of T/2 T/2 but rather only over a portion of it, as can be seen by recalling that (kTS ) = (f kTS T + 0 ) mod T where 0 is the initial timing error. When many lock detectors

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Fig. 4. Variance of simulated metrics, sN , for QPSK input signal, as a function of the number of symbols 2 N that are used to compute them, for various ES /N0 ratios and pulse shapes. Also plotted is the theoretical bound 2/N given by eq. (7).

are computed their absolute values will therefore occupy a wide range of values from 0 to the locked-state value, and hence the variance will then largely be a function of the locked-state value (which increases with SNR), rather than a function of the lock state. This phenomenon is not unique to the proposed detector; in fact, it is discussed in detail in [2] Sec. IV. In general, to ensure that the detector has a sufcient 1 number of symbols, one must choose N >> (fmin T ) , 5 where fmin is the minimum frequency error for which there is a desire for the out-of-lock state to be detected reliably. Equations (7)-(9) can be said to be contingent upon that assumption.

(assuming6 < S ()): PD = P sN >

1 4/N Es N0

=
2 N 4

e(S ())
N 4

(10)

=1 2 erf c
1 4/N

( S ())
N 4

PF A = P ( sN > | noise only input)

2 N 4

d = 1 2 erf c

(11)

from which it immediately follows that a suitable and N are given by: = erf c1 (2PF A ) S () , erf c1 (2PF A ) erf c1 (2PD )
2

C. Lock and False Alarm Probabilities and Circuit Parameter Determination Dealing rst with QPSK, from eq. (8), at a given threshold > 0, for a given input ES /N0 ratio denoted , the lock detection probability PD and false alarm probability PF A are
5 Typically, we would have f min < fL , where fL is the lock-range ([5],[6]) of the symbol synchronization PLL. Thus, when the timing frequency error is smaller than fmin we would transition to the locked state, hence avoiding the problem just outlined.

N =4

erf c1 (2PF A ) erf c1 (2PD ) S ()

(12)

Using similar derivations regarding the case of BPSK and sI,N , one arrives at: = erf c1 (2PF A ) B () , erf c1 (2PF A ) erf c1 (2PD )

6 We are making the implicit assumption that we are disinterested in detecting lock for any ES /N0 = for which S (), since for all Es /N0 = for which S (), we have PD 0.5.

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V. C ONCLUSIONS A new symbol synchronization lock detector for QPSK and BPSK was presented. The subsequent analysis revealed that it is self-normalizing, hence decoupling the symbol lock detection process from the AGC circuit and considerably simplifying the computation of the lock thresholds, the lock probabilities, and the false alarm rates. It was found that the ES /N0 ratio can also be estimated from the lock metric value. A simple hardware implementation for the detector was outlined, one which is particularly appealing for implementation within an ASIC or FPGA. For all of the above reasons, the detectors suggested in this paper have immediate practical applications in contemporary receivers. ACKNOWLEDGMENT
Fig. 5. Required number of symbols 2 N that are needed to achieve a desired PD and PF A , with = 1 dB, for sN (for QPSK) and sI,N (for BPSK).

The author would like to thank his supervisor Prof. Matthew J. Yedlin (University of British Columbia) and Prof. Shmuel Zaks (Technion Israel Institute of Technology) for their continued mentorship, encouragement and support. Additionally, the author would like to thank the editor Prof. Lajos Hanzo for his guidance, and the anonymous reviewers for their efforts and their helpful feedback. R EFERENCES
[1] F. M. Gardner, A BPSK/QPSK Timing Error Detector for Sampled Receivers, IEEE Trans. Commun., vol. 34, no. 5, pp. 423-429, May 1986. [2] G. Karam, V. Paxal, and M. Moeneclaey, Lock Detectors for Timing Recovery, Proc. ICC , pp. 1281-1285, June 1996. [3] A. D. Whalen, Detection of Signals in Noise. New York: Academic Press, 1971. [4] J. G. Proakis, Digital Communications, 4th ed. New York: McGraw-Hill, 2001. [5] H. Meyr, M. Moeneclaey, and S. A. Fechtel, Digital Communication Receivers. New York: John Wiley & Sons, 1997. [6] F. M. Gardner, Phaselock Techniques, 2nd ed. New York: John Wiley & Sons, 1979. [7] H. Gudbjartsson and S. Patz, The Rician distribution of noisy MRI data, Magnetic Resonance Medicine, vol. 34, no. 6, pp. 910914, Dec. 1995. [8] M. R. Spiegel, Mathematical Handbook of Formulas and Tables. Singapore: McGraw-Hill International Edition, 1990. [9] R. L. Peterson, R. E. Ziemer, and D. E. Borth, Introduction to Spread Spectrum Communications. New Jersey: Prentice Hall, 1995. [10] J. D. Gibson (editor), The Communications Handbook, 2nd ed. Boca Raton: CRC Press, 2002. [11] Y. Linn, A Symbol Synchronization Lock Detector and SNR Estimator for QPSK, with Application to BPSK, Proc. 3rd IASTED International Conf. on Wireless and Optical Communications (WOC 2003), pp. 506514, July 2003. [12] Y. Linn, Quantitative Analysis of a New Method for Real-Time Generation of SNR Estimates for Digital Phase Modulation Signals, IEEE Trans. Wireless Commun., vol. 3, pp. 1984-1988, Nov. 2004. [13] Y. Linn, A Hardware Method for Real-Time SNR Estimation for MPSK using a Symbol Synchronization Lock Metric, Proc. 9th Canadian Workshop on Information Theory (CWIT 2005), pp. 247-251, June 2005. [14] A. Blanchard, Phase-Locked Loops Application to Coherent Receiver Design. New York: John Wiley & Sons, 1976. [15] H. Gudbjartsson and S. Patz, Erratum to the Rician distribution of noisy MRI data, Magnetic Resonance Medicine, vol. 36, pp. 331333, Aug. 1996.

Fig. 6. Required threshold that is needed to achieve a desired PD and PF A , with = 1 dB, for sN (for QPSK) and sI,N (for BPSK).

N=

erf c1 (2PF A ) erf c1 (2PD ) B ()

(13)

Unsurprisingly, all the quantities in eqs. (10)-(13) are completely independent of K . Refer to Fig. 5 and Fig. 6 for an example of the use of (12)-(13) to determine7 the required and N needed to fulll requirements of PD and PF A for a given minimum ES /N0 of . Note that, in those gures, the results for = 1 apply for rectangular pulses as well. This is because the expected value of the lock detector for both pulse shapes is the same (see Fig. 3), and hence (from (12)-(13)) so are and N .
7 Eqs. (10) and (11) are inequalities because the variance of s N is bounded by the limit 2/N (see (7)), and not necessarily equal to it. Thus employment of (12) to determine N will produce conservative (i.e. larger than needed) values of N . For similar reasons, the use of (13) for sI,N and BPSK will yield conservative values of N .

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Yair Linn (M01) received his B.Sc. (honors) in computer engineering from the Technion Israel Institute of Technology, Haifa, Israel, in 1996. He is currently pursuing the Ph.D. degree in electrical engineering at the University of British Columbia, Canada, under the direction of Prof. M. J. Yedlin. In the years 1996-2001 he was employed as an Electrical Engineer in the Israeli Ministry of Defense, where he worked with the development, implementation, and deployment of wireless communications systems. His current research interests include synchronization in wireless receivers, estimation of wireless channel

parameters, and implementation of real-time digital signal processing algorithms in FPGAs. Mr. Linn was awarded the Jean MacDonald Graduate Fellowship scholarship as a winner of the University Graduate Fellowship competition at UBC in 2002. In April 2003, he was awarded a postgraduate scholarship by the National Sciences and Engineering Research Council of Canada (NSERC), as a winner of the 2003/4 NSERC Postgraduate Scholarship Competition. In April 2005, he was awarded an NSERC Canadian Graduate Scholarship as a winner of the 2005/6 NSERC Postgraduate Scholarship Competition. In November 2005 he was awarded the Bell Canada 125th Anniversary Graduate Scholarship.