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8086 Memory Addressing The 8086 memory address space can be viewed as a sequence of one million bytes in which

any byte may contain an 8-bit data element and any two consecutive bytes may contain a 16-bit data element. There is no constraint on byte or word address boundaries. The address space is physically connected to a 16-bit data bus by dividing the address space into two 8-bit banks of up to 512K bytes each. One bank is connected to the lower half of the 16-bit data bus (D0 D7) and contains even address bytes. i.e., when A0 bit is low, the bank is selected. The other bank is connected to the upper half of the data bus (D8 - D15) and contains odd address bytes. i.e., when A0 is high and BHE (Bus High Enable) is low, the odd bank is selected. A specific byte within each bank is selected by address lines A1-A19.

Higher Address Bank (512K x 8) ODD A1-A19 Address Bus Data Bus (D0 - D15)

BHE

Lower Address Bank (512K x 8) EVEN D0-D7

A0

D8-D15

Fig. 5

Data can be accessed from the memory in four different ways. They are: 8 - bit data from Lower (Even) address Bank. 8 - bit data from Higher (Odd) address Bank. 16 - bit data starting from Even Address. 16 - bit data starting from Odd Address.
O dd B an k Even Ba n k

8-bit data from Even address Bank

x + 1 x + 3 x + 5

x x + 2 x + 4

BH E = 1 A1 -A1 9 D 8 -D 15 D 0 -D 7

A0 = 0

D 0 -D 15

Fig. 6 8-bit Data Access from Even Address

To access memory bytes from Even address, information is transferred over the lower half of the data bus (D0 - D7). The A0 is output LOW and BHE is output HIGH enabling only the even address bank. It is illustrated in fig. 6.

Example: Consider loading a byte of data into CH register (higher order 8-bits of CX register) from the memory location with an even address. The data will be accessed from the even bank via the (D0 - D7) DATA BUS. Although this data is transferred into the 8086 over the lower 8-bit lines, the 8086 automatically redirects the data to the higher 8-bits of its internal 16bit data path and hence to the CH-register. This capability allows bytes input - output transfer via the AL register to access I/O device connected to either the upper half of the data bus or the lower half of the 16-bit data bus. 8-bit Data from Odd Address Bank To access memory byte from an odd address information, is transferred over the higher half of the data bus (D8 - D15). The BHE output low enables the upper memory bank. A0 is output high to disable the lower memory bank. It is illustrated in fig. 7
O dd B ank Even Bank

x + 1 x + 3

x x + 2

BHE =0 A 1 -A 1 9 D 0 -D 7 D 8 -D 1 5 D 0 -D 1 5

A0 = 1

Fig. 7

16-bit Data Access starting from Even - Address


Odd Bank Even Bank

x+1 x+3

x x+2

A1-A19

D8-D15

BHE =0 D0-D7

A0 = 0

D0-D15

Fig. 8

16-bit data from an even address is accessed in a single bus cycle. Address lines A1 A19 select the appropriate byte within each bank. A0 low and BHE low enables both banks simultaneously. This is illustrated in fig. 8. 16-bit Data Access starting from Odd Address A 16-bits word located at an odd address (two consecutive bytes with the least significant byte at an odd byte address) is accessed using two bus cycles. During the first bus cycle the lower byte (with the odd address 0005 as shown in fig. 9 (a)) is accessed.

Odd Bank

Even Bank

Odd Bank

Even Bank

0005 0007 0009

0004 0006 0008

0005 0007 0009

0004 0006 0008

A1-A19 A1-A9 D0-D7 D8-D15

A1-A19 A1-A9 D8-D15 D0-D7

(a) First Access from Odd Address

(b) Next Access from Even Address

Fig. 9

During the second bus cycle, the upper byte (with the even address 0006H as in fig. 9 (b)) is accessed. During the first bus cycle, A1 - A19 address bus specifies the address and A0 as 1 and BHE is low. Therefore the even memory bank is disabled and odd memory bank is enabled. During the second bus cycle, the address is incremented. Therefore A0 is zero and BHE is made high. The even memory bank is enabled and the odd memory bank is disabled. 8086 Basic System Concepts 8086 can be used either in a minimum mode system or a maximum mode system. The fig. 10 and fig. 11 shows minimum and maximum modes with groups of ICs to generate address bus, data bus and control bus signals. Using these buses, the CPU can be connected to ROM, RAM, PORTS and other devices to form a complete system. BASIC 8086 Minimum mode System 8282 I/O ports are used to latch the addresses from the 8086 Microprocessor Data/Address bus. By using three 8282, A0-A15, BHE , A16-A19 lines are latched during T1 state. OE (Output Enable) input of the 8288 I/O ports are grounded; the bus will therefore, never be floated. ALE signal from 8286 is used to strobe the addresses into the 8282 I/O latches. Since the Data Bus is bi-directional, 8286 bi-directional bus transceivers are used, in order to create a separate Data Bus from the 8086 Address/data Bus. The DT/ R and

DEN outputs from 8086 are used for 8286 "T" signal and OE inputs respectively. Maximum Mode Configuration
When MN/ MX pin is strapped to GND, the 8086 treats pin 24 through 31 to be in maximum mode. An 8288 bus controller interprets status information coded into S0, S1 and S2 to generate bus timing and control signals compatible. DEN, DT/ R and ALE control outputs, are now generated by the 8288 bus controller. The DEN from 8288 is inverted and given to 8286 transceiver to enable the output. The output enable of 8282 latch is grounded. As in minimum mode the address-data lines are latched through 8282 latch. The ALE signal from the 8288 bus controller latches the address during the T1 state of the microprocessor. The DEN signal is used to enable the transceiver either to transmit or receive data from I/O devices and memory. The DT/ R signal is used to transmit or receive the data as the need may be.

PCLK

+5V RES
C lo c k g e n e r a to r
AEN2 AEN1 F /C

CLK READY RESET

M /IO IN T A RD WR M N /M X +5V

C o n tr o l Bus

W a it -S t a t e G e n e ra t o r

ALE

STB OE

A0 - A19 A d d re s s B u s

8086 C PU

A D 0 -A D 1 5 A 1 6 -A 1 9 BHE

8282 L a tc h

BHE

D0 - D15 8286 D T /R DEN T OE 16

Fig. 10 8086 Minimum Mode System


+5V
CLK Clock generator MN/MX S0 S1 S2 Gnd S0 S1 S2 CLK MRDC MWTC AMWC IORC IOWC AIOWC INTA

RESET DEN DT/R

Wait-State Generator

ALE

8086 CPU

STB OE

8288 Bus Controller


A0 - A19 Address Bus BHE

RES

READY

AD0-AD15 A16-A19

8282 Latch

T OE
8286 Transceiver

DATA

Fig. 11 8086 Maximum Mode Configuration

5 Bus Read Machine Cycle Fig- 12 shows the timing diagram of 8086 read machine cycle with WAIT state. The clock (CLK) signal is obtained from the clock-generator 8284. Each cycle of the clock is referred to as a state. Minimum number of states to access a data is four. They are T1, T2, T3, and T4 states. During T1 state of a read machine cycle an 8086 first asserts the M/ IO signal. It will assert this signal high if it is going to read from memory during memory read cycle and it will assert M/ IO low if it is going to do a read from an Input port during its read cycle. The timing diagram in fig. 12 shows two lines for the M/ IO signal, because the signal may be going LOW or going HIGH for a read cycle. The point where the two lines cross indicate the time at which the signal becomes valid for this machine cycle. After asserting M/ IO , the 8086 sends out a high on the address latch enable signal, ALE. The microprocessor sends out on AD0-AD15, A16 through A19 and BHE lines, the address of

the memory location that it wants to read. Since the latches are enabled by ALE being high, this address information passes through the latches to their outputs. The 8086 then makes the ALE output low. This disables the latches (8282) and holds the address information latched on the latch outputs. The address information latched on the latch outputs can now be used to select the desired memory or port location. In the timing diagram, the first point at which the two (AD0 AD15) cross represents the time at which the 8086 has put a valid address on these lines. Two lines DO NOT indicate that all 16 lines are going high or going low at this point. The crossed lines indicate the time at which a valid address is on the bus.
T1 CLK T2 T3 Twait T4

AD0-AD15 BHE

ALE

S2 -S0

M/IO RD

READY DT/R DEN WR

Fig. 12 Read Timing Diagram

Since the address information is now held on the latch, the 8086 does not need to send it out any more. As shown in fig. 12 the 8086 floats the AD0 - AD15 lines so that they can be used to input data from memory or from a port. At about the same time the 8086 also remove the BHE and A16-A19 information from the upper lines and sends out some status information on these lines. The 8086 is now ready to read data from the addressed memory locations or port. During T2-state the 8086 asserts its RD signal low. This signal is used to enable the addressed memory device or port device. At the end of T3 state the microprocessor makes the RD signal high and reads the data available on the data bus, provided the READY input signal is high. It is the duty of the external circuit to see that valid data is made available on the data bus. If the READY input pin is not high at the sampled time in a machine cycle, the 8086 will insert one or more WAIT states between T3 and T4 states in that machine cycle. An external hardware device is set up to pulse READY low before the rising edge of the clock in T2 state. After the 8086 finishes T3 of the machine cycle, it enters a WAIT state. If the READY input is still low at the end of a WAIT state, then the 8086 will insert another WAIT state. The 8086 will continue inserting WAIT states until the READY input is sampled high again. If the READY input is sampled high again during T3 or during the WAIT state, the microprocessor comes out of the WAIT state and will initiate T4 of the machine cycle.

The DEN signal is used to enable bi-directional buffers on the data bus. The data enable signal, DEN, from the 8086 will enable the data buffer when it is asserted LOW. The data transmit / receive signal DT/ R from the 8086 is used to specify the direction in which the buffers are enabled. When DT/ R is asserted high, the buffers will, if enabled by DEN, transmit data from the 8086 to Memory or I/O ports. When DT/ R is asserted low, the buffers, if enabled by DEN, will allow data to be received from Memory or I/O ports of the 8086. DT/ R is asserted during T1 of the machine cycle. The DEN is asserted after the 8086 finishes using the data bus to send the lower 16 address bits. BUS Write Machine Cycle The 8086 write operation is very similar to the read cycle. During T1 of a write machine cycle the 8086 asserts M/ IO low if the write is going to a port and it asserts M/ IO high if the write is going to memory. At about the same time the 8086 raises ALE high to enable the address latches. The 8086 then assert BHE and on the lines AD0 - AD19, it output the address that it will be writing to. When writing to a port, line A16 - A19 will always be low, because the 8086 only sends out 16-bits port addresses. The 8086 brings ALE low again to latch the address on the outputs of the latches. In addition to holding the address, the latches also function as buffers for the address lines. After the address information is latched, the 8086 remove the address information from AD0 - AD15 and outputs the desired data on these lines.

Fig 13 Write Timing Diagram

If the READY input is sampled LOW by the 8086 before or during T2 of the machine cycle, the 8086 will insert a WAIT state after T3. If the READY input is sampled high before the end of the WAIT state, the 8086 will go on with state T4 as soon as it completes the WAIT state. The 8086 will continue to insect wait states for as long as the READY is sampled low just before the end of each WAIT state.

Comparison of 8086 with the 8088 Microprocessor The 8088 CPU is an 8-bit processor designed around the 8086 internal structure. Most internal functions of the 8088 are identical to the equivalent 8086 functions. The 8088 handles the external bus the same way the 8086 does, one difference being hat the 8088 handles only 8-bits at a time. 16-bit operands are fetched or written in two
+5V G n d (2 ) NM I IN T R C lk A D 0 -A D 7 (8 ) A 8 -A 1 5 (8 ) A 1 6 /S 3 (4 ) A 1 9 /S 6 Te s t R eady R e se t S S o (H ig h ) M N /M X RD H O L D (R G /G T 0 ) H L D A (R Q /G T 1)

8088

W R (LO C K ) IO /M (S 2 ) D T /R (S 1 ) D E N (S 0) A L E (Q S 0 ) IN T A (Q S 1 )

Fig . 14 Pin Configuration of 8088 Microprocessor

consecutive bus cycles. To an assembly language programmer both processors will appear identical with the exception of execution times. The internal register structure is identical and all instructions produce the same end result. The pin configuration of 8088 is illustrated in fig. 14. The major differences between 8088 and 8086 are outlined below: The queue length is 4 bytes in the 8088, where as the 8086 queue comprises of 6 bytes. The 8088 BIU will fetch a new instruction to load into the queue as soon as it finds a byte hole (space available) in the queue. The 8086 waits until a 2 byte space is available. The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit fetches and writes from / to memory take an additional four clock cycles. The CPU is also limited by the speed of instruction fetch. When the more sophisticated instructions of the 8088 are being used, the queue has time to fill and the execution proceeds as fast as the execution unit will allow. The hardware interface of the 8088 has some major differences as compared to the 8086. The pin assignments are nearly identical, however, with the following functional changes. A8-A15: These pins are only address outputs on the 8088. These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines. SS0 provides the S0 status information in the minimum mode. This output occurs on pin 34 in minimum mode only. DT/ R , IO/ M and SS0 provide the complete bus status in minimum mode. This is shown in table 5
IO/M DT/R SSO CHARACTERISTICS

0 0 0 0

0 0 1 1

0 1 0 1

Code Access Read Memory Write Memory Passive

1 1 1 1

0 0 1 1

0 1 0 1

Interrupt Acknowledge Read I/O port Write I/O port Halt


Table 5

BHE has no meaning on the 8088 and has been eliminated. IO/ M has been inverted. i.e., (In 8086, this pin as IO /M)
ALE is delayed by one clock cycle in the minimum mode when entering HALT to allow the status to be latched with ALE.

Fig 15 illustrates the 8088 microprocessor system configuration. The Address-Data lines AD0-AD7 are connected to the 74LS373 latch. The address from the multiplexed bus is latched into the 74LS373 when an ALE (Address latch enable) is active during T1 state of the microprocessor. The address A0-A7 is available on the output of 74LS373 and can be used for memory (along with A16-A19), and I/O devices. The address lines A8-A15 are not multiplexed with data lines or status lines, hence there is no need to latch these address lines. The data bus is connected to the 74LS245 transceiver. The 74LS245 is controlled by DT/ R and DEN to transmit and receive and Data respectively. Since 74LS373 and 74LS245 are also buffered chips, it is not required to add buffers to these chips. The address lines A8-A15 need to be buffered and hence the 74LS 244 buffer is used for these lines. The output of 74LS244 is always enabled.

A 1 9 /S 6 - A 1 6 /S 3

OE 7 4 L S 37 3

A19 - A16

ALE
A15 - A8

G 74LS 244 OE

8088
AD0 - AD7

OE A0 - A7

7 4 L S 37 3

D T /R

DEN D0 - D7 7 4 L S 24 4 G D /R

Fig. 15

1. 2. 3. 4. 5. 6. 7.

Compare 8086 and 8088 microprocessors. In what ways are they similar? In what ways do they differ? What is the purpose of the ALE signal in an 8086 system? What is the major difference between an 8086 operating in minimum mode and an 8086 operating in maximum mode? Describe the response of an 8086 when its RESET input is asserted high. Why are buffers often needed on the address, data and control buses in a microprocessor system? What are the function of the 8086 DT/ R and DEN signals? Explain the difference between a memory read cycle and an I/O read cycle.

8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

What are the main functions provided by the 8288 bus controller when used with the 8086/8088 maximum mode operation? Explain the operation of the LOCK pin. What conditions do the QS1 and QS0 pins indicate about the 8086/8088? What three house keeping chores are provided by the 8284 clock generators? Explain the operation of the TEST pin and the WAIT instruction. What is the function of QS0 and QS1 signals? With a timing diagram explain I/O read machine cycle. With a timing diagram explain I /O Output-Write machine cycle with two wait states. Mention an affiliation of the OSC signal in 8284? What is the application of the PCLK signal? Briefly describe the purpose of each of the T-states T1, T2, T3 and T4. What is the purpose of the status bits S3 and S4?

Objective Type Questions


State true or false (a) Both the address and data bus are unidirectional. (b) Both the 8086 and 8088 microprocessors address 64 K bytes of memory. (c) No difference exits between the memory maps of 8086 and 8088. (d) The string source (SI) is located in the Data Segment (DS) and the string destination is located in the Extra segment (ES) for string instructions. 2. The INTR input is -- sensitive. 3.. The 8286 microprocessor has a 1-bit data bus. Its memory is organized into -- banks, each--bit wide. 4. A microprocessor with a 24-bit address bus could access --- MB of memory. 5. A bus cycle is equal to clocking --- periods. 6. If the ready pin is grounded, it will introduce ---state into the bus cycle. 7. The PCLK output of the 8284A is --- MHz if the crystal frequency is 14 MHz. 8. The RES input to the 8284A is placed at a logic --- level in order to reset the 8086/8088. 9. The 8086 and 8088 processor can be operated in either the minimum or maximum mode. The maximum mode is so named because the maximum mode (a) Let you execute the maximum number of instructions. (b) Let you address the maximum number of memory locations (IMB) (c) Requires more support hardware than the minimum mode. (d) All of the above. 10. The 8086/8088 use a multiplexed address and data bus because (a) 40 pins is a good size for the IC. (b) Multiplexing is supported by 8085 Microprocessor. (c) Multiplexing reduces the number of lines between the microprocessor and the auxiliary Ics. (d) All of the above. The DEN signal is active ------- output from 8288 bus controller. 12. An 8086/8088 microprocessor requires -------- and ------- chips is maximum mode systems configuration. 13.The 8288 bus controller must be used in the ------ mode to provide ------ signals to the memory and I/O. 14. 8088 microprocessor does not required latch for a A8 A15 lines because ---------. 15. SSO of 8088 microprocessor indicates -------. 1.