3/14/2014

FPGA Serial UART Receiver

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FPGA Serial UART Receiver

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FPGA Serial UART Receiver

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Serial communication is a very useful feature in any project that you like to design. Serial means that you can send multiple bits of data over a SINGLE line. That's right! 1 line can send many bits. This reduces the complexity of a desig and frees up pins that you might need for other things. Why is this useful? If you want to communicate to a computer, another FPGA, another device like a microcontroller or even interface to a digital to analog converter. If you like to view the Transmitter tutorial, you can find it by HERE.

http://www.ece301.com/fpga-projects/57-uart-rxd.html

3/14/2014

FPGA Serial UART Receiver

Design Needs
1. Clock divider - this is just a counter that sends bit by bit at a specified speed ( baud rate). On the receiver side, this data will be sampled to make sure that the transmission was received without error. I decided to use a speed three times that of the transmitter for sampling. 2. Shift register - The data we plan to receive over a line is stored in bit-registers on the FPGA. A bit register can be composed of many bits. Because we only want to use 1 output of the FPGA to send all the data, we need to have a special register that can shift the data each time one bit is received over the single line, so that the next one in line bei transmitted can be received and no information loss happens. We need to know how many bits at a time we are receiving serially. If you followed my transmitter tutorial which works as the transmitter for this receiver tutorial, then ou shift register size will have a start bit, data bits, end bit. In this case it will be 1 data bit, 8 data bits, 1 parity bit, and 1 e bit with a total of 11 bits.

Design Solution
First, lets figure out what pin inputs and outputs we need. In this case, I will use 8 switches to input 8 bit data that will sent across the serial communication output. A clock is a must to connect to the internal FPGA clock. A reset input is recommended in case somehow the code gets stuck. A transmit button for when we are ready to transmit our data, a finally we need one output pin. Lets see the block diagram,

Figure 1 Ok, for our state diagram, we know a few things already. We know that we need a clock to run some kind of counter, a we know that our receiver will always need to be in two different states, IDLE and RECEIVING. State machines will always have two imporant registers, state and nextstate. These make sure that you can transitio between states in your case statement. More on this later. Next we have to choose the speed we want to receive the data at. This is called the baud rate. This baud rate needs to be known both by the receiver and transmitter ahead of time so they can communicate. There are many baud rates an I will let you look them up if you want to, but I will use 9600, which is pretty standard. To have this baud rate, a counter needed: counter = FPGA clock speed / (baud rate*sample_rate); In this example I have an FPGA clock speed of 50MHz, therefore my counter is 1736 for the baud rate of 9600. Recap registers - state, nextstate, counter, shiftregister. inputs - data, clk, reset RxD. output - [7:0] RxData. Is there anything more needed? Yes, more registers, Why? We have a counter that will count up to a certain number each time the 50MHz clock ticks, after it reaches that number will do something. From above, the counter is 1736 for a baud rate of 9600. We have 11 bits, so we need a bitcounter register to count when we reach the number of bits sent so we can stop transmission. We also need a samplecounter register, something we do not have in the transmitter. This ensures that sampling goes smoothly.

Code:

http://www.ece301.com/fpga-projects/57-uart-rxd.html