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I. Blocking vs. Nonblocking Assignments

Verilog supports two types of assignments within always blocks, with subtly different behaviors.

Blocking assignment: evaluation and assignment are immediate

always @ (a or b or c) begin

x

=

a

| b;

1. Evaluate a | b, assign result to x

y

=

a

^ b

^ c;

2. Evaluate a^b^c, assign result to y

z

= b & ~c;

 

3. Evaluate b&(~c), assign result to z

end

Nonblocking assignment: all assignments deferred until all right-hand sides have been evaluated (end of simulation timestep)

always @ (a or b or c) begin

x

<=

a

| b;

1. Evaluate a | b but defer assignment of x

y

<=

a

^ b

^

c;

2. Evaluate a^b^c but defer assignment of y

z

<=

b

& ~c;

 

3. Evaluate b&(~c) but defer assignment of z

   

end

   

4. Assign x, y, and z with their new values

 

Sometimes, as above, both produce the same result. Sometimes, not!

Why two ways of assigning values?

Conceptual need for two kinds of assignment (in always blocks):

a a x b y b c Blocking: a = b x = a &
a
a
x
b
y
b
c
Blocking:
a = b
x
= a & b
Evaluation and assignment
are immediate
b = a
y
=
x
|
c
Non-Blocking:
a <=
b
<=
Assignment is postponed until
all r.h.s. evaluations are done
b <=
a
y x
x a & b
c
<=
|
When to use:
Sequential
Combinational
( only in always blocks! )
Circuits
Circuits
Assignment Styles for Sequential Logic Flip-Flop Based Digital Delay Line q1 q2 in D Q
Assignment Styles for Sequential Logic
Flip-Flop Based
Digital Delay
Line
q1
q2
in
D
Q
D
Q
D
Q
out
clk

Will nonblocking and blocking assignments both produce the desired result?

module nonblocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin

q1 <= in; q2 <= q1; out <= q2;

end

endmodule

module blocking(in, clk, out); input in, clk; output out; reg q1, q2, out; always @ (posedge clk) begin

q1 = in; q2 = q1; out = q2;

end

endmodule

Use Nonblocking for Sequential Logic

always @ (posedge clk) begin

q1 <= in; q2 <= q1; out <= q2;

end

“At each rising clock edge, q1, q2, and out simultaneously receive the old values of in, q1, and q2.”

q1 q2 in D Q D Q D Q
q1
q2
in
D
Q
D
Q
D
Q

clk

out

always @ (posedge clk) begin q1 = in; q2 = q1; out = q2; end
always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end
“At each rising clock edge, q1 = in.
After that, q2 = q1 = in; After that,
out = q2 = q1 = in; Finally out = in.”
q1
q2
in
out
D
Q
clk

Blocking assignments do not reflect the intrinsic behavior of multi-stage sequential logic

Guideline: use nonblocking assignments for sequential always blocks

Use Blocking for Combinational Logic

Blocking Behavior

 

a b c

x y

(Given) Initial Condition

1

1 0

1 1

a

changes;

0 1 0

1 1

always block triggered

x = a & b;

0 1 0

0 1

y =

x

| c;

0

1 0

0 0

always @ (a or b or c)

begin

 
 

x

y

= a & b; =

| c;

x

end

 

a

b

c

x y = a & b; = | c; x end   a b c x

x

y

Nonblocking Behavior a b c x y Deferred (Given) Initial Condition 1 1 0 1
Nonblocking Behavior
a b c
x y
Deferred
(Given) Initial Condition
1
1 0
1 1
a changes;
0 1 0
1 1
always block triggered
always @ (a or b or c)
begin
x <= a & b;
0 1 0
1 1
x<=0
x
<= a & b;
y
<= x | c;
y <= x | c;
0
1 0
1 1
x<=0, y<=1
end
Assignment completion
0
1 0
0 1

Nonblocking assignments do not reflect the intrinsic behavior of multi-stage combinational logic

While nonblocking assignments can be hacked to simulate correctly (expand the sensitivity list), it’s not elegant

Guideline: use blocking assignments for combinational always blocks

II. Single-clock Synchronous Circuits

We’ll use Flip Flops and Registers – groups of FFs sharing a clock input – in a highly constrained way to build digital systems.

Single-clock Synchronous Discipline:

No combinational cycles

Single clock signal shared among all clocked devices

Only care about value of combinational circuits just before rising edge of clock

Period greater than every combinational delay

Change saved state after noise- inducing logic transitions have stopped!

delay • Change saved state after noise- inducing logic transitions have stopped! 6.111 Fall 2007 Lecture

Clocked circuit for on/off button

module onoff(clk,button,light);

input clk,button; output light; reg light; always @ (posedge clk) begin if (button) light <=
input clk,button;
output light;
reg light;
always @ (posedge clk)
begin
if (button) light <= ~light;
end
Does this work
with a 1Mhz
CLK?
endmodule
0
D
1
Q
LE
D
Q
LIGHT
BUTTON
CLK
CLK
SINGLE GLOBAL CLOCK
LOAD-ENABLED REGISTER

Asynchronous Inputs in Sequential Systems

What about external signals?

Sequential System Clock
Sequential System
Clock

Can’t guarantee setup and hold times will be met!

When an asynchronous signal causes a setup/hold violation

I II Q D Clock Transition is missed on first clock cycle, but caught on
I
II
Q
D
Clock
Transition is missed on
first clock cycle, but
caught on next clock
cycle.
Transition is caught on
first clock cycle.

III

?
?

Output is metastable for an indeterminate amount of time.

Q: Which cases are problematic?

Asynchronous Inputs in Sequential Systems

All of them can be, if more than one happens simultaneously within the same circuit.

Idea: ensure that external signals directly feed exactly one flip-flop

Sequential System D Q Clock
Sequential System
D
Q
Clock
Clocked Synchronous System Async Q0 D Q Input Clock Q1 D Q Clock
Clocked
Synchronous
System
Async
Q0
D
Q
Input
Clock
Q1
D
Q
Clock

This prevents the possibility of I and II occurring in different places in the circuit, but what about metastability?

Handling Metastability

Preventing metastability turns out to be an impossible problem

High gain of digital devices makes it likely that metastable conditions will resolve themselves quickly

Solution to metastability: allow time for signals to stabilize

Can be

metastable

right after

sampling

Very unlikely to be metastable for >1 clock cycle

Very unlikely to be metastable for >1 clock cycle Extremely unlikely to be metastable for >2

Extremely unlikely to be metastable for >2 clock cycle

Extremely unlikely to be metastable for >2 clock cycle Complicated Sequential Logic System D Q D
Extremely unlikely to be metastable for >2 clock cycle Complicated Sequential Logic System D Q D

Complicated Sequential Logic System

Complicated Sequential Logic System
Complicated Sequential Logic System

D

Q

Q
D Q D Q D Q

D

Q

Q
D Q D Q D Q

D

Q

Q
D Q D Q D Q

Clock

Logic System D Q D Q D Q Clock How many registers are necessary? • Depends
Logic System D Q D Q D Q Clock How many registers are necessary? • Depends

How many registers are necessary?

Depends on many design parameters(clock speed, device speeds, …)

In 6.111, a pair of synchronization registers is sufficient

III. Finite State Machines

Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized “states” of operation

At each clock edge, combinational logic computes outputs and

next state as a function of inputs and present state

Combinational Logic D Q Flip- Flops
Combinational
Logic
D
Q Flip-
Flops
and present state Combinational Logic D Q Flip- Flops n inputs + present outputs + next

n

inputs

+

present

outputs

+

next

state

state

n

CLK

Example 1: Light Switch

State transition diagram

BUTTON=0

Logic diagram

BUTTON=1 LIGHT LIGHT = 0 = 1 BUTTON=1 Combinational logic
BUTTON=1
LIGHT
LIGHT
= 0
= 1
BUTTON=1
Combinational logic

6.111 Fall 2007

BUTTON

CLK

0 1 D Q Register
0
1
D
Q
Register

BUTTON=0

LIGHT

Lecture 6, Slide 12

Example 2: 4-bit Counter

Logic diagram

Verilog

4 4 +1 clk
4
4
+1
clk

# 4-bit counter module counter(clk, count); input clk; output [3:0] count; reg [3:0] count;

count

always @ (posedge clk) begin count <= count+1; end endmodule

Example 2: 4-bit Counter

Logic diagram

Verilog

4 4 +1 1 0 enb clk
4
4
+1
1
0
enb
clk

count

# 4-bit counter with enable module counter(clk,enb,count); input clk,enb; output [3:0] count; reg [3:0] count;

Could I use the following instead? if (enb) count <= count+1;

I use the following instead? if (enb) count <= count+1; always @ ( posedge clk) begin

always @ (posedge clk) begin count <= enb ? count+1 : count; end endmodule

Example 2: 4-bit Counter

Logic diagram

Verilog

0 4 4 1 +1 1 0 0 enb clr clk
0
4
4
1
+1
1
0
0
enb
clr
clk

count

# 4-bit counter with enable and synchronous clear

module counter(clk,enb,clr,count); input clk,enb,clr; output [3:0] count; reg [3:0] count;

Isn’t this a lot like Exercise 1 in Lab 2?

[3:0] count; Isn’t this a lot like Exercise 1 in Lab 2? always @ ( posedge

always @ (posedge clk) begin count <= clr ? 4’b0 : (enb ? count+1 : count); end endmodule

Two Types of FSMs

Moore and Mealy FSMs : different output generation

Moore FSM:

next state S + D Q Comb. Flip- Comb. n Logic Logic n present state
next
state
S +
D
Q
Comb.
Flip-
Comb.
n
Logic
Logic
n
present state S
Q Comb. Flip- Comb. n Logic Logic n present state S inputs x 0 x n

inputs

x

0

x

n

Mealy FSM:

direct combinational path! S + Comb. D Q Comb. Flip- Logic n Logic Flops CLK
direct combinational path!
S
+
Comb.
D
Q
Comb.
Flip-
Logic
n
Logic
Flops
CLK
n
S

inputs

x

0

x

n

outputs y k = f k (S)

outputs y k = f k (S, x 0

x

n

)

Design Example: Level-to-Pulse

A level-to-pulse converter produces a single-cycle pulse each time its input goes high.

It’s a synchronous rising-edge detector.

Sample uses:

Buttons and switches pressed by humans for arbitrary periods of time

Single-cycle enable signals for counters

of time – Single-cycle enable signals for counters Whenever input L goes from low to high

Whenever input L goes from low to high

L Level to Pulse Converter P CLK
L
Level to
Pulse
Converter
P
CLK
goes from low to high L Level to Pulse Converter P CLK output P produces a
goes from low to high L Level to Pulse Converter P CLK output P produces a

output

P produces a

single pulse, one clock

period wide.

Step 1: State Transition Diagram

Block diagram of desired system:

Synchronizer Edge Detector Level to unsynchronized user input D Q D Q L Pulse P
Synchronizer
Edge Detector
Level to
unsynchronized
user input
D
Q
D
Q
L
Pulse
P
FSM
CLK

State transition diagram is a useful FSM representation and design aid:

“if L=1 at the clock edge, then jump to state 01.”

L=1 L=1 L=1 00 11 11 01 Low input, Waiting for rise Edge Detected! High
L=1 L=1
L=1
00
11 11
01
Low input,
Waiting for rise
Edge Detected!
High input,
Waiting for fall
P = 1
P = 0
P P
= = 0 0
L=0
L=0

Binary values of states

L=0 L=0
L=0 L=0

L=1

This is the output that results from this state. (Moore or Mealy?)

“if L=0 at the clock edge, then stay in state 00.”

Step 2: Logic Derivation

Transition diagram is readily converted to a state transition table (just a truth table)

L=1 L=1 L=0 11 L=1 00 01 Low input, Waiting for rise Edge Detected! High
L=1
L=1
L=0
11 L=1
00
01
Low input,
Waiting for rise
Edge Detected!
High input,
Waiting for fall
P = 1
P = 0
P = 0
L=0
L=0

Curren

   

Next

   

t State

In

State

Out

S

1

S

0

L

S

1

+

S

0

+

P

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

1

1

1

1

1

0

0 0

0

 

1

1

1

1 0

1

Combinational logic may be derived using Karnaugh maps

for S 1 + : S 1 S 0 L 00 01 11 10 0
for S 1 + :
S
1 S 0
L
00
01
11
10
0 0
0
0
X
S
+
1 0
1
1
X
L
P
Comb.
D
Flip-
Q
Comb.
for P:
n
S
for S 0 + :
Logic
Flops
Logic
1
S
S
CLK
0
1
1 S 0
0
00
01
11
10
n
L
0
0
X
0 0
0
0
X
S
1
1
0
P = S 1 S 0
1 1
1
1
X
S 1 + = LS 0
S 0 + = L

Moore Level-to-Pulse Converter

inputs

x

0

x

n

next state S + D Q Comb. Flip- Comb. n Logic Logic n present state
next
state
S +
D
Q
Comb.
Flip-
Comb.
n
Logic
Logic
n
present state S
S 1 + = LS 0
S 0 + = L
P = S 1 S 0

outputs y k = f k (S)

Moore FSM circuit implementation of level-to-pulse converter:

L

S + S 0 0 D Q CLK Q D Q S + S 1
S
+
S
0
0
D
Q
CLK
Q
D
Q
S
+
S
1
1
Q

P

Design of a Mealy Level-to-Pulse

direct combinational path! S + Comb. Comb. D Q Flip- Logic n Logic Flops CLK
direct combinational path!
S
+
Comb.
Comb.
D
Q
Flip-
Logic
n
Logic
Flops
CLK
n
S

Since outputs are determined by state and inputs, Mealy FSMs may need fewer states than Moore FSM implementations

1. When L=1 and S=0, this output is asserted immediately and until the state transition occurs (or L changes).

L 1 2 P Clock State
L
1
2
P
Clock
State

Output transitions immediately. State transitions at the clock edge.

L=1 | P=1 0 1 Input is low Input is high L=0 | P=0 L=1
L=1 | P=1
0
1
Input is low
Input is high
L=0 | P=0
L=1 | P=0 P=0

2. While in state S=1 and as long as L remains at 1, this output is asserted.

L=0 | P=0

Mealy Level-to-Pulse Converter

L=1 | P=1 0 1 Input is low Input is high L=0 | P=0 L=0
L=1 | P=1
0
1
Input is low
Input is high
L=0 | P=0
L=0 | P=0
L=1 | P=0

Pres.

 

Next

 

State

In

State

Out

S

L

S

+

P

0

0

0

0

0

1

1

1

1

0

0

0

1

1

1

0

Mealy FSM circuit implementation of level-to-pulse converter:

L

S + S D Q CLK Q S
S +
S
D
Q
CLK
Q
S

P

FSM’s state simply remembers the previous value of L

Circuit benefits from the Mealy FSM’s implicit single- cycle assertion of outputs during state transitions

Moore/Mealy Trade-Offs

How are they different?

Moore: outputs = f( state ) only

Mealy outputs = f( state and input )

Mealy outputs generally occur one cycle earlier than a Moore:

Moore: delayed assertion of P L P Clock State[0]
Moore: delayed assertion of P
L
P
Clock
State[0]
Mealy: immediate assertion of P L P Clock State
Mealy: immediate assertion of P
L
P
Clock
State

Compared to a Moore FSM, a Mealy FSM might

Be more difficult to conceptualize and design

Have fewer states

Light Switch Revisited

BUTTON

CLK

0 1 D Q D Q Q
0
1
D
Q
D
Q
Q

Level-to-Pulse

FSM

Light Switch FSM

LIGHT