CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

Chapter#6 Datapath Subsystems

Datapath definition Addition/ Subtraction Bit wise PG logic (Generate, Propagate and Kill) Half adder and Full adder review with PG logic Carry propagation example Carry Ripple Adder Group PG logic Carry Skip/Bypass Adder Carry Select Adder Carry Look Ahead Adder Adder Variants v Subtraction v Multiple Input Addition PRSG (LFSR Linear Feedback Shift Register) One/ Zero detectors Comparators Equality Comparator Magnitude Comparator

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

Datapath Definition
A collection of functional units such as ALUs or multipliers is called as datapath. It consists of an interconnection of basic combinational functions, such as arithmetic operators (Addition, subtraction ) or logic (AND, OR, and XOR, comparison, shifts etc).

Addition/ Subtraction
PG Logic
To get rid of carry propagate adders like carry ripple adder in which carry must ripple through all stages to calculate Cout, and to speed up the process of addition, we use PG Logic. The PG logic is specifically used to predict the Cout of any intermediate stage so that the next high order bits or group of bits may be added simultaneously.

Bitwise PG Logic
Generate: (G): The adder generates (G) a carry i.e. Cout=1 when Cout is true independent of Cin. G = AB Propagate: (P): An adder propagates (P) a carry i.e. Cout = Cin when exactly one input is high. P = A B Kill: (K): The adder kills (K) a carry i.e. Cout = 0 independent of Cin. K = A B = (A + B)

Half adder and Full adder

Figure (a) : Half Adder A 0 0 1 1 B 0 1 0 1

Figure (b) : Full Adder Cout 0 0 0 1 S 0 1 1 0

Truth Table for Half Adder S = A B Cout = AB

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

G 0 0 0 0 0 0 1 1

P 0 0 1 1 1 1 0 0

K 1 1 0 0 0 0 0 0

Cout 0 0 0 1 0 1 1 1

S 0 1 1 0 1 0 0 1

Truth Table for Full Adder S = A B Cin Cout = AB + BCin + ACin Assume that we have not calculated Cout column in the truth table for Full adder by using above logic expression for Cout, instead we have calculated it by observing G,P and K columns. That is if K = 1 then Cout =0 if P = 1 then Cout =Cin and if G = 1 then Cout=1. At this level PG logic seems to be time consuming because of calculating PGK signals instead of calculating Cout directly. But when number of bits or group of bits in adder input increases, the understood advantages of PG logic may also increase. This is because of the fact that none of the PGK signals depend on Cin. At any stage Cout can then be calculated by just observing the bit values of a and b instead of long time waiting for Cout to be generated from previous low order bits or group of bits. S = A B Cin S = P Cin because P = A B

Cout = AB + BCin + ACin Cout = AB + Cin ( B + A ) Or Cout = (AB + Cin ( B + A )) using De-Morgans Law Or it can be written as Cout = MAJ [A, B, Cin] where, Majority Function returns 1 if it exists in majority among the input bits combination of A, B and Cin otherwise it returns 0. This can easily be observed by viewing the column Cout for inputs A,B and Cin.

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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CS-403 VLSI Design Handout_7

Course Teacher: GUL MUNIR UJJAN

BE (CIS) Session-2009

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