SV COLLEGE OF ENGINEERING DEPARTMENT OF ECE III B.TECH (2012-13) I SEM SUB: DICA STAFF: UNIT-I 1.

The logic level representing State 0 in CMOS logic [ ] a) 0-1.5V b) 3.5-5V c) 0-0.8V d) 2.0-5.0V 2. When the current flows from the power supply out of the device o/p and through the load to ground is______ [ ] a) Sourcing current b) Sinking current c) conventional current d) electron current 3. In CMOS inverter circuit the pull down transistor is _______ [ ] a) Depletion mode PMOS b) Enhancement mode PMOS c) Depletion mode NMOS d) Enhancement mode NMOS 4. When Vin of 0.0V is applied to CMOS circuit, PMOS is______ [ ] NMOS is _______ a) off, on b) off, off c) on, off d) on, on 5. The digital logic family which has minimum power dissipation is [ ] a) TTL b) RTL c) DTL d) CMOS 6. The basic gate in TTL is _________ a) AND b) OR c) NAND d) NOR 7. MOS Technology is more suited for LSI because_________ [ a) more MOSFETs can be fabricated in the same chip size b) LSI are more reliable c) LSI have longer life d) LSI are cheaper 8. Which of the following is the fastest logic [ a) TTL b) ECL c) CMOS d) LSI 9. Small scale integration abbreviated SSI, refers to fewer than ________ [ a) 24 gates per chip b) 10 gates per chip c) 12 gates per chip d) 36 gates per chip 10. The fan out of a logic gate is __________ [ a) the no. of subsequent ckts which the gate can drive b) The no.of i/ps divided by the number of o/ps c) The no.of connections to the package d) None of the above 11. The range of VIH in CMOS is________ 12. In TWO i/p CMOS NAND gate, no. of NMOS transistor used are_______ 13. The expression for dynamic power dissipation in CMOS circuits is_________ 14. More the supply voltage_____________is the power consumption in CMOS

] ]

15 MOSFET is _________________ controlled device 16.TTL has excellent noise margin (True/False) 17.CMOS has low power dissipation (True/False) 18. (True/False) 19. In CMOS loading effects output voltage may increase beyond VOC max 20. In CMOS loading effects propagation delay to the o/p may decrease beyond specification

(True/False) (True/False)

UNIT-II 1.Basically the single CE transistor acts as _______ logic circuit. [ a) multiplexer b) inverter c) differentiator d) decoder 2. More power consumption present from following family [ a) 74LS b) 74AS c) 74ALS d) 74S 3. . In digital ICs, Schottky transistors are preferred over normal transistors because of their (A) Lower Propagation delay. (B) Higher Propagation delay. (C) Lower Power dissipation. (D) Higher Power dissipation. 4. In digital ICs, Schottky transistors are preferred over normal transistors because of their [ a) Lower Propagation delay. b) Higher Propagation delay. c) Lower Power dissipation. d) Higher Power dissipation. 5. Fastest logic family from the following [ a) TTL b) Schottky TTL c) RTL d) DTL 6. No.of 7400 ICs required to realize exclusive of gate is ________ [ a) 1 b)2 c)3 d)4 7.. which of the following logic families exhibit lowest power dissipation per gate_____ [ a)TTL b) Lensee-ECL c) CMOS d) 8nsee-ECL 8. current mode logic (CML) is the same as _______ [ a) TTl b) ECL c) CMOS d) I L 9. The ECL can be used to switch frequencies as high as_____ [ a) 1Mhz b)100 Mhz c) 500 Mhz d) 1GHz 10. 7400 series devices can be safely operated in temperature range_________ [ a) 0 to 20c b) 0 to 30c c) 0 to 70c d) 0 to 100c 11. noise margin for high level (logic1)is--------------12. Junction is formed between metal & intrinsic semiconductor that device is Called _____ 13. Speed power product units is________ 14. Dc noise margin of 74LS TTL family in low state is________ 15. The overall fanout s of low state and high state fanout in LS-TTL is_______

] ]

] ] ] ] ]

16. ECL family has shortest delay (True/False) 17. TTL o/p stage is called TOTEMPOLE (True/False) 18. Cut in voltage for schoHky diode is 0.4v (True/False) 19. The storage time of transistor can be reduced by schotkey diode(True/False) 20. In schotkey diode Junction is formed between metal & intrinsic semiconductor (True/False) UNIT-III 1. A VHDL ________ allows you to define and apply i/ps to your desired and to observe its o/ps. [ ] a) Synthesis b) timing verification c) compilation d) simulation 2. . In backend design flow after synthesis next stage is [ ] a) coding b) fitting/Place & route c) timing verification d) compilation 3)A VHDL _________ is simply a declaration of module i/ps & o/ps. [ ] a) architecture b) entity c) data flow d) behavioral model 4) From the following find odd a) AND b) OR [ c) NAND d) abs ]

5. .Do nothing represents _________ statements [ ] a) exit b) null c) wait d) for 6. Identifiers are ______types [ ] a) 2 b) 3 c) 4 d) 5 7. A sequence of characters written between two backslashes is called_____ [ ] a) file b) basic identifier c) external identifier d) data 8. 7 mod 4 this belongs to_____operator [ ] a) Adding operators b) miscellaneous operator c) multiplying operators d) shift operators 9. . ______ describes the external view of the entity [ ] a) Architecture body (b) Entity declaration c) Package body (d) package declaration 10. _____ is used to create a configuration for an entity [ ] a) Architecture body (b) Entity declaration c) Configuration declaration (d) package declaration 11. Write the syntax for signal declaration________ 12. In VHDL language comments are begined with________ 13. Write the full form of VHDL_______ 14. the place where VHDL compiler stores information about a particular design project known as ---------15. process is ---------statement 16.& is used as concatenation operator (True/False)

17. Port is used in architecture 18.vhdl is text based language 19.Synthesis is front end step 20.VHDL is case insensitive

(True/False) (True/False) (True/False) (True/False) UNIT-IV

1.Keyword others used in_______ syntax [ ] a) with select b) if else c) if else if else d) process 2.. The following statement is not a sequential statement [ ] a) case b) for loop c) with select d) wait 3. .______ statements are preferred in the behavioral model [ ] a) concurrent b) sequential c) constant d) exit 4. One of the following statements is incorrect [ ] a) wait on A,B, C; b) wait for ons; c) wait until clock=1 d) wait until A, B, C; 5. One of the following is used assignment operator [ ] a) < b) <= c) >= d) 1= 6. ________ statement selects one of the branches for execution based on the value [ ] Of the expression. a) Case b) Null c) Loop d) Wait 7. _________ statement provides an alternate way to suspend the execution of a [ ] Process. a) variable assignment statement b) signal assignment statement c) wait statement d) IF statement 8. _______ Statement selects different values for a target signal based on the value [ ] Of a select expression. a) Conditional signal assignment b) selected signal assignment c) Both a&b d) none. 9. _______ Statement selects different values for a target signal based on the specified, possibly,different,conditions. [ ] a) Conditional signal assignment b) selected signal assignment c) Both a&b d) none. 10.The following statement is sequential statement [ ] a)null b)report c)wait d)all 11.Exit is ----------statement. 12. type STD_LOGIC_VECTOR is array of -----13.the syntax for package use in VHDl----------14. Write an example of a component instantiation statement________ 15. Portmap is used in_______ model 16. VHDL is almost object-oriented language (True/False) 17. Generic constants are declared in entity (True/False)

18. Entity a declaration of a modules inputs and outputs 19.Report statement is used to display message 20.Always process statement must be associated with sensitive list

(True/False) (True/False) (True/False)

UNIT-V 1. For 74 x 139 dual 2 to 4 decoder, 011 input given______ o/p [ ] a) 0111 b) 1011 c) 1111 d) 1100 2. 74 x 138 has [ ] a) three enable inputs b) two enable inputs c) four enable i/ps d) one enable i/p 3. A seven segment decoder has ________ as its i/p code [ ] a) 4-bit BCD b) 6 bit excess c) 3 bit octal d) 3 bit hex n 4. The 1 out of 2 coded o/ps of n bit binary decoder used to control a set of [ ] n n-1 n+1 a) 2 devices b) 2 devices c)2 devices d) 2n devices 5. The IDLE o/p in generic 8 i/p priority encoder is asserted if________ are asserted. [ ] a) no i/ps b) I1, I4 c) I2, I6 d) I4, I5 6.IC 74x148 is -------------[ ] a)decoder b)encoder c)priority encoder d)buffer 7.------------ gate is used for parity generation [ ] a)AND b)OR C)NOR D)XOR 8.Decoder has ---------inputs and -----------outputs [ ] n n n n a)1,2 b)2 ,1 c)n, 2 d) 2 ,n 9.16x1 MUX has -------select lines [ ] a)1 b)2 c)3 d)4 10.In carry look ahead adder expression for carry propagate a)xi+yi b)xi*yi c)xi-yi d)none 11.IC 74x 151 is 16x1 mux(True/False) 12.IC 74x 245 is three state buffer(True/False) 13.IC74x 139 is dual 2x4 decoder(True/False) 14..74 x 148 o/ps are active low (True/False) 15. 74 x 153 is 4 input, 2 bit multiplexer (True/False) 16. Draw the symbol of non-inverting tristate buffer with active low enable______ 17. 9 bit parity generator IC number is________ 18. IC 74 x 86 is________ 19.Three states present with Tri_ State buffer are ---20.Transceiver is used in between---------------UNIT-VI 1.The following IC is 4 bit comparator [ ]

a)74x83 b)74x89 c)74x85 d)74x283 2.In IC74x181 operations are selected basing on -----pins a)only M b)only s0,s1,s2,s3 c)both d)M,s0,s1,s2,s3,ao,a1,a2,a3 3)Barrel shifter specify a)direction of shift b) type of shift c)amount of shift d)all 4)4 bit universal shift register is available as a)IC 74x183 b) IC74X194 c)IC74x184 d) IC74x173 5)Comparator can be designed using -----gate a)and b)nand c)nor d)xor 6)______ specify the direction of shift, type of shift and amount of shift a) barrel shifter c) sequential shifter b) carry save shifter d) group ripple shift [ ] [ ] [ ] [ ] [ ] [ ]

7) ________ is 8 bit comparator and has no cascading i/ps a) 74 x 138 d) 74 x 153 b) 74 x 85

c) 74 x 682 8) AEQ out in 74 x 85 is equal to a) (A=B).AEQBIN c) (A>B)+(A=B).AGTBIN

[ b) (A<B)+(A=B).ALTBIN d) (A>B)+(A=B) [

9). A combinational fixed point to floating point encoder consists of_______ a)

one 74 x 148, two 74 x154, 74 x 251 one 74 x 148, two 74 x154, 74 x 251 b) one 74 x 148,

three 74 x 151 c) two 74 x 154, 74 x 251 10. The following IC is a 4-bit ALU a) 74381 c) 74283 b) 74151 d) 74161 d) 74 x 280, two 74 x 138. [ ]

11.Expression for ALTBOUT in 74x85 is ----------12.IC74x181 is -------------13. . Expression for PGTQ for 24-bit comparator is_______ 14.Expression for AGT Bout in 74x 85 is_______ 15.IC 74682 is__________ 16.IC74x181 M input selects between arithmetic and logic operation (true/false)

17.Universal shift register performs circular shift(true/false) 18.sequential multiplier use single adder and register to accumulate partial product(true/false) 19. 74 x 682 does not provide lessthan output (True/ False) 20.A combinational circuit is not possible to design to count no. of ones in a number ( True/False)

UNIT-VII 1.Flipflop is used to store a)byte b)word c)bit d)nibble [ d)diode [ b)asynchronous 4_bit counter d) Asynchronous 4_bit binary counter [ ] ] ] 2)First generated sequential PLDs use ---------logic a)RTL 3)IC74X163 IS a)synchronous 4_bit counter c) synchronous 4_bit binary counter b)TTL c)DTL [ ]

4) In IC 74x194 ------------operation is performed when select input S1,S0=1,1 a) right shift 5)Counters are also known as a)frequency adder c) frequency divider
1 1

b)hold

c) load

d) left shift [ ]

b) frequency subtractor d) frequency multiplier [

1 1

6.TFF with enable characteristic equation is_______ a)Q* =EN.Q +EN .Q c) Q*=EN.Q1+EN1.Q+EN.D b) Q*=EN.Q+EN .Q d) Q*=EN.D+EN1.Q

7. ________ contains 4-bit register with a common clock and a synchronous clear i/p a) 74 x 112 c) 74 x 370 b) 74 x 375 d) 74 x 175

[]

8. Little rectangular symbols inside the buffer symbols indicate______ a) Hysterisis c) amplification b) inverter d) inductance

9. ________ is first generation sequential PLD

a) PAL 20L10 c) PAL 16R8 10.LFSR is also known as a) maximum length sequence generator c) shift circular register

b) PAL20L8 d) GAL 16 V8R [ b) minimum length sequence generator d) Johnson counter ]

11.The characteristic equation of 74LS74 is _________ 12.IC 74LS109 is ___________ 13.IC74 x 375 is________ 14.Latches use -------------triggering 15.Shift register combined with combination logic to form state machine is called ------16.Flipflops use both edge triggering and level triggering (true/false) 17.Design of synchronous counter is easier than asynchronous counter(true/false) 18.PAL has programmable AND and OR gates(true/false) 19.74 x 160 is a modulo -10 counter (True/False)

20. IC 74 x 163 is a synchronous 4-bit binary counter with active low load and clear i/p (True/False

UNIT-VIII

1.128X4 ROM has -------inputs and --------outputs a)7,4 b)7,2 c)128,2 d)none

2.In ROM output line of decoder is known as a) bitline b) word line c) both d)None

3.PROM uses _________logic. a)Bipolar b) CMOS c)PMOS d)NMOS

4.Output Hold time is amount of time output is valid after change in a) Address input. b) Output Enable c) Chip Select d) All the above.

5.Memory locations in SRAM behave more like a) D-latch b)edge triggered d flipflop c)latch d)flipflop

6. A 1Mx1ROM could be built with

a) 10 to 1024 decoder and 1024 i/p multiplexer b) 3 to 8 decoder and 16-bit multiplexer

c) floating source MOS 7. EEPROM will have a) floating source MOS

d) 3 to 10 decoder and 20-input multiplexer [ b) floating gate MOS d) floating body MOS [ b) QAM d) PWM [ ] ] ]

c) floating drain MOS 8. _________ is the 8-bit companded encoding a) law PCM c) DPCM

9. EEPROM (NMOS technology) read cycle is _______ a) 500-1500 ns c) 250-300ns b) 250-1200ms d) 50-200ns [ ]

10. ________ is used to reduce the decoder size in ROM a) 2-D decoding c) 5-D decoding 11.pull up resistor in CPLD is used for -------12.programmable logic blocks of FPGA are known as -------13. SRAM cell contains_________ 14. PROM (bipolar technology) read cycle is________ 15. HM6264 is_________ 16.SRAM has more package density (T/F) 17.ROM is non volatile (T/F) 18.CPLD has product term allocators(T/F) 19. SRAM requires periodic refreshment of memory 20. b) 1-D decoding d) 4-D decoding

(True/ False)

AA

is the time required to get the stable data after a change in address (True/ False)