Page 1 of 1

Contents
Abstract
Chapter 1: Introduction
1.1 A Brief Overview of VCO based ADC.2
1.2 Benefits of a VCO-based ADC Architecture...2
1.3 Prior VCO-Based ADC Architectures.3
1.4 Implemented VCO based ADC Architecture.........4
Chapter 2: Asynchronous Sigma delta VCO ADC
2.1 ASDM ...6
2.2 Differential VCO .6
2.3 Phase interpolation.........................................................7
2.4 Sampler..........................................................................................................8
2.5 XOR....8
2.6 Adder8
Chapter 3: Design of ADC
3.1: Introduction.................9
3.2 ASDM ..9
3.3 Op-amp Integrator. .10
3.4 Comparator with hysteresis..........12
3.4 Phase error detection............12
3.6 32 bit Carry Look Ahead adder.14
Chapter 4: Results
Results..16
Conclusion & Future Work.....26
References......27
Page 2 of 2

Chapter 1: Introduction
1.1: A Brief Overview of VCO Based ADC
In todays most advanced electronic systems, the role of high accuracy Analog to Digital
Converters are of great importance. Designing high performance analog to digital converters
(ADCs) in deep sub-micron process is becoming increasingly difficult due to the low supply
voltages of advanced process technologies. Voltage controlled oscillator (VCO) based analog-to-
digital converters (ADCs) have recently become a topic of great interest in the analog & digital
domain [3]. Low value of signal swings and hence, lower value of signal-to-noise ratio is
significant drawbacks for ADCs structures using analog circuit blocks.

A Voltage Controlled Oscillator (VCO) based Analog-to-Digital Converter (ADC) will be
converting an analog voltage to phase domain. The time based signal frequency will be
quantized and processed by digital logics to produce a digital output representing the analog
input voltage. For time based architecture, the resolution will increase with decrease in gate
lengths.

In addition to having a digital design that benefits from technology scaling, the VCO presents a
host of unique signal processing properties that are very attractive in the design of oversampling
converters. A time-based ADC using a voltage-controlled oscillator (VCO) (VCO-based ADC) is
a promising architecture for future low-voltage CMOS processes, since it makes use of digital
circuits and removes the need for accurate analog circuits that need large voltage headroom.
However, certain non-idealities namely, non-linearity in the VCOs voltage-to-frequency
translation have limited the resolution of the VCO-based ADC to less than 8 effective number of
bits (ENOB).

1.2: Benefits of a VCO-based ADC Architecture
While a VCO has a variety of unusual and interesting properties, it has two traits that are
especially attractive and relevant in the design of ADCs. First, the VCO behaves as a CT
voltage-to-phase integrator. As shown in Figure 1(a), the instantaneous VCO output frequency
F
out
(t) is proportional to the applied input voltage I
tunc
(t) according to the voltage-to-frequency
gain K

[Hz/V]. The resulting VCO output phase

out
(t) is proportional to the time integral of the
applied input voltage.

Page 3 of 3


Figure 1.1 the VCO voltage-to-frequency and voltage-to-phase relationships.

Note that as long as the VCO oscillates, the VCO output phase will accumulate endlessly, even
for a DC input. This implies that the VCO behaves as a CT integrator with infinite DC gain.
A second property of interest is the digital nature of a ring-VCOs outputs. Note that while the
VCO output phase and frequency are continuously varying, the VCO output itself toggles
between two discrete levels, I

and gnd, much like a CMOS digital gate .Multi-phase (or

equivalently, multi-bit) quantization can be accomplished by sampling the output phases of a
ring oscillator with an array of D-flip-flops. Note that since the VCO phases are full-swing logic
signals, the quantizer is robust to voltage offsets in the flip-flops. At the same time, only one
VCO edge transitions at a given sampling instant, while the rest of the VCO phases saturate to
either I

or Gnd. Consequently, the quantizer not only is less prone to generate meta-stable
outputs, but also has guaranteed monotonicity without the need of any calibration.
1.3: Prior VCO-based ADC Architecture
The ADC comprises a single-phase output VCO, a counter, and sampling register. As the analog
input signal modulates the VCO frequency via the tuning node, the counter continuously
accumulates the number of transitioning edges during the sample period. At the end of the
period, the resulting count is sampled by a register, the counter reset to zero, and the process
repeated. As can be seen from the figure, the sampled count is proportional to the oscillation
frequency of the VCO, and therefore the input signal level.
In order to improve the resolution of the ADC, a ring-oscillator structure was designed to
generate multiple VCO output phases. Here, each phase output taken from the ring-VCO drives
a counter, producing a total count with higher resolution as compared to the single-phase VCO-
based ADC. There is a serious drawback of this approach, however, is that the counter is more
complicated to design, and typically consumes more power and area in order to meet data and
timing constraints. At the same time, both the designs of VCO-based ADC suffer with error
incurred when counter misses a VCO edge during reset operation.
Page 4 of 4




Figure 1.2 the VCO voltage-to-frequency and voltage-to-phase relationships

Figure 1.3 The VCO voltage-to-frequency and voltage-to-phase relationships

1.4: Implemented VCO-based ADC Architecture
A general open-loop VCO-based ADC consists a VCO and a phase quantizer as a voltage-to-
time converter and a time-to-digital converter. The VCO generates phase proportional to the
integrated input analog voltage and the phase quantizer composed of counters and digital
differentiators converts the phase into digital output. As the nonlinearity of the VCO tuning
curve directly appears at the input of the phase quantizer, the linearity of the VCO-based ADC
cannot exceed the linearity of the VCO and hence limits the input voltage range and reduces the
SNDR. To improve the linearity and resolution, we propose a phase interpolated VCO-based
ADC with foreground calibration shown in Fig. 1.4. The phase interpolator increases the number
of phases of the VCO and hence improves the time resolution of VCO-based ADC. The digital
Page 5 of 5

calibration following the phase quantizer compensates for the nonlinearity introduced by the
VCO [3].

Figure 1.4 Block diagram of the implemented open-loop VCO-based ADC

y(z) =
1
2n
N
ph
(
K
co

s
x(z) (1 z
-1
)E(z))
Where is the K
co
gain of the VCO,
s
is the sampling frequency is the number of phases of the
VCO, x(z) is the input and is the E(z) quantization noise.










Page 6 of 6

Chapter 2: Asynchronous sigma-delta VCO based ADC
After having discussed the various architectures that are available in literature for VCO based
ADCs, this chapter talks about the proposed architecture for Asynchronous sigma-delta VCO
based ADC, with digital calibration employed. The block level schematic of the design is given
first.
2.1 Asynchronous sigma delta modulator (ASDM):
The front end of ADC is Asynchronous Sigma Delta modulator which does the Pulse-Width
Modulation (:
x
(t)) of analog input signal (x(t)). It consists of op-amp based integrator and
hysteresis comparator connected in feedback. The free running frequency (with input=0V) of the
modulator is dependent on loop parameters like op-amp unity gain cut-off frequency and the
comparators hysteresis. The free running frequency of the modulator should be at least 560MHz
(from MATLAB simulations) to achieve the targeted 20MHz bandwidth with SFDR of at least
61dB. The ratio of free running frequency of the modulator to the bandwidth of input signal is
termed as Over-Sampling ratio (OSR) which is 32 in this case. The Loop-filter is designed with
the help of Fully Differential telescopic cascode amplifier which is a single pole system (before
the unity gain frequency) and thus eliminates stability-compensation techniques. The Output
common-mode level of the fully differential feedback is stabilized with the help of common-
mode feedback circuit. The comparators hysteresis is dependent on the process parameters and
the technology. For the OCR to be high, the op-amp unity gain cut-off frequency should be as
high as possible and the hysteresis to be as low as possible.
2.2 Differential VCO:
VCO Comprises of 8 delay cells, with the delay of each of the elements controlled by PWM
voltage (:
x
(t)) coming from ASDM. The Sampling frequency should be at least greater than
twice the VCO free running frequency to avoid the use of counter[1]. The delay of each of the
elements should be made equal to avoid VCOs non-linearity problem. VCO converts the voltage
information coming from ASDM to phase information (
x
(n)).

Figure 2.1 Schematic of phase interpolation with VCO [3]
Page 7 of 7


Figure 2.2 Delay cell of differential VCO [3]
2.3 Phase Interpolation:
Phase interpolation is an attractive method to increase the time resolution. When N differential
delay cells are used to implement a ring VCO, 2N phases become available. If phase
interpolation technique is used, more phases can be obtained while maintaining the frequency. If
the total number of the phases after interpolation is N(int), then the bit resolution of VCO-based
ADC increases as much as log (Nint/Nph )bits.

Figure 2.3 Single ended to differential phase interpolation scheme [3]


Figure 2.4 Implemented phase interpolation [3]
Page 8 of 8


2.4 Sampler:

Figure 2.5 Phase Quantizer with adder

2.5 XOR (Phase error detection):

The phase error detection between the continuous phase and sample phase in feed-forward loop
is done by XOR. XOR in this case is implemented by transmission gate logic in the design. The
quantization noise generated by phase error detector (
q
(n)) is used for further processing in 2
nd

order feed-forward loop.
2.6 Adder:

One 32-bit adders are implemented in the system, one at the output and the other in feed-forward
path of quantization noise shaping. The adder has to add 32-bit parallel data coming to it from
the previous blocks. The adder is implemented in pipelined fashion in Carry-Look Ahead (CLA)
style. The adder at the output will have the 5 digital bits of ADC.






Page 9 of 9

Chapter 3: Design of ADC
3.1 Introduction
After having discussed the key blocks involved in the design of double VCO based ADC, this
chapter talks about the systematic design of each and every block that is involved in the ADC.
The design is carried out in cadence using UMC 180nm CMOS technology.
This section talks about the design of key building blocks involved in the ADC i.e., ASDM
which comprises of Op-amp based integrator and comparator with hysteresis operated in
feedback mode, differential VCO, adders and the digital subtraction blocks that are involved in
the design.
3.2 ASDM
ASDM consists of op-amp based integrator and comparator with hysteresis operated in
feedback mode. The setting up of oscillations and the oscillator free running frequency
dependence on loop parameters are discussed. ASDM designed in cadence environment is shown
in Fig. 3.1.

Fig 3.1: Asynchronous sigma-delta modulator
ASDMs free running oscillator frequency (
c
) is dependent on op-amp integrators unity gain
frequency(
1
), hysteresis of comparator (), output of comparator (:
out_comp
) and the feedback
factor (FB) as follows:

c
=
n
2h
:
out_comp
FB
1
.( 3.1)
where FB represents the feedback term, defined as the ratio between the input signal level
amplitude and the output of hysteresis comparator. This FB is usually kept less than one to
ensure the stability of feedback loop. The term
1,
the integrators unity gain frequency is
defined as
Page 10 of 10

1
=1/ 2nRC...................................................(3.2)
There is no sampling in this type of modulator, therefore the output PWM signal is free of
quantization noise. Theoretically, this ASDM output signal also contains some in-band harmonic
distortion spurs, as has been analyzed in. The worst-case third-harmonic distortion coefficient is
given by ,

3
=
1
0CR
2

M
2
_1-
M
2
2
]
2

n
2
216
.................................(3.3)
where M denotes the modulation depth, defined as the ratio of input signal level amplitude to
the output of comparator. According to the ADCs system requirements, such as SFDR and
SNR, the required value of M and free running frequency of ASDM can be determined. Once a
relatively small M and large OSR are chosen, the harmonic distortion spurs are insignificant and
eventually comes below the noise floor within the signal bandwidth considered. The overall SNR
of ADC improves with increasing
c
and worsens with increasing value of M .
Although the harmonic distortion spurs are important and needs an attention, the value of
M chosen in the design plays a key role in determining the width of clean bands . A larger OSR
not only offers a better distortion performance, it also provides the reflection of less harmonic
spurs into the signal bandwidth after sampling.
3.3 Op-amp based integrator:
To achieve the linearity of integration, the integrator is chosen to be op-amp based. The
op-amp is operated in fully differential mode, to remove common mode noise and to double the
input differential swing, helping in increasing the SNR of overall ADC. There are three
structures to build the integrator with the help of op-amp. They are (1) Two state differential
amplifier (2) Folded cascode and (3) Telescopic cascode . These topologies are briefly reviewed
here.
The two stage fully differential amplifier can provide high gain while the output swing is
one overdrive less than both of the supplies. The only disadvantage with this type of op-amp is
the unity gain cut off frequency, which is most important in op-amp design. This type of
structure will have two poles before UGF, thus requiring special compensation techniques to
ensure proper stability. The Stability can be achieved by using miller compensation technique
with a resistance in series with miller capacitance to cancel the Right hand Zero. However, these
two dominant poles along with zero, cause the relatively low unity gain cut-off frequency for
two-staged op-amp [14].
The folded cascode op-amp has larger input common mode range compared to two
staged one since the available overdrive voltage for the input transistors is large. Comparing with
two staged one, this has lower DC gain and the output swing is only half of the two-staged one,
since a total of two transistors appear on either side at the output. However, this architecture has
Page 11 of 11

significant advantage on unity gain cut off frequency, which is the most important parameter in
the design. As such, this configuration can achieve comparatively high unity gain cut-off
frequency.
The telescopic cascode op-amp has a similar structure with the folded-cascode one. The
cascodes are connected between the power supplies in series with the input transistor pair. The
gain is almost same as folded-cascode one and little less than the two staged one. Comparing
with the other two architectures, the telescopic cascode has the lowest input common mode range
and the output swing. The output swing is comparatively lower than the folded-cascode since an
additional tail transistors overdrive will come in series with the other transistors. Similar to
folded-cascode, the telescopic cascode has only one dominant pole and the unity-gain cut off
frequency is high compared to two staged one. In the sense of overall power consumption,
telescopic cascode has the lowest, since only one current branch exists in the architecture.
As the minimum gain required for the op-amp integrator is around 50dB, with very high unity
gain cut-off frequency (around 1GHz), consuming minimum power, and telescopic cascode is
chosen for the design. The compensation is not needed in this case as the cascode structure will
have single pole before UGF, ensuring 20dB/decade roll-off before UGF. As the op-amp is fully
differential, common mode feedback structure is needed to stabilize the output common mode
level of op-amp, which in turn biases the next stage, i.e., comparator with hysteresis. The
complete op-amp with the common mode feedback is shown in Fig. 3.2. The gain of the op-amp
is set to be 55dB in open loop, with UGF around 2.4GHz, with a load of 100fF .
The output common mode level of the circuit is set to be 1.1V which biases the comparator. The
resistive mode detection of common mode level is replaced with the transistors, which avoids the
use of large resistors, so as not to affect the differential gain of op-amp. The common mode
feedback loop should be checked for stability, to ensure proper operation.
The reference current chosen for the analog circuit is 50A. The reference current is generated
using reference current generator shown in Fig. 3.2. The current from the reference current
generator is mirrored accordingly using PMOS and NMOS for the supply of 50A source and
sink currents respectively.
The integrator is built with the above telescopic-cascode differential amplifier. The unity gain
cut-off frequency of the integrator is set to around 151MHz. The resistance (R) is chosen to be
10K, and the capacitance (C) is chosen to be 100fF for the UGF of integrator to be 151MHz.
For the overall feedback to be stable, FB is chosen to be around 0.6, giving the feedback
resistance R
]b
to be 15K.

Page 12 of 12


Fig 3.2: Telescopic cascode with common mode feedback, reference current circuit
3.4 Comparator with hysteresis:
. For the 1
st
order ASDM loop (with single integrator and comparator) to have the start up
of oscillations, the comparator should have hysteresis and the dependence of free running
frequency on hysteresis is as per Eq.4.1. Hysteresis is the quality of a comparator in which the
output level changes when the input level crosses the hysteresis point. When the input passes the
threshold, defined by the design, the output changes and the input threshold is reduced so that the
input must be lower than the previous threshold voltage before the comparator changes that state
again . Figure 3.3 illustrates the transfer function of a hysteresis comparator. Assuming the input
voltage starts at negative and increases, comparator output changes when the input crosses the
positive hysteresis point. During this state, the negative hysteresis point changes[14].
Comparator output changes when the input voltage crosses the negative hysteresis point.
Usually, the width of hysteresis is defined as the difference between the positive and the negative
turning point.
The hysteresis comparator schematic is shown in Fig 3.4. There are two feedback paths in the
circuit, positive and negative feedback. The cross coupled transistors provide positive feedback.
For the hysteresis to occur, the positive feedback factor should be greater than negative feedback.
The ratio of widths of cross-coupled transistor to the diode-connected transistor is the key in
determining the width of hysteresis in the transfer curve of comparator. The outputs of the
Page 13 of 13

comparator are pulled to supply and ground using the inverters connected to the outputs of
comparator. The reference current for the comparator is chosen to be 50A.
Hysteresis of the comparator should be kept as low as possible for the oscillation
frequency of the modulator to be high. The hysteresis of the comparator depends on various
factors like the process technology, bias current and the ratio of widths of cross-coupled
transistor to diode-connected one [11].


Figure 3.3: Transfer function of comparator with hysteresis

Figure 3.4: Comparator with hysteresis
Page 14 of 14

The hysteresis of the comparator is given by ,
=2

(I
bus
I
q
/ c
ox
pw
q
(o 1)/ 1+o.....................................( 3.4)
where I
bus
is the tail biasing current, is the ratio of aspect ratios of cross-coupled transistor to
the diode-connected and w
q
/ I
q
is the aspect ratio of input pair. The trade off exists in the
comparator between the power consumption and switching speed on one hand and minimum h
and on the other[11]. The minimum value of h that can be implemented is evaluated with
respect to the process technology constraints, while always ensuring the regenerative action of
the comparator .

3.5 Phase error detection
The phase error is detected by mathematical subtraction between the continuous phase and the
sampled phase of VCO, which is implemented in design by digital XOR gates. Each gate
generates phase error for one output node of VCO. From the phase error-detection a
corresponding control signal is generated to drive the DAC. As there are thirty-two phases that
would be sampled from VCO, the corresponding phase error would be generated for all the 32
nodes. All these would be added with the help of a 32-bit adder, which generates a 5 bit output.
The 5-bit digital output drives the current steering DAC to generate equivalent analog signal.

3.6 32-bit Carry-Look-Ahead adder
One 32-bit adders are used in the architecture. One is given in the feed-forward path to generate
a 5-bit control signal for the DAC and the other to generate the final digital output. The
schematic of the carry look ahead adder designed in cadence is shown in Fig. 4.8. The carry-look
ahead adder is implemented in a conventional way using CMOS logic [12]. As shown in Fig.4.8,
the carry-look ahead adder is implemented in pipelined fashion. The 1
st
stage is implemented
with the help of Half-adders, which takes 2 bits and generates sum and carry bits. The 2
nd
stage is
implemented with 2-bit CLA style, and generates 3-bits, two sum bits and one carry bit. The 3
rd

stage is implemented with 3-bit CLA style, generating 4-bits and so on. The last stage is
implemented with 5-bit CLA taking two 5-bits generating 6-bit output. Since the adder takes its
inputs from previous 32-bit XOR block, and all the 32-bits cant be simultaneously one (This is a
condition of phase-overflow, which is avoided in the design, by making the sampling frequency
at least twice that of VCO-free running frequency), the carry bit of last stage will never be 1
and thus the carry generation block for 5-bit CLA is discarded.
Page 15 of 15


Figure 3.5: 32-bit carry look-ahead adder
The delay that should be taken to generate the final 32-bit addition output should be less
than 1.54ns. The pipelined structure is advantageous in a way that the delay constraint can be
mitigated with the help of inclusion of a register, which is clocked with the same frequency as
that of a sampling clock, at the cost of latency .Latency is not a major problem in ADC design, as
the digital output for the first sample will be delayed by the latency added by the system, there
onwards the digital output will be coming with a delay of one clock period (1T). With the
inclusion of register, the first three stages in pipelined adder can have the delay of 1T and the last
two stages can have the delay of 1T. This ensures safe operation, as any malfunctioning of the
adder, due to not meeting the delay constraint can hamper the overall ADCs performance. All
the output bits of an adder are synchronized with the help of a register clocked with the sampling
clock. The adder, thus adds a latency of 2T in the system.
The first stage in the pipeline is implemented with Transmission-Gate logic, since it
offers fewer loads to the previous stage (XOR in this case which is also implemented with TG
logic). TG logic is smart in a way, that they are simpler and consumes very less area, but the
speed of this kind of logic becomes really bad when driving large capacitive loads .Since the
delay constraint needs to be met, the 2
nd
, 3
rd
, 4
th
and 5
th
stages in the pipelined stage are
implemented with CMOS logic style.





Page 16 of 16

Chapter 4: Results of ADC
After discussing the design of individual blocks in the double VCO based ADC, this chapter
gives the results of the same, done in cadence UMC 180nm CMOS technology.
4.1 ASDM
The frequency response of the telescopic cascode amplifier and the comparator with hysteresis is
shown in Fig. 4.1 and Fig. 4.2 respectively. The various parameters of op-amp and the
comparator are tabulated in table 4.1 and table 4.2.

Figure 4.1: Frequency response of the telescopic cascode amplifier (Gain =55.68dB)
Table 4.1: Telescopic cascode based op-amp
Sl.No. Parameter Obtained from
Simulation
1. DC Gain 55.68 dB
2. Input common-mode 0.6V 0.9V
3. PM(with 100fF load) 50
4. Output Swing 450 mV P/P
5. Output common mode level 1.05 V
Page 17 of 17

6. Power Consumption 1.5 mW
7. Unity-Gain cut off frequency(with
15fF load)
2.2GHz
8. Slew-rate(with 100fF Load) 2.12 V/ns


Figure 4.2: Frequency response of a comparator with hysteresis

Table 4.2: Comparator with hysteresis
Sl.No. Parameter Obtained from
Simulation
1. DC Gain 70 dB
2. Input common-mode 0.9V-1.2V
3. Comparator Hysterisis 41 mV
4. Output common mode level 0.84V
5. Power Consumption 0.7 mW

Page 18 of 18

Together with the op-amp integrator and comparator with hysteresis in feedback, ASDM is
realized, the free running oscillations of which is found to be 570MHz. The integrators and the
comparator with hysteresis output is shown in Fig. 4.3.

Figure 4.3 ASDM free running oscillations along with the integrators output
The ASDM realised, acts a pulse-Width modulator for the input signal [8]. The Pulse width
modulated wave, generated by ASDM for 1MHz input sinusoidal signal, is shown in Fig. 5.4.
ASDMs differential output drives the chain of current-starved inverters in the VCO. A buffer
(chain of inverters) is designed in between, so as not to to have an impact on rise and fall timings
of PWM signal, due to the effective load capacitance seen by it, had the buffer not been there.
The buffer is designed with the help of inverter chain (6 in this case), the 1
st
stage is with
minimum size devices, and the rest of the stages with a tapering ratio of 3. PMOS devices width
is chosen to be 2.5 times that of NMOS to have equal raise and fall time delays. The SFDR of the
modulation is calculated using cadence psd calculator function. The SFDR tells how clean the
pulse-width modulation is performed. Since the sampling is not involved in ASDM, the
quantization noise is not added here.
The SFDR of the modulation decreases with increase in frequency and Modulation depths.
Figure 5.5 shows the PSD plot of PWM waveform of 16MHz sinusoidal signal with 750mV
peak-to-peak. The SFDR is found to be 83dB from the PSD plot. The SFDR after modulation is
tabulated in Table 4.3.

Page 19 of 19


Figure 4.4 PWM output from ASDM for 1MHz input sinusoidal signal

Figure 4.5: PSD and DFT plot for PWM of 16MHz 750mV peak-to-peak (SFDR=75 dB)

Page 20 of 20

Table 4.3: SFDR of PWM after ASDM
Sl.No Frequency(650mv p-p) SFDR obtained from PSD cadence(in
dB)
1. 20 MHz 75
2. 18 MHz 72
3. 16 MHz 73

Table 4.4 Summary of ASDM
Sl.No. Parameter Simulation
1. Free running frequency 544 MHz
2. Integrator UGF 151 MHz
3. Power Consumption 2.2 mW
4. SFDR of PWM (within 20
MHz Bandwidth)
75dB
4.2 Differential VCO
(a) Phase Noise
Phase noise (at frequency 500MHz) =-106.7 dBc/Hz @1MHz offset


Figure 4.6: Phase noise of differential VCO
Page 21 of 21

(b) Frequency Tuning Curve
Frequency tuning 450 MHz to 910 MHz

Figure 4.7: Tuning Curve of differential VCO
(c) Jitter Performance of Implemented VCO
J itter =21 ps Frequency of Oscillation =910MHz
Period of Oscillation =1.09ns % of J itter =(21ps / 1.09ns )*100 =1.6%


Figure 4.8 Jitter performance (@ 910 MHz)
Page 22 of 22

J itter =5 ps Frequency of Oscillation =476MHz
Period of Oscillation =1.09ns % of J itter =(5ps / 2.10ns )*100 =0.238%
Figure 4.9 Jitter performance (@ 476 MHz)

(d) VCO Specification
Parameters Cross coupled Delay cell Negative Skewed Delay cell
Number of
Stages
8 8
Delay Cell Cross Coupled Negative Skewed delay
Supply voltage 1.8V 1.8V
Tuning Range 285 475Mhz 458 910 MHz
Phase Noise -100.7 dBc/Hz @ 1MHz Offset -106.1 dBc/Hz @ 1MHz Offset
-126 dBc/Hz @ 10MHz Offset -131 dBc/Hz @ 10MHz Offset
J itter
Performance
163 ps (4.5% of Total Period) 10 ps (0.9% of Total Period)
Power 3.4 mW 3.6 mW
Page 23 of 23

4.3 1st order Results of VCO based ADC

Figure 4.10 Test of VCO based ADC
The test bench for 1
st
order noise shaping is shown in Fig. 5.15. The ADCs performance is
evaluated by giving the digital output to an Ideal DAC and observing the frequency components
in it using PSD and DFT plots. The PSD plot for 16MHz input signal is shown in fig. 5.16, the
SFDR as shown, is found to be 61dB. The PSD Plot for 14MHz input is shown fig 5.17. The
simulation time chosen for both the simulations is around 30s (around 256 cycles). The SNR
was calculated from the DFT plot.
SNR =20log
10
_
Signol
RMS
Noisc
RMS
] .Eq.5.3
where the RMS value of the Noise is calculated from the DFT components(excluding DC and
signal frequency component) within 20MHz bandwidth(which is targeted).

Figure 4.11 PSD plot of VCO-ADC (18 MHz , 600mv p-p Input signal)
Page 24 of 24

Figure 4.12 DFT plot of VCO-ADC (18 MHz , 600mv p-p Input signal)


Figure 4.13 Input/Output Comparision of VCO-ADC (18 MHz , 600mv p-p Input signal)
Page 25 of 25

(d) ADC Summary (Without Digital Calibration and Decimation Filter)
Sl.No. Parameter Implemented VCO ADC Reference Paper
1. Sampling frequency 600 MHz 600 MHz
2. Modulation depth 180 nm 130 nm
3. Power consumption 11 mW 14.3 mW
4. SFDR(16MHz) 57 dB 64 dB (After Calibration)
5. Bandwidth 19 MHz 20 MHz
6. SNR(16MHz) 47.2 dB 55.1 dB
7. Area NA (After Layout) 0.12 mm sq.




















Page 26 of 26

Conclusion & Future Work
Digital analog to digital converters have potential applications in very low voltage, low power circuits.
Moreover, the implementation of such converters is fully compatible with the standard digital CMOS
technology. Actually one important feature of Digital ADC is that, advances in process technology allow
the same architecture to achieve a high sampling frequency and better resolution as well as lower power
consumption.
The design is implemented in UMC 180nm CMOS process with a supply voltage and it can be used for
lower supply voltage and sub micron technologies. The VCO ADC is designed with approx 20 MHz
bandwidth and SNR/SFDR of value 47.2 dB/ 57 dB.
The Dynamic performance of VCO based ADC can improved in open loop configuration with digital
calibration and decimation filter techniques.

















Page 27 of 27


References
(1) C.H.Park and B.Kim , A Low noise , 900MHz VCO in 0.6m CMOS, IEEE J . Solid State Circuits ,
vol. 34 , no. 5 ,pp. 179-194, May 1999.
(2) Yalcin Alper Eken and J ohn P.Uyemera, A 5.9 GHz Voltage Controlled Oscillator in 0.18m CMOS ,
IEEE J . Solid State Circuits , vol. 39, no. 1 ,pp. 230-233,J an. 2004.
(3) T.K. J ang and J . Kim, A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase
Interpolator and Digital Calibration, IEEE transactions on very large scale integration (VLSI) systems,
vol. 20, no. 8, August 2012.
(4) S.Lee, B.Kim and K.Lee . A novel High Speed Ring Oscillator for multiphase clock generation using
negative skewed delay scheme, IEEE J .Solid State Circuits , vol. 32, no. 2,pp. 289-291,Feb. 1997.
[7] Sachin Rao, Brian Young, Amr Elshazly, Wenjing Yin, Naga Sasidhar, and Pavan Kumar Hanumolu,
A 71dB SFDR Open Loop VCO-Based ADC Using 2-Level PWM Modulation, 2011,Symposium on VLSI
Circuits.
[8] Engel Roza,Analog-to-Digital Conversion with duty cycle modulation, IEEE transactions on circuits
and systems, Analog and Digital Signal processing, Vol.44, No.11, November 1997.
[9] J aewook kim, Tae-Kwang jang, Young-Gyu Yoon and Seong Hwan Cho, Analysis and Design of
VCO based ADCs, IEEE transactions on circuits and systems, Vol.57, No.1, J an 2010.
[12] CMOS Analog circuit Design, Philip E. Allen, Douglas R. Holberg, Oxford University Press, 2
nd

Edition,2010.
[13] J org Daniels, Wim Dehaene, Michael S.J . Steyaert and Andreas Wiesbauer,A/D conversion using
Asynchronous delta-sigma modulation and Time-to-Digital conversion, IEEE transactions on circuits and
systems, Vol.57, No.9, Sep 2010.
[14] Design of Analog CMOS integrated circuits, Behzad Razavi, McGRAW-HILL International
Edition,2001.