PART-1 1.

Determine the range and resolution of a 16-bit timer which operates at a clock frequency of 1OMHz and generates an overow signal when it reaches FFFF. Calculate the terminal count value for measuring a 3msec time interval. What is the minimum division needed in a prescaler for measuring l00msec?
Sol:

Resolution = period = 1 / frequency = 1 / (10 MHz) = 0.1^(-6) s Range = 2^16 * resolution = 65536 * 10^(-6) s = .0065536 s = 0 to 6.5536 ms Terminal count value = desired time interval / clock period = 3m s / 0.1^(-6) s = 30,000 The prescaler should be set to output a frequency 1/(2^4) or 1/16 the original frequency of 10 MHz.

2.What is WDT and what is its use ? A 16 bit timer operates at clock frequency of 200 MHz. If a4 prescaler is also used what is the range and resolution of the design.
(Refer notes also)

A watchdog timer can be thought of as having the inverse functionality than that of a regular timer. We configure a watchdog timer with a real-time value, just as with a regular timer. However, instead of the timer generating a signal for us every X time units, we must generate a signal for the timer every X time units. If we fail to generate this signal in time, then the timer generates a signal indicating that we failed. Use of WDT : To enable an embedded system to restart by itself in case of failure. Here we connect fail signal WDT to processor reset pin to implement a time out for an ATM. Resolution = period = 1 / frequency = 1 / (200 MHz) = 0.005*10^(-6) s Range = 2^16 * resolution = 65536 *0.005* 10^(-6) s = 32.768ms Reduced resolution = p*Resolution Here p=4 Reduced resolution = 4*0.005*10^(-6) s=0.02*10^(-6) s Range = 4*32.768ms=131.072ms

3. Similar problem done in notes 4. Similar problem done in notes 5.Describe the working of PWM with necessary diagrams and explain how it can be used in the speed control of DC motor.
A pulse-width modulator (PWM) generates an output signal that repeatedly switches between high and low. We control the duration of the high value and of the low value by indicating the desired period, and the desired duty cycle, which is the percentage of time the signal is high compared to the signal's period. A square wave has a duty cycle of 50%. The pulse's width corresponds to the pulse's time high. Again, PWM functionality could be implemented on a dedicated general-purpose processor, or integrated with another program's functionality, but the single-purpose processor approach has the benefits of efficiency and simplicity.

One common use of a PWM is to control the average current or voltage input to a device. For example, a DC motor rotates when power is applied, and this power can be turned on and off by setting an input high or low. To control the speed, we can adjust the input voltage, but this requires a conversion of our high/low digital signals to an analog signal. Fortunately, we can also adjust the speed simply by modifying the duty cycle of the motors on/off input, an approach which adjusts the average voltage. This approach works because a DC motor does not come to an immediate stop when power is turned off, but rather it coasts, much like a bicycle coasts when we stop pedaling. Increasing the duty cycle increases the motor speed, and decreasing the duty cycle decreases the speed. This duty cycle adjustment principle applies to the control other types of electric devices, such as dimmer lights.

6.Explain how a stepper motor is controlled using driver. Give relevant hardware and software details. Controlling a stepper motor requires applying series of voltages to the four coils of the stepper motor. The coils energized one or two at a time causing the motor to rotate one step. In this example, we are using 9v.2 phase bipolar stepper motor. The entire sequence must be applied to get the motor to rotate 7.5 degrees.To rotate the motor in opposite direction we simply apply the sequence in reverse order. we can use an 8051 microcontroller and a stepper motor driver(MC3479P)chip to control the stepper motor.We need only worry about setting the direction on the clockwise/counterclockwise pin and pulsing the clock pin on the stepper motor driver using the 8051 microcontroller.

7.Given the following three cache designs, find out the one with the best performance by calculating the average cost of access. a. 4K bytes 8-way set-associative cache with 6% miss rate. Cache hit costs 1 cycle and cache miss costs 12 cycles. b. 8K bytes 4-way set-associative cache with 4% miss rate. Cache hit costs 2 cycle and cache miss costs 12 cycles. c. 16K bytes 2-way set-associative cache with 2% miss rate. Cache hit costs 3 cycle and cache miss costs 12 cycles.
Sol: a) 4 Kb, 8-way set-associative cache with a 6% miss rate; cache hit costs 1 cycle, cache miss costs 12 cycles. miss rate =0.06 hit rate = 1- miss rate =0.94 0.94 * 1cycle (hit) +0 .06 * 12 cycles (miss) =0 .94 + 0.72 = 1.66 cycles avg. b) 8 Kb, 4-way set-associative cache with a 4% miss rate; cache hit costs 2 cycles, cache miss costs 12 cycles. miss rate =0 .04 hit rate = 1 - miss rate =0.96 0.96 * 2 cycles (hit) + 0.04 * 12 cycles (miss) = 1.92 + 0.48 = 2.4 cycles avg. c) 16 Kb, 2-way set-associative cache with a 2% miss rate; cache hit costs 3 cycles, cache miss costs 12 cycles. miss rate = 0.02 hit rate = 1 - miss rate = 0.98 0.98 * 3 cycles (hit) + 0.02 * 12 cycles (miss) = 2.94 + 0.24 = 3.18 cycles avg. BEST PERFORMANCE: a) 1.66 cycles avg.

8. With diagram explain the direct mapping technique for cache.

Cache mapping is the method for assigning main memory addresses to the far fewer number of available cache addresses, and for determining whether a particular main memory address' contents are in the cache.

Direct mapping:
In this technique, the main memory address is divided into two fields, the index and the tag. The index represents the cache address, and thus the number of index bits is determined by the cache size, i.e., index size = log2(cache size). Note that many different main memory addresses will map to the same cache address. When we store a main memory address' content in the cache, we also store the tag. To determine if a desired main memory address is in the cache, we go to the cache address indicated by the index, and we then compare the tag there with the desired tag. Direct-mapped caches are easy to implement, but may result in numerous misses if two or more words with the same index are accessed frequently, since each will bump the other out of the cache. Fully-associative caches on the other hand are fast but the comparison logic is expensive to implement. Set-associative caches can reduce missescompared to direct-mapped caches, without requiring nearly as much comparison logic as fully-associative caches. Caches are usually designed to treat collections of a small number of adjacent main memory addresses as one indivisible block, typically consisting of about 8 addresses. NOTE: Draw Fig. 6.2 Direct Mapping

PART-2 1. With the help of timing signals, explain how disabling of interrupts affects system response for the following case. Disable interrupts for 125 sec for task code to use a pair of temperature variables it shares with ISR that reads temperatures from hardware and writes them into variables. Disable interrupts for 250 sec for task code to get time accurately fromvariables it shares with ISR that responds to timer interrupt. A special signal recieved from another processor shall be responded with 625 sec If in the above case, microprocessor is replaced with another having exactly half speed, will the system meet the deadline?

Interrupts are disabled in our hypthetical system for at most 250 sec at a time. The interrupt routine needs 300 sec, for a total, worst case time of 550 sec, within the 625 sec limit. Note that the interrupt will never be delayed for 375 sec, the sum of the two periods of time during which interrupts are disabled. If the hardware asserts the interprocessor interrupt signal while the system has disabled interrupts in order to read the time, then in at most 250 sec the system will reenable the interrupts, and the microprocessor will jump to the interrupt routine. The fact that the system might at some other time disable the interrupts for another period of time is irrelevant. There is no way to enable and then disable interrupts so fast that the microprocessor will not service the pending interrupts. However, to cut costs, the hardware group proposes to replace the microprocessor with one that runs only half as fast. The prcessing time are doubled, interrupts are disabled for twice as long, the ISR takes twice as long, but the 625 sec deadline remains the same. The system will not meet its deadline. Interrupts will be disabled for upto 500 sec at a time, and the ISR needs 600 sec to do this work.The total of these two is 1100 sec , much longer than the 625 sec deadline.

2. Let the minimum interrupt latency in a system be 100usec and context switching time is negligible. The execution time for high, medium and low priority processes be 200usec, 400usec and 600usec respectively. The deadline for the low priority process be 1000usec. Is it possible for the low priority process to complete its execution if a) Both high and medium processes interrupt it and b) Only high priority processes interrupt it? Write timings diagrams for both the cases and indicate worst case interrupt latency and total time.
Sol:

a) when both high and medium processes interrupts, then the lower priority process does not complete its execution. Highest priority interrupt takes 200usec for execution and has interrupt latency of 100usec and the medium interrupt takes 400usec for execution and has interrupt latency of 100usec therefore in total 800usec is required for both this to be executed and then lower interrupt process required 600usec plus interrupt latency time total 1500usec but the deadline is 1000usec for low priority process to complete its execution so it is not possible to execute low priority process. (Deadline time should be more than the total time for execution.) b) when only high priority process interrupt is executed then it takes 200usec plus 100usec for interrupt latency time and for low interrupt process it takes 600usec plus 100usec in total 1000usec which is same as deadline time so this may execute low priority process. 3.Explain the need for interrupts in processing system. Also explain the various events that take place when a processor is interrupted.
Suppose a peripheral intermittently receives data, which must be serviced by the processor. There are two methods of servicing viz Polling and Interrupts. Polling-The processor can poll the peripheral regularly to see if data has arrived, this method is wasteful. Interrupts-The peripheral can interrupt the processor whenever it has data, this method is efficient as it saves CPU time to greater extent. It requires an extra pin/pins:Int, if Int is 1, processor suspends current program, jumps to an Interrupt Service Routine(ISR). Essentially, "polling" of the interrupt pin is builtinto the hardware. So no extra time is required to poll the interrupt pin.

Events taking place when a processor is interrupted are Microprocessor detects interrupt request (IRQ) signal is asserted Stops executing the instructions Saves on stack the address of next instruction Jumps to interrupt service routine (ISR) and executes it Returns from ISR Pops address from stack Continues execution of next instruction

On the left-hand side of the code is the task code , the microprocessor is busy doing the task code. The task code is busy converting emperatures from centigrade to Farrenheit. It moves the centigrade temperature into register R1,does the necessary arithmetic, and store the result. When the interrupt occurs, the microprocessor suspends the task code, and goes to the instructions that make up the interrupt routine. It does all of those instructions; when it comes to the RETURN instruction at the end of the interrupt routine,it goes back to the task code and continues converting temperatures. Interrupt service routine pushes the values in register R1 and R2 onto thestack before executing interrupt code and then pops them(in reverse order) after executing interrupt code. This is known as Saving and restoring the context. permanent failure of a node versus temporary errors.

4. What is interrupt latency? Explain the factors affecting it.

Interrupt latency refers to the amount of time it takes a system to respond to an interrupt. It is nothing but how fast does my system respond to each interrupt. Factors affecting interrupt latency are: 1.The longest period of time during which that interrupt is disabled. 2.The period of time it takes to execute any interrupt routines for interrupts that are of higher priority than the one in question. 3.How long it takes the microprocessor yo stop what it is doing, do the necessary bookkeeping, and start executing instructions within the interrupt routine. 4.How long it takes the interrupt routine to save the context and then do enough work that what it has accomplished counts as a "response". However different people include different combinations of the above factors when they calculate interrupt latency.among 4 above factors factor 3 can found by looking in the microprocessor documentation provided by the manufacturer. The other 3 items can found in one of two ways.First , we can write the code and measure how long it takes to execute. Second, you can count the instructions of various types and look up in the microprocessor's documentation how long each type of instruction takes. The later technique works reasonably ell for the smaller microprocessor, since the time it takes to do each instruction is deterministic, and the manufacturer can provide the data. It works far less well for microprocessors that cache instructions ahead of time;with these microprocessors,how long an insructin takes depends critically upon whether the instruction was already in the cache and often upon several other unknowable factors as well.

5. Explain the reason why the systems with the conventional operating system fail to respond to real time problems. Also explain how these are taken care in RTOS.
The systems with conventional operating system fail to respond to real time problems because all the shared data problems can jump and bite you. Worst case response time= sum of task code execution times of all other device in round robin architecture where as in function- queue scheduling architecture worst wait for highest priority task code function = length of longest task code function . Where as in real time operating system interrupt routines take care of most urgent operations. Signal that there is work for task code to do. Difference with other architectures. Signal between interrupt routine and task code is handled by RTOS (no need of shared variables). No main loop deciding what to do next, RTOS decides the scheduling . RTOS can suspend one task code sub routine to run another.

Worst case execution for the sample code shown :

Advantages of RTOS:
1. Changes to any task code in the RR or function - queue scheduling schemes have a global effect :affects all tasks 2. Changes to lower priority task code in RTOS does not affect response time of higher priority tasks 3. RTOS are widely available , immediate solution to your response problems

6.Differentiate between hard and soft RTOS highlighting the advantages and disadvantages of each.