Dept 34 LV 3 14910

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Text: Charles H. Roth, Jr.
Fundamentals of Logic Design

5th Edition 2004 THOMSON BROOKS/COLE
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Digital Systems and Switching Circuits

Digital system The physical quantities or signals can assume only discrete values Greater accuracy Analog system The physical quantities or signals may vary continuously over a specified range
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Design of digital systems

System design Breaking the overall system into subsystems Specifying the characteristics of each subsystem E.g. digital computer : memory units, arithmetic unit, I/O devices, control unit Logic design Determining how to interconnect basic logic building blocks to perform a specific function E.g. arithmetic unit : binary addition: logic gates, Flip-Flops, interconnections Circuit design Specifying the interconnection of specific components such as resistors, diodes, and transistors to form a gate, flip-flop or other logic building block E.g. Flip-Flop: resistors, diodes, transistors
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Many of subsystems of a digital system take the
form of a switching network

Switching Networks
Combinational Networks
No memory
Sequential Networks
Combinational Circuits + Memory
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Basic Operations
The basic operations of Boolean algebra are
AND, OR, and NOT (complement, or inverse).

NOT (Complement)
0 = 1 1 = 0 X = 1 if X = 0 and X = 0 if X = 1
Inverter
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Basic Operations
AND
Operation
Omit the symbol ., A . B=AB
AND Gate
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Basic Operations
OR
operation
OR Gate
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Exclusive-OR and Equivalence Operations

Exclusive-OR:
0 0 = 0 0 1 = 1 1 0 = 1 11 = 0
Truth table and gate for X Y
X Y =1 if and only if X=1 or Y=1 and X and Y are not both 1.

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The equivalence operation( ) is defined by
The truth table for X Y is
(X Y) =1 if and only if X = Y .
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( X Y ) = XY + X Y
Equivalence is the complement of exclusive-OR:
( X Y ) = ( X Y + XY ) = ( X + Y )( X + Y ) = XY + X Y = ( X Y )
Alternate symbol for the equivalence gate
The equivalence gate is also called an exclusive-NOR gate.
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NAND and NOR Gates

NAND gate: An AND gate followed by an NOT gate
n-input NAND gates: n=2 F = ( AB ) = A + B n=3 F = ( ABC ) = A + B + C
+ ... + X n F = ( X 1 X 2 ... X n ) = X 1 + X 2
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NAND and NOR Gates

NOR gate: An OR gate followed by an NOT gate
n-input NOR gates: n=2 F = ( A + B ) = AB n=3 F = ( A + B + C ) = ABC

... X n F = ( X 1 + X 2 ... + X n ) = X 1X 2
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Boolean Expressions and Truth Tables

Order in which the operations are perform
ParenthesesComplentationANDOR Circuits for expressions

AB + C
[ A(C + D )] + BE
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Truth Table
If an expression has n variables, the number of different
combinations of values of the variables is 2n. Therefore, a truth table for n-variable expression will have 2n rows. ( 2n ) There are 2 functions of n variables.
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Sum-of-products (SOP)
An expression is said to be in sum-of-products form when all products are the products of only single variables.
AB + CDE + AC E , A + B + C + DE are in SOP form, ( A + B)CD + EF is not in SOP form.
Product-of-sums (POS)
An expression is said to be in product-of-sums form when all sums are the sums of only single variables.
( A + B)(C + D + E )( A + C + E ) , ABC ( D + E ) are in POS form, (A + B)(C + D) + EF is not in POS form.
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Combinational Logic Design Using a Truth Table

Example: Design a switching circuit with three
inputs A, B, and C and one output f. The input A,B, and C represent the first, second, and third bits, respectively, for a binary number N. f=1 if N 0112 and f=0 if N < 0112 . Sol-1:
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Sol-1 (cont.): Derive an algebraic expression for
f from the truth table by using the combinations of values of A,B, and C for which f=1. f = ABC + ABC + ABC + ABC + ABC = ABC + AB + AB = ABC + A = A + BC The circuit is
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Sol-2: First write f as a sum of products, and then complement the result. f is 1 for input combinations ABC=000, 001, 010, so
f = ABC + ABC + ABC

f = ( f ) = ( ABC + ABC + ABC ) = ( A + B + C )( A + B + C )( A + B + C ) ( Three 3 - input OR gates and one 3 - input AND gate) = ( A + B )( A + B + C ) [Two OR gates and one AND gate] = A + BC
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Minterm and Maxterm Expansions

Minterm
A minterm of n variables is a product of n literals in which each variable appears exactly once in either true or complement form, but not both. Maxterm A maxterm of n variables is a sum of n literals in which each variable appears exactly once in either true or complement form, but not both.
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Minterm and Maxterm for three variables
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Minterm expansion or
Standard sum of products

When a function is written as a sum of minterms, this is referred to as a minterm expansion or standard sum of products.
Examples: f ( A, B, C ) = ABC + ABC + ABC + ABC + ABC
f ( A, B, C ) = m3 + m4 + m5 + m6 + m7 f ( A, B, C ) = m(3,4,5,6,7)
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Maxterm expansion or
Standard product of sums

When a function is written as a product of maxterms , this is referred to as a maxterm expansion or standard product of sums.
Example: f ( A, B, C ) = ( A + B + C )( A + B + C )( A + B + C )
f ( A, B, C ) = M 0 M 1M 2 f ( A, B, C ) = M (0,1,2)
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Complement of a function f .
Example:
f ( A, B, C ) = m3 + m4 + m5 + m6 + m7 f = (m3 + m4 + m5 + m6 + m7 )
m4 m5 m6 m7 = M 3M 4 M 5M 6 M 7 = m3
f ( A, B, C ) = M 0 M 1M 2 + M 1 + M 2 = m0 + m1 + m2 f = ( M 0 M 1M 2 ) = M 0
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Incompletely Specified Functions

Incompletely Specified Function
A function contains dont care terms.
Example 1: The output of subcircuit N1 drives the input of the subcircuit N2. Assume that there are no combinations of values for w,x,y, and z which cause A,B, and C to assume values of 001 or 110..
The function F is incompletely specified.

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Incompletely Specified Functions

Example 1(cont.):
F = m(0,3,7) + d (1,6) F = M (2,4,5) D (1,6)
1. Assign 0 to both Xs F = A B C + A BC + ABC = A B C + BC 2. Assign 1 to the first X and 0 to the second --- simplest solution
F = ABC + ABC + ABC + ABC = AB + BC

3. Assign 0 to the first X and 1 to the second
F = ABC + ABC + ABC + ABC = ABC + ABC + AB
4. Assign 1 to both Xs
F = ABC + ABC + ABC+ ABC + ABC= AB + BC+ AB

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Examples of Truth Table Construction

Example 2: Design an adder which adds two
2-bit binary numbers to give a 3-bit binary sum. The circuit has 4 inputs and 3 outputs :
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Examples of Truth Table Construction

Example 2(cont.):
The output functions are :

X ( A, B, C , D) = m(7,10,11,13,14,15) Y ( A, B, C , D ) = m(2,3,5,6,8,9,12,15) Z ( A, b, C , D ) = m(1,3,4,6,9,11,12,14)
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Design of Binary Adders and Subtracters

Half Adder:
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Full Adder:
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The logic equation for the full adder:
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The logic circuit of full adder:
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4-Bit Parallel Adder
Adds two 4-bit unsigned binary numbers
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4-Bit Parallel Adder
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Unit 5 Karnaugh Maps
Two- and Three- Variable Karnaugh Maps

2- variable Karnaugh Maps
Example:
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2- variable Karnaugh Maps
Example:
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3-variable Karnaugh Maps
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Adjacent Cells
Two cell which differ in just one variable are said to be adjacent. 2k adjacent calls can be combined.
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If F is given as a minterm (maxterm) expansion, the map by placing 1s(0s) in the squares which correspond to the minterm ( maxterm) and then by filling in the remaining squares with 0s(1s).
Example: F(a,b, c) = m1 + m3 + m5 = M0M2M4M6M7
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If a function is given in algebraic form,
plot its Karnaugh Map. Example: f (a, b, c) = abc + bc + a
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Simplify a function using Karnaugh Map
Example: F = m(1,3,5)
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Simplify a function using Karnaugh Map
Example: Simplify the complement of

F = m(1,3,5)
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Illustrate the Consensus Theorem
Example:
xy + xz + yz = xy + xz
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Minimum sum-of-products is not unique. f = m(0,1,2,5,6,7) Example:
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Four- Variable Karnaugh Maps

4-Variable Karnaugh Maps
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Example: f (a, b, c, d ) = acd + ab + d
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Example: Simplify f1 = m(1,3,4,5,10,12,13)
f 2 = m(0,2,3,5,6,7,8,10,11,14,15)
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Simplify a function with dont care Example: f = m(1,3,5,7,9) + d (6,12,13)
All the 1s must be covered, but the Xs are only used if they will simplify the resulting expression.
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Find a minimum product-of-sums
1. Find a minimum sum-of-products for F 2. Complement F using DeMorgans Theorem Example: Find a minimum product-of-sums for
f = xz + wyz + wyz + xy
f = yz + wxz + wxy f = ( f ) = ( y + z)(w + x + z)(w+ x + y)
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Determination of Minimum Expansions Using Essential Prime Implicants

Cover: A switching function f(x1,x2,,xn) is said to
cover another function g(x1,x2,,xn), if f assumes the value 1 whenever g does. Implicant : Given a function F of n variables, a product term P is an implicant of F iff for every combination of values of the n variables for which P=1 , F is also equal 1.That is, P=1 implies F=1. Prime Implicant: A prime implicant of a function F is a product term implicart which is no longer an implicant if any literal is deleted from it. Essential Prime Implicant: If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant.
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Implicant :f1
1 F Prime Implicant: Essential Prime Implicant: (minterm)

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On a Karnaugh Map
Any single 1 or any group of 1s (2k 1s, k=0,1,2,) which can be combined together on a map of the function F represents a product term which is called an implicant of F. A product term implicant is called a prime implicant if it cannot be combined with another term to eliminate a variable. If a minterm is covered by only one prime implicant, then that prime implicant is called an essential prime implicant.
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Examples
f=wx+yz, g=wxy g=1 (w=1,x=1,y=0) implies f=1.1+0.z=1, f covers g. g is a product term, g is an implicant of f. g is not a prime implicant. The literal y is deleted from wxy, the resulting term wx is also an implicant of f. h=wx is a prime implicant. The deletion of any literal (w or x) results a new product (x or w) which is not covered by f. [w=1 does not imply f=1 (w=1,x=0,y=0,z=0 imply f=0)]
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5-variable Karnaugh Map
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Example : Simplify the function
F( A, B, C, D, E) = m(0,1,4,5,13,15,20,21,22,23,24,26,28,30,31)
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Unit 7 Multi-Level Gate Circuits NAND and NOR Gates
Multi-Level Gate Circuits

Increasing/reducing the number of levels Increasing the number of levels Reduce the required number of gates Reduce the number of gate inputs Increase gate delays Reducing the number of levels Reduce gate delays, speed up the operation of the digital system
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Multi-Level Gate Circuits

Example:
4 levels
6 gates 13 gate inputs
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Functionally Complete
A set of logic operations is said to be
functionally complete if any Boolean function can be expressed in terms of this set of operations. {AND,OR,NOT} is functionally complete. Any set of logic gates which can realize AND,OR, and NOT is also functionally complete. {NAND} is functionally complete. {NOR} is functionally complete. {AND,OR} is not functionally complete.
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{AND,NOT} is functionally complete.
{OR,NOT} is functionally complete.
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{NAND} is functionally complete.
Any switching function can be realized
using only NAND gates.

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{NOR} is functionally complete.
Any switching function can be realized
using only NOR gates.

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Design of Two-level Circuits Using NAND and NOR Gates

Example (cont.):
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Design of Two-level Circuits Using NAND and NOR Gates

Example (cont.):
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Design of Two-Level, MultipleOutput Circuits

Example: Design a circuit with four inputs and three outputs which realizes the functions F1 ( A, B, C , D) = m(11,12,13,14,15)
F2 ( A, B, C , D) = m(3,7,11,12,13,15) F3 ( A, B, C , D ) = m(3,7,12,13,14,15)
Sol: Each function is realized individually.

The cost of the resulting circuit is 9 gates and 21 gate inputs.
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Sol (cont.):
F1 ( A, B, C , D) = m(11,12,13,14,15) = AB + ACD
F2(A,B,C,D) = m( 3,7 ,11,12 ,13,15 ) = ABC + CD
F3(A,B,C,D) = m( 3,7 ,12 ,13,14 ,15 ) = ACD + AB

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Sol (cont.):
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Sol (cont.): Use the common terms to save gates. F1=AB+ACD F2=ABC+CD=ABC+ACD+ACD F3=ACD+AB
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Sol (cont.):
4 AND gates 3 OR gates

In realizing multiple-output circuits, the use of a minimum sum-of-product implicants for each function does not necessarily lead to a minimum cost solution for the circuit as a whole.
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Unit 08 Combinational Circuit Design and Simulation Using Gates
Gate Delays and Timing Diagrams

Propagation delay : If the change in output is delayed by time , , with respect to the input, we say that this gate has a propagation delay of . Propagation delay in an inverter
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Timing Diagram
Example: Assume that each gate has a propagation delay of 20 ns (nanoseconds).
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Example: Circuit with and delay element
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Hazards in Combinational Logic

The unwanted switching transients may
appear in the output when different paths from input to output have different propagation delays. Static 1- hazard: If , in response to any single input
change and for some combination of propagation delays, a circuit output may momentarily go to 0 when it should remain a constant 1, we say that the circuit has a static 1-hazard.
Static 0- hazard: If , in response to any single input

change and for some combination of propagation delays, a circuit output may momentarily go to 1 when it should remain a constant 0, we say that the circuit has a static 0-hazard.
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Dynamic hazard: If, when output is supposed to change from 0 to 1 (or 1 to 0), the output may change three or more times, we say that the circuit has a dynamic hazard.
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Example: Circuit with a static 1-hazard
Assume that each gate has a propagation delay of 10 ns. If A=C=1, then F=B+B=1. F should remain a constant 1 when B changes from 1 to 0.
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Procedure for detecting hazards in a
two-level AND-OR circuit

1.Write
down the SOP expression for the
circuit. 2.Plot each term on the map and loop it. 3.If any two adjacent 1s are not covered by the same loop, a 1-hazard exists for the transition between the two 1s. For an nvariable map, this transition occurs when one variable changes and the other n-1 variables are held constant.
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Eliminating hazards
Add a loop to cover two adjacent 1s.
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Example: A circuit with several 0-hazards F=(A+C)(A+D)(B+C+D)
A=0, B=1, D=0, C changes from 0 to 1 Gate delay : 3 ns for NOT, 5 ns for AND/OR
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Example (cont.):
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Example (cont.):
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Example (cont.):
Eliminating the 0-hazards by looping additional prime implicants that cover the adjacent 0s that are not covered by a common loop.
F = ( A + C)(A + D)(B + C + D)(C + D)(A + B + D)(A + B + C)
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Unit 9
Multiplexers, Decoders, and Programmable Logic Devices
Multiplexers
Multiplexers (MUX, or data selector)
A MUX has a group of data inputs and a group of control inputs. The control inputs are used to select one of the data inputs and connect it to the output terminal.
2-to 1 MUX

A=0, Z=I0 A=1, Z=I1 Z=AI0+AI1
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Multiplexers
4-to-1, 8-to-1, 2n-to-1 MUX
Logic equation for 8-to-1 MUX Z = ABC I 0 + ABCI1 + ABC I 2 + ABCI 3
+ ABC I 4 + ABCI 5 + ABC I 6 + ABCI 7

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Multiplexers
Logic Diagram for 8-to-1 MUX
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Multiplexers
Logic equation for 2n-to-1 MUX
2 n 1 k =0
Z=
mk I k
where mk is a minterm of the n control variables and I k is the corresponding data input
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Multiplexers
Quad Multiplexer Used to Select Data
A=0, (z0z1z2z3)=(x0x1x2x3) A=1, (z0z1z2z3)=(y0y1y2y3)

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Multiplexers
Quad Multiplexer with Bus Input and Output
A=0, Z=X
A=1, Z=Y
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Three-State Buffers
A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system. A buffer may be used to increase the driving capability of a gate output.
F =C
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Three-State Buffers
A logic circuit will not operate correctly if
the outputs of two or more gates or other logic devices are directly connected to each other. Use of three-state logic permits the outputs of two or more gates or other logic devices to be connected together.
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Three-State Buffers
Three-state buffer (Tri-state buffer)
Enable input B=1, output C=A, when B=0, C acts like an open circuit, C is effectively disconnected from the buffer output so that no current can flow. This is referred to a Hi-Z (high-impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current.
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Three-State Buffers
Data Selection Using Three-State
Buffers
D=BA+BC
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Three-State Buffers
Circuit with Two Three-State Buffers
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Three-State Buffers
Three-state Bus A bus is driven by three-state buffers 4-Bit Adder with four sources for one
operand

Use a 4-to-1 MUX to select one of several sources Set up a three-state bus
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Three-State Buffers
Bi-directional I/O Pin
Buffer
is enabled, Output Buffer is disabled, Input
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Decoders and Encoders

Decoder

Generates all of minterms Exactly one of the outputs lines will be 1 for each combination of the values of the input variables.
3-to-8 Decoder
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4-to-10 Line Decoder with Inverted Output
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4-to-10 Line Decoder
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n-to-2n line decoder Generate all 2n minterms (or maxterms) of the n input variables Outputs Noninverted i=0,1,2,,2n-1 yi=mi , Inverted yi=mi=Mi , i=0,1,2,,2n-1
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Use decoder and gates to realize a
function Example: Realize the following functions using a

decoder.
f1 (a, b, c, d ) = m1 + m2 + m4 f 2 (a, b, c, d ) = m4 + m7 + m9
Sol:
m2 m4 ) f1 = (m1 m7 m9 ) f 2 = (m4
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Sol:
m2 m4 ) f1 = (m1 m7 m9 ) f 2 = (m4
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Encoder
The inverse function of a decoder

8-to-3 Priority Encoder
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Read-Only Memories
Read-Only Memory (ROM)
Consists of semiconductor devices that interconnected to store binary data
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Read-Only Memories
n m 2 A m ROM can realize m functions
(F1,F2,Fn) of n variables. A ROM consists of a decoder and a memory array.
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Read-Only Memories
Multiple-output combinational circuits
can be realized using ROMs. Example: Realize the following functions using ROM.
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Read-Only Memories
Sol:
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Read-Only Memories
Example: Design a code converter that converts a 4-bit
binary number to a hexadecimal digit and outputs the 7-bit ASCII code.
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Read-Only Memories
, the ROM needs Sol: Because A5 = A4 , A6 = A4
only five outputs. The ROM size is 16 words by 5 bits. The decoder is a 4-to-16 decoder.
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Read-Only Memories
Types of ROMs Mask-programmable ROMs Programmable ROMs (PROMs) Electrically Erasable Programmable ROMs (EEPROMs, E2PROMs) Flash memories Flash memory has built-in programming and erase capability so that data can be written to it while it is in place in a circuit without the need for a separate programmer.
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()

Text: Charles H. Roth, Jr.

Fundamentals of Logic Design

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Digital Systems and Switching Circuits

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Digital Systems and Switching Circuits

Design of digital systems

Digital Systems and Switching Circuits

form of a switching network

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AND, OR, and NOT (complement, or inverse).

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Omit the symbol ., A . B=AB

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Exclusive-OR and Equivalence Operations

Truth table and gate for X Y

X Y =1 if and only if X=1 or Y=1 and X and Y are not both 1.

Exclusive-OR and Equivalence Operations

The truth table for X Y is

Exclusive-OR and Equivalence Operations

Alternate symbol for the equivalence gate

The equivalence gate is also called an exclusive-NOR gate.

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NAND and NOR Gates

n-input NAND gates: n=2 F = ( AB ) = A + B n=3 F = ( ABC ) = A + B + C

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NAND and NOR Gates

n-input NOR gates: n=2 F = ( A + B ) = AB n=3 F = ( A + B + C ) = ABC

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Boolean Expressions and Truth Tables

ParenthesesComplentationANDOR Circuits for expressions

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( A + B)(C + D + E )( A + C + E ) , ABC ( D + E ) are in POS form, (A + B)(C + D) + EF is not in POS form.

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Combinational Logic Design Using a Truth Table

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Combinational Logic Design Using a Truth Table

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Combinational Logic Design Using a Truth Table

f = ABC + ABC + ABC

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Minterm and Maxterm Expansions

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Minterm and Maxterm Expansions

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Minterm and Maxterm Expansions

Standard sum of products

Examples: f ( A, B, C ) = ABC + ABC + ABC + ABC + ABC

Minterm and Maxterm Expansions

Standard product of sums

Minterm and Maxterm Expansions

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Incompletely Specified Functions

The function F is incompletely specified.

Incompletely Specified Functions

F = m(0,3,7) + d (1,6) F = M (2,4,5) D (1,6)

F = ABC + ABC + ABC + ABC = AB + BC

F = ABC + ABC + ABC+ ABC + ABC= AB + BC+ AB

Examples of Truth Table Construction

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